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HCC Overview. Mitch Newcomer for Francis Anghinolfi , Michelle Key Charriere , Joel Dewitt, Nandor Dressnandt , Amogh Halgeri , Paul Keener, Daniel Lamarra , Aditya Narayan . HCC Block Diagram (2012). 2 bits GPIO. HCC ASIC. Interface ASIC between: - PowerPoint PPT Presentation

Transcript of HCC Overview

HCC Overview

HCC OverviewMitch Newcomer for Francis Anghinolfi, Michelle Key Charriere, Joel Dewitt, Nandor Dressnandt, Amogh Halgeri, Paul Keener, Daniel Lamarra, Aditya Narayan

HCC Block Diagram (2012)

2 bits GPIO HCC ASICInterface ASIC between:ABC130 front end readout ASICs grouped in sensor determined units (Hybrid)High speed control/readout provided by the GBT servicing groups of Hybrids.GBT generated Control Signals - differential signals delivered over multi-drop bus.BC 40MHz clock BC Phase encoded control signalsCMD_L0 - CMD (rising edge) and L0 (falling edge) on common diff. pair.

CMD - (40MHz data Rate) - used internally to set operational modes and control readback of status information and regenerated to send to ABC.L0 - (40MHz data rate)Received and regenerated, delayed to ABC130s.

R3_L1 - R3 Rising edge and L1 falling edge on common diff. pair.

R3 Regional Readout Request 26 bits - 3bits start, 14 bits module pos.,8bits L0ID, 1bit trailL1 -- Readout L1 12 bits- 3bits start, 8bits L0ID, 1bit trail

HCC ASIC Hybrid Side Control SignalsBC Hybrid Delayed version of BC that may be ePll synthesized CMD_L0 - Delayed, otherwise unchanged, broadcast to ABC130s on hybrid.R3s_L1 - Module selection bits stripped from R3 to make R3s and L1 R3s_L1 delayed, Broadcast to ABC130s on Hybrid. DRC - ePLL synthesized 80 or 160MHz Data Rate Clock

HCC Data Out - Point to point, programmable current differential drive with pre-emphasis. 160Mbps baseline Barrel (26hybrids*160Mbps ~4.2GBPS/GBT) 320Mbps upgraded or multiple GBTs

Pad ring collaboratively designed with hybrid designers

HCC Layout (2014)Sides Mirrored for symmetric BondingSides Mirrored for symmetric Bonding 4700um x 2860um 83 I/O padsDual pad-ringList of major Blocks DigitalCommand Decoder / R, W, read&clear registersData ConcentratorCoarse / Fine Delay, Half Fine delay Mixed Analog and DigitalePll (CERN GBT) Heart of HCC design BandGap (CERN GBT) Unresolved extracted NL( powerup ~1.2V) issue. Voltage Regulator (CERN/Penn) Analog MonitorI/O Receiver with Hysteresis160MHz DriverPre Emphasis Driver ( Extracted NL shows good perf to 800MHz )

ePllePll Block diagramFilip Tavernier - CERN80 *
















337.5 VCO 320 MHzPFDePllReference (0/40/80/160 MHz)CPLPF40/80/160 MHzePll320MHzA/B/CePllPhase320MHzA/B/C[3:0]ePllEnablePhaseA/B/C[7:0]ePllPhase160MHzA/B/C[4:0]ePllResetA/B/CePllCapA/B/C[1:0]ePllResA/B/C[3:0]ePllIcpA/B/C[3:0]LockDetectorePll Instant LockePllReferenceFrequencyA/B/C[1:0]ePllPhaseShifterFeedback ClockePll160MHz AePll160MHz BePll160MHz C

Measurements of ePll @CERN

Guidance to HCC group for choice ofDefault SetupGuidance to HCC group for choice ofDefault Setup

Design Team: Sandro Bonacini, Rui Reancisco, Paulo Moriera, Karolina Poltorak

ePll measurements Filip Tavernier

Design Specific VerificationFunctional Test Bench created by Joel Dewitt (UCSC) HCC instantiated with wires (named nets) Initialized and run through a task driven input file.

Generalized investigation using graphics interface eg. simvision Function Specific tests results listed in output stream.

Design Verification using the Test Bench

L0 sampled at the falling edge of the clk.

The CMD signal is sampled at the rising edge of the clkBCBCL0L0 RegisteredCMD RegisteredCMDHCC Hybrid Level Verification Michelle Key Charriere (RAL) Test Bench generated Command SignalsHybridABC130HCC HCC DATA OUT Verification EngineCompatibility of Control Signals? Margin? Clock / PLL phasing Delay Generation Data thru-put? Congestion? Data Fidelity

Data, Delays, PileupTest Bench inputBC, CMD_L0,R3_L1BC, DRC CMD_L0, R3s_L1Data OutLoopData, Xon/offBC_Stave Jitter Study Pointed out the benefit of a PLL synth. BC to Hybrid Project File Management (SVN)All official project files are stored in a CERN-hosted SVN code repositoryRTL verilog, test benches, synthesis / P&R scriptsCadence libraries for macro cells, placeholder verilog blocks, .lib file etc.Enables designers to work in parallel with common base designEnables change tracking and backtrackingExpanded HCC Features/Description

Nandor DressnandtHCC FunctionalityReceive data/clock from GBT (Stave Side BC_STAVE clock, phase encoded data L0_CMD, R3_L1)Adjust data/clock delays to account for physics - particle time of flight differences at different locations in the detector. Programming delay macros and ePLL can achieve more than a full period delay for all clocks (40MHz, 160MHz, 320MHz, 640MHz)Remove Hybrid address from R3_L1 data packet to generate R3s_L1 only when hybrid is addressedProvide BC (40MHz) clock and data (R3s_L1, L0_CMD) to Hybrid chips (ABC130s)Provide ePll generated 160MHz Data Readout Clock (DRC) to Hybrid chipsReceive data from Hybrid chips with Xoff mechanismEncode data into serial stream and send back to GBT at 320MHzProvide debugging start-up mode at 40MHz

Implement Fail-Safe Interlock to protect Hybrid chips Autonomous MonitorMonitor Temp, Voltage, CurrentAutomatically turn off clocks and/or power to ABC130 chips if necessary Provide two (programmable) clocking modes: Use received 40MHz GBT clock (BC_STAVE) to sample data and pass along to Hybrids Ok if have high quality GBT clock/data missing pulse or glitch will invalidate dataNever any start-up phasing issues w.r.t GBT dataUse ePLL- generated clock to resample data and pass along to HybridsTolerant to corrupted GBT clock (missing pulses or glitches)But Sensitive to phasing issues w.r.t. GBT data phase checking/correction logic requiredNOTE: Command Decoder must always run on BC_STAVE. (ePLL clock is not available during startup)Unclear how Data Concentrator performs when missing 160/320MHz clock??HCCFeaturesCommon Chip Ground Reference (GND 9 pads)Unregulated Voltage DVDD 4 padsRegulated Voltage VDD 5 pads (Used to bypass regulator for testing)Digital comparator (DFF) to test analog part of delay-chain in Delay MacrosPad to monitor PCB ground-reference (weakly coupled to HCC ground GND)6 Test pads: Bandgap voltage, maybe ePll control voltage, other?? Duplicated pads left/right to fit onto left/right flavor HybridsSEU tolerance: Key registers are triplicatedBF Moat free except for one Macros: prompt circuit (Detects Nuclear detonation)Pre-emphasis driver to compensate for data degradation over Stave transmissionline to GBT - programmableStave-side data receivers have hysteresis to permit AC coupling of Stave signals. No hysteresis in stave clock receiver (BC_STAVE) avoids duty cycled degradationABC130 Data receivers have programmable (2x40) 80 Ohms termination to accommodate adding external termination if desired.Components (* = used in ABC130 chip)Delay elements (coarse/fine, fine, very-fine)I/O Drivers/Receivers *ePLLAutonomous MonitorBandGap, RC filter, and Regulator * HV monitoring OpAmp (4 scales to monitor leakage)Temperature monitoring OpAmp (Diode based)Power-on Reset *Prompt circuits *

Hybrid Controller Chip (HCC) Size: 4700um x 2860um; I/O pads: 83Dual pad-ring structure to fit onto HybridIBM Standard Cells: ~20,000 + 727 Decoupling caps (200pF total)Nets: 22,942Macros:Voltage RegulatorBand GapPLL /w 160, 320, and 640MHz (Modified GBT ePLL)Delay Macos: Synchronous coarse delays (6.25ns/steps )Asynchronous fine delays (1.2ns/steps)Asynchronous half-fine delays (600ps/step)Asynchronous very fine delay (200ps steps)Coarse + fine delays used for Hybrid-side signals (BC_Hybrid, R3sL1, CMDL0)half-fine delays used for Data Readout Clock (DRC) and returning ABC130 Data Very fine delay used for Phase delay of 640MHz Fast Cluster Finder ClockAutonomous Monitor (monitors chip health)Power-on ResetPrompt event circuit (USA export regulations)TCL script driven PnR (based on CERN code ) ~ 3600 lines of codeVerification: Verilog, STA (RC, Encounter), Spectre