Gemini Circuit Reference

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Gemini Circuit Reference for POP-21408-001 B

Originator: Jason Bridger

Date Created: Mar. 16, 2009

Department: MFG Training

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Last Revised By: Jason Bridger

Revision #: 1.0.1

Last Date Revised: Mar. 19, 2009

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POP-21408-001 B – Gemini with WLAN

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1.0 Revisions Description: Rev: Date: Name:

Initial Draft Release to Production 1.0.0 Mar. 16, 2009 Jason Bridger

Second Draft

• Updated graphics to correctly reflect POP-21408-001 B

• Completed WLAN section information

1.0.1 Mar. 19, 2009 Jason Bridger

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2.0 Table of Contents

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3.0 Gemini Overview

3.1 Specifications

3.2 Features

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4.0 Quad Band GSM/EDGE Radio

4.1.0 GSM/EDGE Antenna and Front End Module (PA) Schematic (See Page 2, SCH-21408-001_revB.pdf)

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4.1.1 GSM/EDGE Antenna and Front End Module Placement Diagram, SH401 (See Page 2, POP-21408-001_revB.pdf)

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4.1.2 GSM/EDGE Antenna and Front End Module (PA) Information and Reference

RF Signal Lines:

Line Designation Reference Description

GSM_RF_CONN_IN C233 (DNP) Signal on S201 (RF Spring Contact) side of SW201 (GSM BLT RF Interface)

Good location to check the signal leaving SW201

GSM_RF_CONN_OUT C211 (DNP) Signal on U201 (GSM Front End) side of SW201 (GSM BLT RF Interface)

Good location to check the signal leaving U201

CAUTION! RF Coaxial Connectors (SW201) and RF Spring Contacts (S201) are Easily Damaged, Do Not Probe These Contacts!

HB_OUT / GSM_TX_HB_IN C224 High Band (DCS1800/PCS1900) signal from U402 (GSM Transceiver) to U201 (GSM Front End)

dBm varies based on Power Control Level (PCL) required

LB_OUT / GSM_TX_LB_IN C220 Low Band (GSM850/GSM900) signal from U402 (GSM Transceiver) to U201 (GSM Front End)


RX850, RX900, RX1800, RX1900 No Access RX signals from U201 (GSM Front End) to FL401 (GSM SAW Filter Bank)

Voltage Supplies:


VBAT C235 3.8V (Approx.), Voltage supplied directly from battery

GSM_PA_VBATT2 C234 3.8V (Approx.), Voltage supplied directly from battery Supplies the Power Amplifier (PA) control circuitry

GSM_PA_VBATT3 C204 3.8V (Approx.), Voltage supplied directly from battery May supply the Low Band (LB) internal Power Amplifier (PA), unconfirmed

GSM_PA_VBATT4 C202 3.8V (Approx.), Voltage supplied directly from battery Supplies the High Band (HB) internal Power Amplifier (PA)

GSM_PA_VBATT5 C243 3.8V (Approx.), Voltage supplied directly from battery Supplies the Power Amplifier (PA) control circuitry

V2_7RF_A R415 2.8V, Supplied by U401 (2.8V LDO) Supplies the Power Amplifier (PA) control circuitry

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I/O Signal Lines and Clocks:


IPC_BCM C242 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the radio mode, GMSK (1) or EDGE (0)

LB_HB C241 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects High Band (HB = 1) or Low Band (LB = 0) for RX/TX functions

TX_ANT_SW_EN C240 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End)

Enables U201 (GSM Front End) to transmit

TX_EN No Access 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End)

Enables the Power Amplifier (PA) on U201 (GSM Front End)

US_EURO No Access 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the US (850/1900MHz = 0) or EUROpean (900/1800MHz = 0) bands for RX functions

VDETECT C214 RF power detector linear output from U201 (GSM Front End) to U402 (GSM Transceiver) 1.25V @ 10dBm (RF output power), 2.0V @ 30dBm (RF output power), 40mV/dBm slope

VRAMP C213

Power Amplifier (PA) control voltage from U402 (GSM Transceiver) to U201 (GSM Front End) Controls output power for GMSK modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 0.1V to 2.1V, -10dBm ≤ POUT ≤ 33.0dBm POUT range is 5dBm ≤ POUT ≤ 33.0dBm, 25dB/V relationship DCS/PCS (1800MHz & 1900MHz): VRAMP range is 0.1V to 2.1V, -10dBm ≤ POUT ≤ 32.0dBm POUT range 0dBm ≤ POUT ≤ 32.0dBm, 25dB/V relationship Sets bias conditions for EDGE modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 27.0dBm, Error Vector Magnitude (EVM) is ≤ 5% DCS/PCS (1800MHz & 1900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 26.0dBm, Error Vector Magnitude (EVM) is ≤ 5%

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Key Components:

Reference RIM Part Number Description

FL401 FIL-00231-001 850 / 900 / 1800 / 1900 MHz SAW Filter Bank for Receiver

U201 ANA-00515-001 Skyworks GSM/GPRS/EDGE Power Amplifier Front End Module

U401 ANA-00641-001 2.8V Ultra Low Noise, Dual 200mA Linear Regulator (LDO)

U402 ANA-00485-002 (No Datasheet on Matrix) Freescale GSM / GPRS / EDGE Transceiver

Notes and Applications:

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4.2.0 GSM/EDGE Transceiver Schematic (See Page 4, SCH-21408-001_revB.pdf)

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4.2.1 GSM/EDGE Transceiver Placement Diagram, SH401 (See Page 2, POP-21408-001_revB.pdf)

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4.2.2 GSM/EDGE Transceiver Information and Reference

RF Signal Lines:


RX850, RX900, RX1800, RX1900 No Access RX signals from U201 (GSM Front End) to FL401 (GSM SAW Filter Bank)

GSM_RF_..._P, GSM_RF_..._N No Access Differential RX signals from FL401 (GSM SAW Filter Bank) to U402 (GSM Transceiver)

HB_OUT C224 (Near U201)

High Band (DCS1800/PCS1900) signal from U402 (GSM Transceiver) to U201 (GSM Front End)


LB_OUT C220 (Near U201)

Low Band (GSM850/GSM900) signal from U402 (GSM Transceiver) to U201 (GSM Front End)


Voltage Supplies:


V1_8DIG SM0 Bus 1.8V Main SM0 Supply Bus from U901 (Power Management)

V1_8DIG R411 1.8V, Supplies RF_ON_ENABLE signal line

V1_8DIG C404 1.8V, Supplies U402 (GSM Transceiver) digital I/O and digital RF processing sections

V1_8DIG C428 1.8V, Supplies U406 (Buffer)

V2_7TCXO C423 2.8V, Supplied by U401 (2.8V LDO) Supplies the 52MHz TCXO

V2_7RF_A C402 2.8V, Supplied by U401 (2.8V LDO) Supplies the 52MHz TCXO and U201 (GSM Front End)

VSYS SM2 Bus 2.85V Main SM2 Supply Bus from U901 (Power Management)

VSYS C401 2.85V, Supplies U401 (2.8V LDO)

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AUX_CLK No Access Line Not Used

BT_CLK N/A Line Not Used

BT_CLK_REQ N/A Line Not Used

CLK_ON R409 (SH1001)

1.8V, Enable line from U601 (BB Processor)

Enables the 26MHz system clock

CNTRLCLK TP410 1.8V, Synchronization clock for control lines

CNTRLDATA TP409 1.8V, Serial data line from U601 (BB Processor) to U402 (GSM Transceiver)

CNTRLEN TP411 1.8V, Enable line from U601 (BB Processor) Enables the I/O control lines on U402 (GSM Transceiver)

DBG_DATA TP413 (SH1001)

1.8V, Data read control line from U402 (GSM Transceiver) to U601 (BB Processor)

DEBUG_DATA TP401 1.8V, RX data line from U402 (GSM Transceiver) to U601 (BB Processor)

IPC_BCM C242 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the radio mode, GMSK (1) or EDGE (0)

LB_HB C241 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects High Band (HB = 1) or Low Band (LB = 0) for RX/TX functions

MARS_EXTAL N/A Line Not Used

MARS_INT TP403

RESETB TP405 0V(0) or 1.8V(1), Active Low, Reset signal from U601 (BB Processor)

Resets U402 (GSM Transceiver)

RF_ON N/A Line Not Used

RF_ON_ENABLE R411 1.8V, Active High, Enable line for U401 (2.8V LDO), pin A2 (V2_7RF_OUT) Permanently tied high by V1_8DIG via R411

RXTXDATA TP406 1.8V, TX data line from U601 (BB Processor) to U402 (GSM Transceiver)

RXTXEN TP407 1.8V, Bidirectional communications line between U601 (BB Processor) and U402 (GSM

Transceiver) for RX and TX enabling.

STROBE TP402 1.8V, Data framing signal for TX and RX data transactions

SYSCLK R419 26MHz, System clock reference to U601 (BB Processor)

Timing reference for transmit and receive operations between U601 (BB Processor) and U402 (GSM Transceiver)

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I/O Signal Lines and Clocks Continued:


TCXO_52MHZ / MARS_XTAL C426 52MHz, Clock signal from X401 (52MHz TCXO) to U402 (GSM Transceiver)

TX_EN No Access 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End)

Enables the Power Amplifier (PA)

TX_ANT_SW_EN C240 (Near U201)

1.8V, Active High, Enable line from U402 (GSM Transceiver) to U201 (GSM Front End)

Enables U201 (GSM Front End) to transmit

USB_CLK / MARS_SYS_CLK R420 26MHz, System clock reference for U1404 (USB Transceiver), gated by U1405 (AND Gate)

US_EURO No Access 0V(0) or 1.8V(1), Signal line from U402 (GSM Transceiver) to U201 (GSM Front End) Selects the US (850/1900MHz = 0) or EUROpean (900/1800MHz = 0) bands for RX functions

V2_7_TCXO_EN No Access 1.8V, Active High, Enable line from U402 (GSM Transceiver) to U401 (2.8V LDO) Enables the output at pin C2 (V2_7TCXO) on U401 (2.8V LDO)

VDETECT C214 Linear output from U201 (GSM Front End) RF power detector to U402 (GSM Transceiver) 1.25V @ 10dBm (RF output power), 2.0V @ 30dBm (RF output power), 40mV/dBm slope

VRAMP C213

Power Amplifier (PA) control voltage from U402 (GSM Transceiver) to U201 (GSM Front End) Controls output power for GMSK modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 0.1V to 2.1V, -10dBm ≤ POUT ≤ 33.0dBm POUT range is 5dBm ≤ POUT ≤ 33.0dBm, 25dB/V relationship DCS/PCS (1800MHz & 1900MHz): VRAMP range is 0.1V to 2.1V, -10dBm ≤ POUT ≤ 32.0dBm POUT range 0dBm ≤ POUT ≤ 32.0dBm, 25dB/V relationship Sets bias conditions for EDGE modulated signals: EGSM (850MHz & 900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 27.0dBm, Error Vector Magnitude (EVM) is ≤ 5% DCS/PCS (1800MHz & 1900MHz): VRAMP range is 1.8V to 2.1V POUT is fixed at 26.0dBm, Error Vector Magnitude (EVM) is ≤ 5%

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Key Components:


FL401 FIL-00231-001 850 / 900 / 1800 / 1900 MHz SAW Filter Bank for Receiver

U201 ANA-00515-001 Skyworks GSM/GPRS/EDGE Power Amplifier Front End Module


U402 ANA-00485-002 (No Datasheet on Matrix) Freescale GSM / GPRS / EDGE Transceiver

U406 DIG-00151-001 Dual Buffer

U601 DIG-00179-004 Baseband Processor (Argon LV)

U901 ANA-00614-006 BQ Huge Power Management IC

U1404 ANA-00533-002 USB / Mass Storage Controller

U1405 DIG-00213-001 Dual AND Gate

X401 XTL-00035-001 52.000000MHz Voltage Controlled Crystal Oscillator


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4.3.0 GSM/EDGE 52MHz TCXO Schematic (See Page 4, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

4.3.1 GSM/EDGE Temperature Sensor Schematic (See Page 4, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

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4.3.2 GSM/EDGE 52MHz TCXO Placement Diagram (See Page 2, POP-21408-001_revB.pdf and POP-21407-001_revB.pdf)

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4.3.3 GSM/EDGE 52MHz TCXO Information and Reference

Voltage Supplies:



V1_8DIG C417 1.8V, Supplies U403 (52MHz TCXO DAC) digital I/O

V2_7RF_A R407 2.8V, Supplied by U401 (2.8V LDO) Supplies the bias voltage for RT401 (Thermistor)

V2_7TCXO / TCXO_DAC_VDD R405 2.8V, Supplied by U401 (2.8V LDO) Supplies VDD and positive voltage reference for U403 (52MHz TCXO DAC)

V2_7TCXO / VCC_TCXO_52MHZ C415 2.8V, Supplied by U401 (2.8V LDO) Supplies X401 (52MHz Crystal)



AFC_DAC_FRM TP408 1.8V, Active Low, Signal from U601 (BB Processor) to U403 (52MHz TCXO DAC)

Signals the beginning of a serial data frame for U403 (52MHz TCXO DAC)

EDGE_CTL_AFC_CTL_CLK TP410 1.8V, Control line synchronization clock from U601 (BB Processor)

Note: Also known as CNTRLCLK

EDGE_CTL_AFC_DO TP409 1.8V, Serial data input from U601 (BB Processor) to U403 (52MHz TCXO DAC)

Note: Also known as CNTRLDATA

TCXO_DAC_OUT/TCXO_52MHZ_VCON R404 Control line from U403 (52MHz TCXO DAC) to X401 (52MHz Crystal) Provides feedback to U403 (52MHz TCXO DAC)

TCXO_TEMP C419 Outputs a voltage representation of the TCXO temperature to U901 (Power Management)

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Key Components:


RT401 RES-10017-001 47kΩ Thermistor, part of Temperature Compensation System


U403 ANA-00311-001 12bit Voltage Output DAC



X401 XTL-00035-001 52.000000MHz Voltage Controlled Crystal Oscillator


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5.0 Bluetooth (BT) Section

5.1.0 Bluetooth Transceiver and Antenna Schematic (See Page 5, SCH-21408-001_revB.pdf and SCH-21407-001_revB.pdf)

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5.1.1 Bluetooth Transceiver and Antenna Placement Diagram (See Page 2, POP-21408-001_revB.pdf and POP-21407-001_revB.pdf)

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5.1.2 Bluetooth Information and Reference

RF Signal Lines:


RF_BT C232 Signal at BT Antenna (After TP203)

Note: RF_BT is the same as BT_ANT

BT_ANT C523 Signal from BT Antenna to FL501 (BT Filter) Note: BT_ANT is the same as RF_BT

CAUTION! RF Spring Contacts (TP203) are Easily Damaged, Do Not Probe These Contacts!

BT_RF_N No Access Differential signal from FL501 (BT Filter) to U501 (BT Transceiver)

BT_RF_P No Access Differential signal from FL501 (BT Filter) to U501 (BT Transceiver)

Voltage Supplies:


1.5VPOWERPLANE C509 1.5V, Supply from U501 (BT Transceiver) internal 1.5V regulator to FL501 (BT Filter)

Also supplies BT_VDD_CORE

BT_VDD_CORE C510 1.5V, Supply from U501 (BT Transceiver) internal 1.5V regulator to U501 internal circuitry


V1_8DIG C521 (DNP) 1.8V, Supplies U501 (BT Transceiver) digital I/O

V1_8DIG / BT_VREG_IN C504 (DNP) 1.8V, Supplies U501 (BT Transceiver) internal 1.5V regulator



BT_ACTIVE TP503 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Signals U1501 (WLAN) that U501 (BT Transceiver) is actively transmitting

BT_CLK C522 (DNP) 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO) Same as TCXO_26MHZ

BT_CLK26M N/A Line Not Used

BT_CLK_REQ R505 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) to U1508 (OR Gate) Signals U1508 (OR Gate) to assert a high on TCXO_VCC_EN (in WLAN Section)

Enables TCXO_26MHZ / BT_CLK

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BT_FREQ TP515 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth reserved channel indication

BT_LO_REF C511 Reference voltage decoupling

BT_PRIORITY TP502 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth priority signal

BT_RSTB R508 1.8V, Active Low, BT Reset Permanently tied high by V1_8DIG via R508

BT_SPI_CLK TP506 Line Not Used

BT_SPI_CSB TP505 Line Not Used

BT_SPI_MISO TP508 Line Not Used

BT_SPI_MOSI TP507 Line Not Used

BT_UART_CTS TP513 1.8V, Active Low, UART clear to send line from U601 (BB Processor)

BT_UART_RTS TP514 1.8V, Active Low, UART request to send line to U601 (BB Processor)

BT_UART_RX R510 1.8V, Active High, UART RX communications data line from U601 (BB Processor)

BT_UART_TX R509 1.8V, Active High, UART TX communications data line to U601 (BB Processor)

BT_VREG_EN C504 (DNP) 1.8V, Active High, Enable line Enables U501 (Bluetooth) internal voltage regulators

PCM_CLK TP509 1.8V, Pulse Code Modulation (PCM) clock reference from U601 (BB Processor)

PCM_IN TP511 1.8V, Pulse Code Modulation (PCM) audio data from U601 (BB Processor)

PCM_OUT TP510 1.8V, Pulse Code Modulation (PCM) audio data to U601 (BB Processor)

PCM_SYNC TP512 1.8V, Pulse Code Modulation (PCM) frame synchronization signal

WLAN_ACTIVE TP504 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Disables U501 (BT Transceiver) when WLAN is active

TCXO_26MHZ R516 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO)

Same as BT_CLK

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Key Components:


FL501 FIL-00271-001 Bluetooth Bandpass Filter 2450MHz ±50MHz


U1501 ANA-00537-002 WLAN Transceiver (MAC Baseband Processor)

U1508 DIG-00193-001 Dual OR Gate

X1501 XTL-00018-001 26.0MHz Crystal Oscillator for WLAN TCXO


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6.0 Global Positioning System (GPS) Section

Gemini POP-21408-001 B does not support GPS functionality.

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7.0 Wireless b/g LAN (WLAN) Section

7.1.0 WLAN Antenna Schematic (See Page 2, SCH-21408-001_revB.pdf )

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7.1.1 WLAN Transceiver and Front End Module (PA) Schematic (See Page 15, SCH-21408-001_revB.pdf )

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7.1.2 WLAN Transceiver (Power) and 26MHz TCXO Schematic (See Page 15, POP-21408-001_revB.pdf )

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7.1.3 WLAN Power Management IC (PMIC) Schematic (See Page 15, POP-21408-001_revB.pdf )

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7.1.5 WLAN Section Placement Diagram (See Page 2, POP-21408-001_revB.pdf )

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7.1.6 WLAN Information and Reference

RF Signal Lines:


GPS_WLAN_RF_CONN_IN C236 Signal from GPS/WLAN Antenna (After TP204, Before SW202)

GPS_WLAN_RF_CONN_OUT R216 Signal from GPS/WLAN Antenna (After SW202)

CAUTION! RF Coaxial Connectors (SW202) and RF Spring Contacts (TP204) are Easily Damaged, Do Not Probe These Contacts!

WLAN_ANT_2G R213 Signal from Antenna to FL1501 (SAW Filter)

WLAN_RF_IO L1502 Signal from FL1501 (WLAN SAW Filter) to U1502 (WLAN Front End)

WLAN_RF_RXN / WLAN_RF_RXP No Access Received Signal, Differential outputs to U1501 (WLAN Transceiver)

WLAN_RF_TXN / WLAN_RF_TXP No Access Transmitted Signal, Differential inputs from U1501 (WLAN Transceiver)

Voltage Supplies:


V1_2WLAN C1509 1.2V, Supply from U1506 (WLAN Power IC) to U1501 (WLAN Transceiver) VDD12 inputs


V1_8DIG C1511 1.8V, Supplies U1501 (WLAN Transceiver) VDDIO inputs

V1_8DIG C1512 1.8V, Supplies U1501 (WLAN Transceiver) VIOXIO input

V1_8DIG No Access 1.8V, Supplies U1506 (WLAN Power IC) VIO input

V1_8DIG No Access 1.8V, Supplies U1501 (WLAN Transceiver) NC input

V1_8DIG No Access 1.8V, Supplies U1504 (OR Gate)

V1_8DIG No Access 1.8V, Supplies U1508 (OR Gate)

V1_9WLAN C1505 1.9V, Supply from U1506 (WLAN Power IC) to U1501 (WLAN Transceiver) VDD19 inputs

VPWR_SYS ?V, Supply Bus from U901 (Power Management)

VPWR_SYS C1520 ?V, Supplies U1506 (WLAN Power IC)

VSYS SM2 Bus 2.85V Main SM2 Supply Bus from U901 (Power Management)

VSYS C1515 2.85V, Supplies U1506 (WLAN Power IC)

VSYS C1521 2.85V, Supplies U1507 (2.85V LDO)

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ABAND No Access 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Signals U1506 (WLAN Power IC) to switch on U1502 (WLAN Front End)

BT_ACTIVE TP503 (Near U501)

0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Signals U1501 (WLAN Transceiver) that U501 (BT Transceiver) is actively transmitting

BT_CLK_REQ R504 (DNP) 0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) to U1508 (OR Gate) Signals U1508 (OR Gate) to assert a high on TCXO_VCC_EN

BT_FREQ TP515 (Near U501)

0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth reserved channel indication

BT_PRIORITY TP502 (Near U501)

0V(0) or 1.8V(1), Active High, Signal line from U501 (BT Transceiver) Bluetooth priority signal

STBY No Access 1.8V, Active High, Puts U1506 (WLAN Power IC) into ‘standby mode’ (all LDO’s on)

TCXO_26MHZ C1523 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO)

TCXO_26MHZ_VCC C1522 2.8V, Supplies X1501 (WLAN TCXO)

TCXO_VCC_EN R1504 (DNP) 0V(0) or 1.8V(1), Active High, Signal line from U1508 (OR Gate) Enables U1507 (2.85V LDO) to turn on X1501

VDB C1501 Supply from U1506 (WLAN Power IC) to U1502 (WLAN Front End) VLNA input Controls U1502 (WLAN Front End) LNA bias

VDPA C1503 High current supply from U1506 (WLAN Power IC) to U1502 (WLAN Front End) VPA inputs Controls U1502 (WLAN Front End) PA bias

WLAN_26MHZ_TCXO C1508 0.8Vp-p to 1.5Vp-p 26.0MHz clipped sine wave, Clock signal from X1501 (WLAN TCXO)

Provides the clock signal reference for U1501 (WLAN Transceiver)

WLAN_ACTIVE TP504 0V(0) or 1.8V(1), Active High, Signal line from U1501 (WLAN Transceiver) Disables U501 (BT Transceiver) when WLAN is active

WLAN_ACTIVITY No Access 1.8V, Output from U1504 (OR Gate) Active when WLAN_LNAEN or WLAN_PAEN is asserted high Signals U601 (BB Processor) that the WLAN LNA or PA are enabled

WLAN_DETN / WLAN_FE_DETN No Access Negative RF power detector output from U1502 (WLAN Front End)

WLAN_DETP / WLAN_FE_DETP No Access Positive RF power detector output from U1502 (WLAN Front End)

WLAN_EN TP1503 0V(0) or 1.8V(1), Active High, Signal line from U601 (BB Processor) Enables or disables U1506 (WLAN Power IC) and the WLAN subsystem

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WLAN_HFCLK_EN R1505 1.8V, Active High, Enables the WLAN 26.0MHz TCXO via U1508 (OR Gate)

Signals U601 (BB Processor)

WLAN_INT No Access Interrupt signal from U1501 (WLAN Transceiver) to U601 (BB Processor)

WLAN_LFCLK No Access 32.768kHz slow clock signal from U901 (Power Management) to U1501 (WLAN Transceiver) Signal is called EXT_32K at U901 (Power Management)

WLAN_LNAEN No Access 1.8V, Active High Signal from U1501 (WLAN Transceiver) to U1506 (WLAN Power IC) and U1504 (OR Gate)

Enables WLAN_ACTIVITY and the LNA in U1502 (WLAN Front End)

WLAN_PAEN No Access 1.8V, Active High Signal from U1501 (WLAN Transceiver) to U1506 (WLAN Power IC) and U1504 (OR Gate)

Enables WLAN_ACTIVITY and the PA in U1502 (WLAN Front End)

WLAN_RESET_N No Access 0V(0) or 1.8V(1), Active Low, Reset line from U601 (BB Processor)

Resets U1506 (WLAN Power IC), U1501 (WLAN Transceiver) is reset via the WLANRS signal line

WLAN_REXT R1503 External reference, datasheet does not specify the purpose

WLAN_SD_CLK No Access 1.8V ?MHz, SD clock from U601 (BB Processor) to U1501 (WLAN) Note: Line is called WLAN_CLK at U601

WLAN_SD_CMD No Access 1.8V, SD command I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver)

Note: Line is called WLAN_CMD at U601

WLAN_SD_DAT0 No Access 1.8V, SD data I/O line to/from U601 (BB Processor) and U1501 (WLAN Transceiver)

Note: Line is called WLAN_DAT0 at U601







WLAN_VSW_OUT C1516 Routes output from U1506’s (WLAN Power IC) internal switching power supply pin A1 (VSW) to the switcher input to the chips internal LDO’s pin E1 (VFB)

WLANRS No Access Active Low, Resets U1501 (WLAN Transceiver)

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Approvals:

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Note: There are currently no fixtures or engineering software tools provided to support the following debug lines:

WLAN_GPIO8 R1502 Debug UART transmit, Pulled Low by R1502

WLAN_RS232_RX TP1502 Debug RS232 receive line

WLAN_RS232_TX TP1501 Debug RS232 transmit line

WLAN_UART_RX TP1511 Debug UART receive line

Key Components:


FL1501 FIL-00155-001 2.4GHz Bandpass Filter, 100MHz Bandwidth



U1501 ANA-00537-002 WLAN Transceiver (MAC Baseband Processor)

U1502 ANA-00358-003 WLAN Front End Module


U1506 ANA-00355-004 WLAN Power Management IC

U1507 ANA-00463-001 2.85V 150mA Linear Regulator (LDO)


X1501 XTL-00018-001 26.0MHz Crystal Oscillator for WLAN Transceiver Generates 26.0MHz clock signal at 0.8Vp-p to 1.5Vp-p

Confidential





Approvals:

Document #:


Revision #: 1.0.1


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Gemini Circuit Reference

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