FUNDAMENTALS OF DIGITAL COMPUTERS - … · and then construct the logic circuit. SAU1A t...

SAU1A

FUNDAMENTALS OF

DIGITAL COMPUTERS

Unit : I - V

Unit : I – Overview

Fundamentals of Computers

Characteristics of Computers

Computer Language

Operating Systems

Generation of Computers

2 SAU1A– Fundamentals of Digital Computers

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A computer is an electronic device that operates under the control of a set of instructions that is stored in its memory unit. A computer accepts data from an input device and processes it into useful information which it displays on its output device. Actually, a computer is a collection of hardware and software components that help you to accomplish many different tasks. 1. Hardware consists of the computer itself, and any equipment connected to it. 2. Software is the set of instructions that the computer follows in performing a task.

Definition of a Computer

SAU1A– Fundamentals of Digital Computers

4 SAU1A– Fundamentals of Digital Computers 4

Components of a Computer

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1. INPUT DEVICES - Devices that allow the user to enter

information into the PC (keyboard, mouse, scanner, etc.)

2. OUTPUT DEVICES - Devices that allow the computer to

communicate with the user (monitor, printer, etc.)

Functional Components of a Computer


3. CPU - The CPU consists of electronic circuits that interpret and

execute instructions; it communicates with the input, output, and

storage devices.

4. Memory - or primary storage, works with the CPU to hold

instructions and data in order to be processed.

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Shape Name Capacity Drive Letter (usually)

Characteristics

3 ½ Diskette 1.44 Megabytes A: or B: Recordable, Very slow, Tend to lose information easily, Very cheap, Exchangeable, Easy to carry.

Hard Disk Drive

Between 1 and 16 Gigabytes

C: Recordable, Very fast, Boot disk, Safe, Very Expensive.

ZIP or LS-120

Between 100 Megabytes and 1 Gigabyte

D:, E:, F: Recordable, Fast, Safe, Very Expensive, Exchangeable, Easy to carry.

CD-ROM 650 Megabytes (0.65 Gigabytes)

D:, E:, F: Some Recordable (expensive), Capacity for Audio, Very Fast, Very Safe, Cheap , Easy to carry.

DVD-ROM Up to 17 Gigabytes (Up to 17000 Megabytes)

D:, E:, F: New, Capacity for Audio and Video, Very Fast, Very Safe, Very Expensive, Easy to carry.

Storage Devices


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• Speed

• Memory

• Diligence

• Versatility

• Lack of Decision making

Characteristics of a Computer


10

Programming languages can be classified as:

1. Machine language – The only language understood by

computers. It comprises entirely of numbers.

2. Assembly language – Similar to machine languages, but enable

the use of names instead of numbers. Assembly language is converted

to machine language using an interpreter.

3. High-level language – Closer to human languages, easier to read,

write and maintain. High-level language is converted to Assembly

language using a compiler or assembler. Eg. C, C++, Cobol, Fortran,

Java

4. Fourth-generation language – 4GL is more closer to human

languages than typical high-level languages. Most 4GLs are used to

access databases.

Computer Languages


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Computer Language


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• The operating system is the software that provides an interface between the hardware (the computer itself) and the user.

• It manages the hardware and enables the user to control the computer.

• Microsoft developed the first operating system for IBM machines, MS DOS (Microsoft Disk Operating System), the grandfather of the current DOS and Windows systems.

• The IBM family is based on the Intel 8086 family of chips, which evolved into the high-speed Pentium chips of today.

• At the same time, the Apple Computer Company started Macintosh series based on the Motorola 68000 family of microprocessor chips.

Operating System


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• The history of computer development is often referred to in reference to the different generations of computing devices.

• Each generation of computer is characterized by a major technological development that fundamentally changed the way computers operate, resulting in increasingly smaller, cheaper, more powerful and more efficient and reliable devices.

• Based on the above mentioned features, we have five generations of computers.

Generations of Computers

Generations of Computers


https://www.youtube.com/watch?v=sTc4kIVUnoA

15

Unit : II – Overview

Number System

Binary System

Binary Code

Logic Gates


• The larger the base, more the numerals required:

Number System Base Digits or Symbols

included

Binary 2 0,1

Decimal 10 0,1,2,3,4,5,6,7,8,9

Octal 8 0,1,2,3,4,5,6,7

Hexadecimal 16 0,1,2,3,4,5,6,7,8,9,

A,B,C,D,E,F

• For example, a 16-bit PC will have

R = 216 = 65,536 different values.

• The range of possible numbers for each system is

R=BK, where B = Base, K = number of digits


Conversion from Decimal to

other system

Step 1 : Repeatedly, divide the integer part by the

base to which it has to be converted, and collect

the remainders in the reverse direction.

19 / 2 = 9; remainder = 1

9 / 2 = 4; remainder = 1

4 / 2 = 2; remainder = 0

2 / 2 = 1; remainder = 0

1 / 2 = 0; remainder = 1

0.625 x 2 = 1.250; carry = 1

0.250 x 2 = 0.500; carry = 0

0.500 x 2 = 1.000; carry = 1

Thus, (19.625)10 = (10011.101)2

Step 2 : Successively, multiply the fractional part by the base to which it

has to be converted, and collect the carries from top to bottom. If the

fractional part is not zero after 4 or 5 steps, the process can be

stopped.

Examples:

1. Convert (19.625)10 to its binary equivalent.


Conversion from Binary to Octal /

Hexadecimal

Step 1 : Arrange the given number into groups of 3 bits (Octal) or 4

bits (Hexadecimal), starting from the Least Significant Bit (LSB).

If the final group has lesser number of bits, include 0s.

Step 2 : Replace each group with its octal or hexadecimal equivalent,

as required.

Example:

Convert (11110.11)2 to octal and hexadecimal equivalents.

(11110.11)2 = (011 110.110)2

= ( 3 6. 6)8

= (36.6)8

(11110.11)2 = (0001 1110.1100)2

= ( 1 E. C)16

= (1E.C)16


Conversion from Octal / Hexadecimal to

Binary

• These conversions are the simplest of all.

• Replace each octal or hexadecimal digit with its binary equivalent.

Examples:

1. Convert (3D.E8)16 to its binary equivalent.

(3D.E8)16 = (0011 1101. 1110 1000)2

2. Convert (45.5)8 to its binary equivalent.

(45.5)8 = (100 101. 101)2


Binary Arithmetic Rules for Binary Addition

1. 0 + 0 = 0

2. 0 + 1 = 1 ; 1 + 0 = 1

3. 1 + 1 = 0 ; Carry = 1

4. 1 + 1 + 1 = 1 ; Carry = 1

Example:

1. Add 3 and 4.

3 -> 011 Augend

4 -> 100 + Addend -------- ---------------

7 -> 111 Result

2. Add 13 and 7.

1 1 1 1 1

13 -> 1101 Augend

7 -> 111 + Addend --------- -----------------

20 -> 10100 Result


Complements

• There are 2 types of complements used in Binary System, namely 1’s Complement and 2’s Complement.

• Complements are also used to represent negative numbers.

• 1’s Complement: 1’s Complement of a bit can be obtained as 1 minus that bit. i.e. 1’s complement of 1 is 1 – 1 = 0 and

1’s complement of 0 is 1 – 0 = 1.

In general, invert the given bit to get its 1’s complement.

• 2’s Complement: 2’s Complement of a bit is obtained by adding 1 to the 1’s complement of that bit.

i.e. 2’s Complement of 1010 -> 1’s complement of 1010 + 1

-> 0101 + 1 = 0110


Signed Binary Numbers

• To represent the sign of the given number, we will use a separate bit (sign bit). It becomes the MSB of the binary number.

• The bit 0 represents (+) or positive numbers and the bit 1 represents (-) or negative numbers.

• Negative numbers are represented in either of the following ways:

1. Sign-Magnitude – The MSB represents the sign and the remaining

bits represent the magnitude of the number.

Example: +5 = 0 000 0101 +127 = 0 111 1111

-5 = 1 000 0101 -127 = 1 111 1111

Note: Positive numbers are represented only using the sign-

magnitude form


1’s Co ple e t Su tra tio – Contd.

Example 1:

Subtract 4 from 13.

1. 13 -> 1101 ;

4 -> 0100

2. 1’s complement of 4 -> 1011

1101 + 1011

1 1000

3. Adding carry, result is

1001 i.e. +9

Example 2:

Subtract 13 from 4.

1. 4 -> 0100 ; 13 -> 1101


0100 + 0010 0110

3. No carry -> result is negative.

Take 1’s complement of 0110 ->

1001

Thus, result is -9


2’s Complement Subtraction – Contd.

Example 1:

Subtract 4 from 13.

1. 13 -> 1101 ;

4 -> 0100

2. 2’s complement of 4 -> 011 + 1 = 1100

1101 + 1100

1 1001

3. Ignore carry, result is 1001 i.e.

+9

Example 2:

Subtract 13 from 4.

1. 4 -> 0100 ; 13 -> 1101


0100 + 0011 0111

3. No carry -> result is negative.

Take 2’s complement of 0111 -> 1000

+ 1

i.e. 1001. Thus, result is -9


Binary Codes • Codes are alternate representations for the binary numbers.

• Different codes are used for binary numbers. Commonly used are

1. BCD (Binary Coded Decimal) Code

a) 8421

b) 2421

c) 4221

2. Excess-3 Code

3. Gray Code


Logic Gates and Truth Tables • Any logic circuit can be implemented using the following basic

gates:

1. NOT Gate

2. OR Gate

3. AND Gate

• Each of the Gates can be represented schematically, or as an

expression, or as a truth table.

• Other gates can be implemented as a combination of the basic

gates.

• For the given logic circuit, we can get the Boolean expression and

then form the truth table.

• Also for the given truth table, we can get the Boolean expression

and then construct the logic circuit.


NOT Gate

• This function operates on a single Boolean value.

• Its output is the complement of its input.

i.e. Output Y = X’ • An input of 1 produces an output of 0 and an input of 0 produces

an output of 1.

X Y = X’

0 1

1 0

x x'


Output is 1 if at least one input is 1.

More than two values can be “or-ed” together.

For example x + y + z = 1 if at least

one of the three values is 1.

x y

out

=

x+y

0 0 0

0 1 1

1 0 1

1 1 1

x

y

out

AND Gate

• Output is one if every input has value of 1.

• More than two values can be “and-ed” together. • For example xyz = 1 only if x=1, y=1 and z=1.

x y out = xy

0 0 0

0 1 0

1 0 0

1 1 1

x

y

out


NAND Gate

• When the output of AND gate is given as input to the NOT gate (or a bubble can be added to the AND gate), the result circuit is the NAND gate. The output of the NAND gate is the complement of the output of the AND gate.

x y out = (xy)’ 0 0 1

0 1 1

1 0 1

1 1 0

x

y

out


When the output of OR gate is

given as input to the NOT gate

(or a bubble can be added to

the AND gate), the result circuit

is the NOR gate.

The output of the NOR gate is

the complement of the output of

the OR gate.

x y out = (x + y)’ 0 0 1

0 1 0

1 0 0

1 1 0

x

y

out

EX-OR (Exclusive-OR) Gate • The output of the XOR gate is equal to 1, if an odd number of input

values are 1 and 0 if an even number of input values are 1.

x y out =

0 0 0

0 1 1

1 0 1

1 1 0

x

y

out

yx


The output of the XNOR gate is the

complement of the output of the XOR

gate.

x y out =

0 0 0

0 1 1

1 0 1

1 1 0 x

y

out

X

y

z

xy'+yz

Manipulating Boolean Functions

Given Logic Circuit:


• We can express it as:

f(x,y,z) = xy’+ yz

• The truth table is:

x y z xy' yz xy‘ + yz

0 0 0 0 0 0

0 0 1 0 0 0

0 1 0 0 0 0

0 1 1 0 1 1

1 0 0 1 0 1

1 0 1 1 0 1

1 1 0 0 0 0

1 1 1 0 1 1


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Unit : III – Overview

Boolean Algebra

Truth Tables

Universal Gates

Simplification of Boolean functions

Map Methods

Mc-Clausky Tabulation Methods


Boolean Algebra

• Using Boolean laws helps to reduce the given function to a lesser

number of literals. Also a lesser number of gates.

• Result – More efficient and cheaper digital circuits.

• The simplification can be achieved using the various axioms and laws

of Boolean Algebra


Boolean Axioms

Laws similar to Ordinary Algebra

• Commutative Law

A + B = B + A

A . B = B . A

• Associative Law

A + (B + C) = (A + B) + C

A (BC) = (AB) C

• Distributive Law

A (B + C) = AB + AC


Rules specific to Boolean

Algebra

When A = 0

A + 0 = 0 + 0 = 0 = A

When A = 1

A + 0 = 1 + 0 = 1 = A

When A = 0

A . 1 = 0 . 1 = 0 = A

When A = 1

A . 1 = 1 . 1 = 1 = A

2. a) A + 1 = 1 b) A . 0 = 0

When A = 0

A . 0 = 0 . 0 = 0

When A = 1

A . 0 = 1 . 0 = 0

When A = 0

A + 1 = 0 + 1 = 1

When A = 1

A + 1 = 1 + 1 = 1


1. a) A + 0 = A b) A. 1 = A

3. a) A + A = A b) A. A = A

When A = 0

A + A = 0 + 0 = 0 = A

When A = 1

A + A = 1 + 1 = 1 = A

When A = 0

A . A = 0 . 0 = 0 = A

When A = 1

A . A = 1 . 1 = 1 = A

4. a) A + A’ = 1 b) A . A’ = 0

When A = 0

A . A’ = 0 . 1 = 0

When A = 1

A . A’ = 1 . 0 = 0

When A = 0

A + A’ = 0 + 1 = 1

When A = 1

A + A’ = 1 + 0 = 1



Algebra

5. a) A’’ = A When A = 0

A’ = 1 ; A’’ = 0 = A

When A = 1

A’ = 0 ; A’’ = 1 = A

This double complement rule is also known as

Involution



Algebra

6. a) A + AB = A b) A (A + B) = A

L.H.S = A + AB

= A (1 + B) Distributive law

= A . 1 Since, 1 + B = 1

= A Since, A . 1 = A

= R.H.S

L.H.S = A (A + B)

= AA + AB Distributive law

= A + AB Since, AA = A

= A Since, A + AB = A

= R.H.S



Algebra

7. a) A + A’B = A + B b) A (A’ + B) = AB

L.H.S = A + A’B

= A.1 + A’B Since, A.1=A

= A.(1 + B) + A’B Since, 1+B=1

= A + AB + A’B Distributive law

= A + B (A + A’) Distributive law

= A + B Since, A + A’ = 1

= R.H.S

L.H.S = A (A’ + B) = A.A’ + AB Distributive law

= 0 + AB Since, A . A’ = 0

= AB Since, 0 + AB = AB

= R.H.S



Algebra

8. a) A + BC = (A + B) (A + C)

R.H.S = (A + B) (A + C)

= AA + BA + AC + BC

= A + AB + AC + BC Since, A.A=A ; AB = BA

= A (1 + B + C) + BC Distributive Law

= A + BC Since, 1 + A + … = 1 & A.1 = 1

= L.H.S

b) A ( B + C) = AB + AC

This is the Distributive Law.



Algebra

9. a) AB + A’C + BC = AB + A’C

Hint: We need to remove BC from L.H.S

LHS = AB + A’C + BC

= AB + A’C + BC . 1 Since, 1.BC = BC

= AB + A’C + BC (A + A’) Since, A + A’ = 1

= AB + A’C + ABC + A’BC Distributive law

= AB (1 + C) + A’C (1 + B) = AB + A’C = RHS



Algebra

b) (A+B) (A’+C) (B+C) = (A+B) (A’+C) LHS = (A + B) (A’+ C) (B + C) = (AA’ + A’B + AC + BC) (B + C) = (A’B + AC + BC) (B + C) Since, AA’=0

= A’BB + ABC + BBC + A’BC + ACC + BCC

= A’B + A’BC + ABC + BC + AC + BC Since, BB=B

= A’B (1 + C) + BC (A + 1) + AC + BC

= A’B + BC + AC + BC Since, 1+C=1

= A’B + AC + BC

RHS = (A + B) (A’ + C) = AA’ + A’B + AC + BC

= A’B + AC + BC = LHS



Algebra

• The AND and OR functions can be shown to be related to each other through the following equations.

Theorem 1:

“The complement of a product is equal to the sum of individual complements.” In other words,

(AB)’ = A’ + B’ or

NAND = Bubbled OR

Theorem 2:

“The complement of a sum is equal to the product of individual complements.” In other words,

(A + B)’ = A’ . B’ or

NOR = Bubbled AND

Demorgan’s Laws


For Example:

1. Simplify: Find the complement of AB’ + C’D’ and simplify.

Solution: (AB’ + C’D’)’ = (AB’)’ . (C’D’)’

= (A’ + B) . (C’’ + D’’)

= (A’ + B) . (C + D)

2. Show that (A’B + AB’)’ = A’B’ + AB

Solution: LHS = (A’B + AB’)’

= (A’B)’ . (AB’)’

= (A’’ + B’) . (A’ + B’’)

= (A + B’) . (A’ + B)

= AA’ + A’B’ + AB + BB’

= A’B’ + AB Since, AA’ = 0 and BB’ = 0


Universal Gates

• Universal gates are the ones which can be used for implementing

any gate like AND, OR and NOT, or any combination of these basic

gates.

• NAND and NOR gates are universal gates.

• But there are some rules that need to be followed when

implementing NAND or NOR based gates.

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NAND as Universal Gate Any logic function can be implemented using NAND gates.

To achieve this, first the logic function has to be written in Sum of Product

(SOP) form.

Once logic function is converted to SOP, the logic circuit with AND gates in

first level and OR gates in second level can be converted into a NAND-

NAND gate circuit.


Simplification of Boolean functions is mainly used to reduce the gate count

of a design.

• Less number of gates means less power consumption, sometimes the

circuit works faster.

• When number of gates is reduced, cost also comes down.

• There are many ways to simplify a logic design.

1. Algebraic Simplification - Simplify symbolically using theorems.

2. Karnaugh Maps – Simplifies using Diagrammatic technique.

3. Quine-McCluskey – Simplifies using Tabulation technique.

Simplification of Boolean functions


• Karnaugh maps provide a systematic method to obtain simplified sum-of-

products (SOPs) Boolean expressions.

• This is a compact way of representing a truth table and is a technique that

is used to simplify logic expressions.

• It is ideally suited for four or less variables, becoming cumbersome for five

or more variables.

• A K-map of n variables will have 2n squares.

• Each square represents either a minterm or maxterm.

• For a Boolean expression, product terms are denoted by 1's, while sum

terms are denoted by 0's - but 0's are often left blank.

Karnaugh Maps (K-Maps)


A 2-variable K-Map will have 4 cells.

• The function can have 4 possible combinations.

a) 00, 01, 10, 11 or

b) A’B’, A’B, AB’, AB or

c) m0, m1, m2, m3

The K-Map can be drawn in either of the following ways:

2 – Variable K-Map


For example :

F = X'Y+XY+XY'

1. Draw the k-map for function F with marking 1 for X'Y, XY and XY

position.

2. Now combine two 1's as shown in figure to form the two single terms.

F = X + Y



• The function can have 8 possible combinations.

a) 000, 001, 010, 011, 100, 101, 110, 111 or

b) A’B’C’, A’B’C, A’BC’, A’BC, AB’C’, AB’C, ABC’, ABC or

c) m0, m1, m2, m3, m4, m5, m6, m7

The K-Map can be drawn as below:

Using gray code arrangement

ensures that minterms of adjacent

cells differ by only ONE literal.


SAE2B– Digital Electronics & Microprocessor 58

For example :

F(X,Y,Z) = Σ(1,3,4,5,6,7)

1. Draw the k-map for function F with marking 1 for m1, m3, m4, m5, m6

and m7.

2. Now combine 1’s as shown in figure to form the reduced terms.

F = X + Z



• The function can have 16 possible combinations m0 to m15.

The K-Map can be drawn as below:



For example :

F(A, B, C, D) = Σ(0, 1, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

1. Draw the k-map for function F with marking 1 for the given minterms.

2. Now combine 1’s as shown in figure to form the reduced terms.

1 1

1 1

1 1

1 1

1 1

1 1

AB CD

00 01 11 10

00

01

11

10

F = B’ + D


A 5-variable K-Map will have 32 cells – m0 to m31.

• The 5-Variable Map can be drawn as 2 4-variable maps-m0 to m15

and m16 to m31.

• If the reduced expressions for the 2 individual maps is Y1 and Y2, we

can write the final expression as Y = Y1 + Y2.

• If necessary, apply Boolean laws for further simplification.



A = 0

1 1

00 01 11 10

00

01

11

10

1 1

1 1

BC DE

1 1 1

00 01 11 10

00

01

11

10

DE

1 1

1 1

BC

A = 1

• The reduced expressions for

the 2 maps are:

Y1 = AB’C’D’ + AE and Y2 = A’B’D’

For Example: F(A,B,C,D,E) = Σ(0,1,3,5,7,,9,11,13,15,16,17,20,21)

Thus, Y = AB’C’D’ + AE + A’B’D’ = B’D’(A’ + AC’) + AE = B’D’ (A’ + C’) + AE

= A’B’D’ + B’C’D’ + AE


• Represent the expression in the canonical SOP form.

Consider the function F(A,B,C,D) = Σ(0, 1, 4, 5, 10, 11, 14, 15)

Step 1: Represent each minterm in binary as shown:

Decimal Binary

0

1

4

5

10

11

14

15

0 0 0 0

0 0 0 1

0 1 0 0

0 1 0 1

1 0 1 0

1 0 1 1

1 1 1 0

1 1 1 1

Quine – McCluskey

Method


Step 2: Arrange the minterms in different groups, so that the first group has

no 1’s, second group contains only one 1, third group contains two 1’s and so on.

0 – 0 0 0 0 ; First Group

1 – 0 0 0 1 ; Second Group

4 – 0 1 0 0

5 – 0 1 0 1 ; Third Group

10 – 1 0 1 0

11 – 1 0 1 1 ; Fourth Group

14 – 1 1 1 0

15 – 1 1 1 1 ; Fifth Group


Step 3 :

a) Each minterm of one group is compared with each minterm in the group

immediately below.

b) Each time a number is found in one group which is the same as a

number in the group below except for one digit, the numbers pair is

ticked and a new composite is created.

c) This composite number has the same number of digits as the numbers

in the pair except the digit different which is replaced by an "x".


Column 1 - A B C D Column 2 - A B C D

0 0 0 0 0 √

1 0 0 0 1 √

4 0 1 0 0 √

5 0 1 0 1 √

10 1 0 1 0 √

11 1 0 1 1 √

14 1 1 1 0 √

15 1 1 1 1 √

(0,1) 0 0 0 x

(0,4) 0 x 0 0

(1,5) 0 x 0 1

(4,5) 0 1 0 x

(10,11) 1 0 1 x

(10,14) 1 x 1 0

(11,15) 1 x 1 1

(14,15) 1 1 1 x


Step 4 : Repeat Step 3 on Column 2.

Column 1 - A B C D Column 2 - A B C D Column 3 - A B C D

0 0 0 0 0 √

1 0 0 0 1 √

4 0 1 0 0 √

5 0 1 0 1 √

10 1 0 1 0 √

11 1 0 1 1 √

14 1 1 1 0 √

15 1 1 1 1 √

(0,1) 0 0 0 x √

(0,4) 0 x 0 0 √

(1,5) 0 x 0 1 √

(4,5) 0 1 0 x √

(10,11) 1 0 1 x √

(10,14) 1 x 1 0 √

(11,15) 1 x 1 1 √

(14,15) 1 1 1 x √

(0,1,4,5) 0 x 0 x

(0,4,1,5) 0 x 0 x

(10,11,14,15) 1 x 1 x

(10,14,11,15) 1 x 1 x


Unit : IV – Overview

Sequential Logic

Flip-Flops

Shift Register

Counters


70

The outputs of a sequential logic circuit depend on both the current inputs and

on previous inputs and outputs of the circuit.

Sequential elements have storage elements that record the state of the circuit.

In other words, the state information combined with the inputs is generating the

outputs.

The state and inputs also combine to generate a new state of the circuit.

The same inputs in a sequential circuit may generate different outputs and

different new states, depending on the circuit’s current state.

Sequential Logic


71

A bi-stable device i.e. a circuit with only 2 stable states, namely the ‘0’ state and the ‘1’ state.

Ability to retain its state and store a bit of information.

It is one-bit memory cell.

A flip-flop has 2 outputs and they complement each other.

Types of Flip Flop – SR Flip Flop, JK Flip Flop, D Flip Flop, T Flip Flop.

Flip-Flops


https://www.youtube.com/watch?v=rF_wASnSZkk

72

A common form of register used in computers and in many other types of

logic circuits is a shift register.

It is simply a set of flip flops (usually D latches or RS flip-flops) connected

together so that the output of one becomes the input of the next, and so on in

series.

It is called a shift register because the data is shifted through the register

by one bit position on each clock pulse.

Shift Register


https://www.youtube.com/watch?v=Iecj9xmIfXM

73

Serial-in Serial-out Register

On the leading edge of the first clock pulse, the signal on the D input is

latched in the first flip flop.

On the leading edge of the next clock pulse, the contents of the first flip-flop

is stored in the second flip-flop, and the signal which is present at the D input

is stored is the first flip-flop, etc.

Because the data is entered one bit at a time, this called a serial-in shift

register. Since there is only one output, and data leaves the shift register one

bit at a time, then it is also a serial out shift register.


74

Parallel-in Parallel-out Register

Parallel input can be provided through the use of the preset and clear

inputs to the flip-flop.

The parallel loading of the flip-flop can be synchronous (i.e., occurs with

the clock pulse) or asynchronous (independent of the clock pulse)

depending on the design of the shift register.

Parallel output can be obtained from the outputs of each flip-flop as

shown in Figure.


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Counters

Counter is a register which counts the sequence in binary form.

The state of counter changes with application of clock pulse.

The counter is binary or non-binary.

The total number of states in counter is called as modulus.

If counter is modulus-n, then it has n different states.

State diagram of counter is a pictorial representation of counter states directed by arrows in graph.

000

100

111

110

101

001

010

011

State diagram of mod-8 counter


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Asynchronous (Ripple) Counters

All Flip-Flops are in toggle mode.

The clock input is applied.

Count enable = 1.

Counter counts from 0000 to 1111.


77

In synchronous counters, the clock inputs of all the flip-flops are connected

together and are triggered by the input pulses. Thus, all the flip-flops

change state simultaneously (in parallel).

After the 3rd clock pulse, both outputs of FF0 and FF1 are HIGH. The

positive edge of the 4th clock pulse will cause FF2 to change its state due

to the AND gate.

Synchronous Counter

The J and K inputs of FF0 are connected to HIGH. FF1 has its J

and K inputs connected to the output of FF0, and the J and K inputs of

FF2 are connected to the output of an AND gate that is fed by the

outputs of FF0 and FF1.


78

Up / Down Counter

Bidirectional counters, also known as Up/Down counters, are

capable of counting in either direction through any given count

sequence and they can be reversed at any point within their count

sequence by using an additional control input


https://www.youtube.com/watch?v=PnwYW3RWARw

Unit : IV – Overview

Adders,Subtractors

Decoders,Encoders

Multiplexer,Demultiplexer

ROM

PLA


From our truth table, we can derive the following statement: “Our adding circuit should consist of an XOR gate (for R output, the Sum line) and an

AND gate (for Q output, the Carry line).

INPUTS OUTPUTS

A B Q R

A•B A B

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

• The XOR circuit delivers the

Sum Line (R) of adding two

single digits.

• The AND circuit produces the

Carry Line (Q).

• We’ve just created a fundamental circuit called a

Half Adder, which provides the

capability of adding two single

bit numbers.

HALF ADDER


Circuit Diagram for the Half Adder

A

B

R SUM

Q CARRY


• The Half Adder operates as the key component in a divide-and-conquer

approach to adding n digits.

• Three single digit numbers could be added two at a time:

1. Add the first two digits together using a half-adder.

2. Add the result of this sum to the third number

using another half-adder.

• To achieve this,

1. We need 3 input lines, one for each number.

2. Two input lines feed into the first half adder;

the third input line functions as a carry-in line.

3. The second half-adder has two input lines:

the output sum from the first half-adder, plus the third, carry-in input

line.

FULL ADDER


INPUTS OUTPUTS

A B CIN QCARRY RSUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Truth Table for the Full

Adder


Subtractor

• What we have is a circuit that can add numbers. We want to make

this circuit also work for subtracting two numbers…

• Let’s rethink our problem, with a specific example: 5 - 2 = 3, or, put

another way:

5 + (-2) = 3

• Now, we have an addition problem, instead of subtraction. This

means our existing circuit will work if we could unlock how to

represent negative numbers, like -2.

• This could be achieved using 2’s Complement.


Half Subtractor


Full Subtractor

• To subtract the higher order columns you also

need to subtract the borrow.

• The circuit can be constructed out of 2 half

subtractors


• A decoder is a combinational circuit that converts binary information from

n inputs to exactly one output of a maximum of 2^n outputs.

• The maximum number of outputs is directly related to the number of

inputs.

• A decoder with n inputs supports 2^n outputs.

• When n = 2, there are 2^2 = 4 outputs that can be decoded.

• When n = 3, there are 2^3 = 8 outputs that can be decoded.

DECODERS


Example: Design a 3 x 8 decoder using a truth table.

Y0 = A’B’C’ Y1 = A’B’C Y2 = A’BC’ Y3 = A’BC

Y4 = AB’C’ Y5 = AB’C Y6 = ABC’ Y7 = ABC


• A demultiplexer, sometimes abbreviated demux, is a circuit that has one

input and more than one output.

• It is used when a circuit wishes to send a signal to one of many devices.

• This description sounds similar to the description given for a decoder, but a

decoder is used to select among many devices while a demultiplexer is used

to send a signal among many devices.

DEMULTIPLEXER


The truth table for a 1-to-2 demultiplexer is

I A D0 D1

0

0

1

1

0

1

0

1

0

0

1

0

0

0

0

1

Using our 1-to-2 decoder as

part of the circuit, we can

express this circuit easily


• Multiplexers can be used in the design of both complex circuits and

also realization of primitive gates such as XOR and AND gates.

– XOR gate: If we look at an XOR gate’s functionality a little differently, we can easily see that when one input is 0 the other is

simply propagated through and when one is 1 the other is

complemented. Using a multiplexer to realize this, is shown in the

following figure. This realization uses only 6 transistors if we use

the second method used for a 2-to-1 MUX whereas XOR gates

usually consist of 8 transistors.

a b y

0

1

1

0

0

00

1

1 1

1

0

a

b

b-

y

0

1

Design of Circuit using MUX


• A read-only memory (abbreviated ROM) consists of an array of

semiconductor devices that are interconnected to store an array of binary

data.

• Once binary data is stored in the ROM, it can be accessed or read out

whenever desired, but it cannot be changed under normal operating

conditions.

• Shown next is an example of a truth table for an 8X4 ROM. The 8

indicates that there are 8 words of data stored in

the ROM.

The 4 indicates that each word of data stored in the

ROM consists of 4 bits.

Each word of data has a size of 4 bits.

Read Only Memory (ROM)


• Each combination of the input lines A, B, and C is used to access or

output one stored word value of 4 bits using the output lines F0, F1, F2,

and F3.

• Each input combination serves as an address that is used to access one

of the words of data stored in the ROM.


• The PAL (programmable array logic) is a special case of the

programmable logic array in which the AND array is programmable and the

OR array is fixed.

• The basic structure of the PAL is the same as the PLA.

• Because only the AND array is programmable, the PAL is less expensive

than the more general PLA.

• In general, the PAL is easier to program.

Programmable Array Logic (PAL)


Shown below is a segment of an unprogrammed PAL:


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