1

 FLOATING GATE MOS AS

NVRWM(non volatile read and write memory)

A Seminar Report Submitted in partial Fulfilment of the Requirements for Award of

Bachelor of TechnologyIn

Electronics & Telecommunication Engineering  

BYBISWABANDITA NAIK

Department of Electronics and Telecommunication Engineering

INSTITUTE OF TECHNICAL EDUCATION AND RESEARCH

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EDUCATION INSTITUTE OF TECHNICAL & RESAERCH

BHUBANESWAR

CERTIFICATEBISWABANDITA NAIK Reg.No. _0811016019__respectively ,has completed his/her seminar, in the academic year 2011-2012 for the partial fulfillment of Bachelor of technology under Siksha ‘O’ This is to certify that the Seminar entitled FLOATING GATE MOS AS NONVALATILE READ AND WRITE MEMORY Siksha “O” Anusandhan University , under the department of Electronics and Communication engineering, of Institute of Technical Education & Research, Bhubaneswar.

Date:3/04/2012

H.O.D.:Prof. NIVA DAS

Seminar In charge:prof L.P Mishra

Prof. susmita panda

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ACKNOWLEDGEMENT

I am indebted to many people for their guidance, suggestions, and encouragement without which I would not have been able to complete this technical paper presentation.

I would like to acknowledge all our teachers, whose insightful comments and recommendations on my presentation was the driving force for the success of this presentation.

And last but not the least; I would like to thank my parents and friends for their constant support and guidance and for standing by me through thick and thin.

BISWABANDITA NAIK

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CONTENTS

Page No.

Acknowledgement...........................................................................................................................

List of figures...................................................................................................................................

Abstract..........................................................................................................................................

Chapter 1:

1.1Introduction-----------------------------------------------------------------------------

1.2What is fgmos? --------------------------------------------------------------------------------------------

1.3History…………………………………………………………………………………………………

1.4Structure---------------------------------------------------------------------------------------------------------------

1.5TTDB------------------------------------------------------------------------------------------------------------------

Chapter 2:

2.1Basic Operation of NVM……………………………………………………………………

Chapter 3:

3.1Basic programming mechanism……………………………………………………………..

3.1.1.Fowler-Nordheim Tunneling……………………………………………….

3.1.2-Polyoxide Conduction……………………………………………………..

3.1.3Hot Electron Injection………………………………………………………

3.1.4Source Side Injection………………………………………………………

3.1.5Direct Band to Band Tunelling and modified Fowler nordheim tunneling..

Chapter 4:

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4.1Multiple input floating gate mos transistor……………………………………………….

Chapter5: Basic NVSM memory products

5.1 EPROM ………………………………………………………………….………………

5.2EEPROM………………………………………………………………………………….

5.3FLASH EEPROM…………………………………………………………………………

Chapter6:Application…………………………………………………………

Chapter 7: Conclusion and future scope.................................................................

References..................................................................................................................

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LIST OF FIGURES

i. FIGURE 1.1structure of FGMOS..............................................................................................

ii. FIGURE 1.2:TTDB…………...................................................................................................

iii. FIGURE 1.3Basic operating principle of nonvolatile

semiconductor memory:the storage of charges in the gate

insulator of MOSFET……………………………………………………

iv. FIGURE 1.4: Influence of charge in the gate dielectric on the

threshold of a p-channel transistor……………………..

v. FIGURE 1.5: Two classes of nonvolatile

semiconductor memory devices: (a)floating gate devices; (b) charge-trapping devices (MNOS device)………………………………………………………………………………………….

vi. FIGURE 1.6:Energy band structures of (a) the Si-SiC>2

system………………………….

vii. :FIGURE1.7 :Energy band representationof Fowler-Nordheim

tunneling through thin oxides: the injection field equals the

average thin oxide field. Electrons in the silicon conduction

band tunnel through the triangular energy

barrier2………………………………………………

viii. FIGURE 1.8: Energy band representation of Fowler-Nordheim

tunneling through oxides thermally grown on polysilicon: the

injection field is much higher than the average oxide field. The

high injection field is due to local field enhance-ment at

polysilicon-oxide interface asperities………………………

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ix. FIGURE 1.9 Energy band representation of hot-electron injection

in the oxide; the oxide field is low, but the electrons are

heated by the high lateral fields at the drain in the channel.

Some of them acquire enough energy to overcome the

interface energy

barrier…………………………………………………………………………

…………….

x. FIGURE 1.10Schematic representation of the problem of low-

injection effi-ciency for channel hot-electron injection and the

principle of source-side injection……………………..

xi. FIGURE 1.11Energy band representation of (a) direct band-to-

band tunnel-ing and (b) modified Fowler-Nordheim tunneling

between the silicon and the nitride conduction band…..

xii. FIGURE 1.12 lay out and Id Vs Vg………………………………………………………

xiii. FIGURE 1.13:Two-transistor EEPROM memory cell. In order to

allow byte selective write and erase, a select transis-tor is

added to the memory cell…………………………………………..

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ABSTRACT

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Chapter:1

1.1..INTRODUCTION

Floating-gate devices can be used for long-term nonvolatileinformation storage devices for analog applications. Because afloating gate is a polysilicon gate surrounded by silicon dioxide,charge on the floating gate is stored permanently, providinga long-term memory. Because a large number of electronscan be stored on an integrated circuit capacitor, we can storea nearly continuous analog voltage. Furthermore, the chargeon this floating gate can be modified by projecting ultraviolet(UV) light on the chip, by applying large voltages across asilicon-oxide capacitor to tunnel electrons though the oxide, orby adding electrons using hot-electron injection .Floating gate MOS transistors currently have widespread applications as the storage elements in EPROM and EEPROM circuits. These devices are optimized for small area, high write/erase speed and low failure rate when used for digital memory . Due to their long-term charge retention, the floating gate devices would have potential applications in analog circuits but they are not trivial to implement and need much fundamental work.The research is directed toward the use of floating gate devices as compact and non-volatile elements for analog trimming. Among the desired features of such a device are bidirectional fine trimming, low programming voltages, good charge stability, and large trim range. It is also desirable to avoid the need for special processing to achieve ultrathin oxide film or textured-surface polysilicon since these processing features are expensive and often not available.

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1.2.WHAT IS FLOATING GATE??

The floating-gate MOSFET (FGMOS) is a field-effect transistor, whose structure is similar to a conventional MOSFET. The gate of the FGMOS is electrically isolated, creating a floating node in DC, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG. Since the FG is completely surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time.

Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used in order to modify the amount of charge stored in the FG.

Some applications of the FGMOS are digital storage element in EPROM, EEPROM and flash memories, neuronal computational element in neural networks, analog storage element, e-pots and single-transistor DACs.

1.3.History

The first report of a floating-gate MOSFET was made by Kahng and Sze. and dates back to 1967. The first application of the FGMOS was to store digital data in EEPROM, EPROM and flash memories. However, the current interest in FGMOS circuits started from developing large-scale computations in neuromorphic systems, which are inherently analog.In 1989 Intel employed the FGMOS as an analog nonvolatile memory element in its ETANN chip, demonstrating the potential of using FGMOS devices for applications other than digital memory.

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1.4.Structure

Fig-1.1

An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node.

For applications where the charge of the FG needs to be modified, a pair of small extra transistors are added to each FGMOS transistor in order to conduct the injection and tunneling operations. The gates of every transistor are connected together; the tunneling transistor has its source, drain and bulk terminals interconnected in order to create a capacitive tunneling structure. The injection transistor is connected normally and specific

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voltages are applied in order to create hot carriers that are then injected via an electric field into the floating gate.

FGMOS transistor for purely capacitive use can be fabricated on N or P versions. For charge modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated.

1.4.TTDB(TIME DEPENDENT DIELECTRIC BREAKDOWN)

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Fig-1.2

Thin layers of silicon dioxide used as a dielectric for capacitors or as the gate oxide for a MOS semiconductor device are subject to a wearout mechanism known as time dependent dielectric breakdown (TDDB). This mechanism causes the dielectric to break down and become electrically shorted after some duration of operation. The expected lifetime of a thin oxide under normal operating conditions should be several million years. However, defects in the oxide can shorten this lifetime by many orders of

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++

++

++

--

--

--

--

P-Si

EC

EV

EC

EV

POLY

ORIGINAL BAND DIAGRAMM

E

DISTORTED

TIME DEPENDENT DIELECTRIC BREAKDOW

N IN MOS

SiO2

magnitude. Therefore, the random defect density is the primary parameter determining the reliability of the oxide.Therefore, the random defect density is the primary parameter determining the reliability of the oxide. The interface trap density at a range of energies and the bulk electron trap density are two material properties of the oxide that affect the reliability of the oxide.

The mechanism that causes time dependent dielectric breakdown begins with an electron tunneling through the oxide, a phenomenon known as Fowler-Nordheim tunneling. Electrons in the conduction band of the conductor above or below the oxide can randomly acquire enough energy to jump the energy barrier separating the electron from the oxide. This is a rare occurrence at low electric fields, but, as the electric field increases, the frequency of this injection increases rapidly. Once an electron has sufficient energy to overcome the energy barrier keeping a conductor’s electron from the oxide, it acts as a charged ballistic particle in an electric field. As long as the electron travels in a free path (i.e., no collisions), the electron is accelerated by the electric field and its kinetic energy increases. The longer the free path is, the greater the energy of the electron will be. In addition, the greater the electric field for any free path is, the greater the energy of the electron will be.

Chapter:2 2.1. BASIC OPERATION OF NVM

The basic operating principle of nonvolatile semiconductor memory devices is the storage of charges in the gate insulator of a MOSFET, as illustrated in Fig. 1.3. If one can store charges in the insulator of a MOSFET, the threshold voltage of the transistor can be modified to switch between two distinct values, conventionally

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Figure 1.3 Basic operating principle of nonvolatile semiconductor memory:the storage of charges in the gate insulator of MOSFET.

denned as the 0 or erased state and the 1 or written (programmed) state, as illustrated in Fig. 1.4.From the basic theory of the MOS transistor, the threshold voltage is given by

Thus , the threshold voltage shift, caused by the storage of the charge QT is given by

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The information content of the device is detected by applying a gate voltage Vrea d with a value between the two possible threshold voltages. In one state, the transistor is conducting current , while, in the other, the transistor is cut off. Whenthe power supply is interrupted, the charge should, of course, remain stored in the gate insulator in order to provide a nonvolatile device.The storage of charges in the gate insulator of a MOSFET can be realized in two ways, which has led to the subdivision of nonvolatile semiconductor memorydevices into two main classes.

Figure 1.4 Influence of charge in the gate dielectric on the threshold of a p-channel transistor.

The first class of devices is based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, usually thermaloxide, as shown on Fig. 1.5a. Since this layer acts as a completely electrically isolated gate, this type of device is commonly referred to as a floating gate device .

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In the second class of devices, the charge is stored in discrete trapping centers of an appropriate dielectric layer. These devices are, therefore, usually referred to as charge-trapping devices. The most successful device in this category is the MNOSdevice (metal-nitride-oxide-semiconductor) structure , in which the insula-tor consists of a silicon nitride layer on top of a very thin silicon oxide layer, as shown in Fig. 1.5b. Other possibilities, such as A12O3 (MAOS) and Ta2O5 (MTOS), have never been successfully exploited.

Figure 1.5 Two classes of nonvolatilesemiconductor memory devices: (a)floating gate devices; (b) charge-trapping devices (MNOS device).

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chapter:33.1.BASIC PROGRAMMINGMECHANISM………

In silicon oxide, the current is determined mainly by theelectrode characteristics, more specifically by the characteristics of the injection interface. This is due to the fact that SiO2 has a large energy gap (about 9Ev compared to 5 eV for Si3N4) and a high energy barrier at its interface with aluminum or silicon. For example, the barrier of SiO2 is about 3.2 eV for electrons in theconduction band of silicon and 4.8 eV for holes in the valence band, compared to 2eV for holes and electrons in Si3N4, as shown in Fig. 1.9, which gives a comparison of the band structure for both materials. This means that conduction through SiO2 will be determined primarily by electron injection, while, in Si3N4, both holes and electrons can contribute to the injection currents .In both classes of nonvolatile memory devices, charge-trapping and floating gate devices, the charge needed to program the device has to be injected into an oxide layer, either to store it in the isolated traps in the nitride for the case of MNOSdevices or to collect it at the floating gate in floating gate devices.During the last two decades, various mechanisms for charge injection into the oxide have been considered. In order to change the charge content of floating gate devices, four mechanisms have been shown to be viable: i-Fowler-Nordheim tunnel-ing (F-N) through thin oxides (< 12 nm)ii-enhanced Fowler-Nordheim tunnel-ing (F-N)

iii-channel hot-electron injection (CHE)

iv-source-side injection (SSI) .

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Figure 1.6 Energy band structures of (a) the Si-SiC>2 system

The first two are based on a quantum mechanical tunneling mechanism through an oxide layer, whereas the last two are based on injection of carriers that are heated in a large electric field in the silicon, followed by injection over the energy barrier of SiO2. In order to change the charge content in charge-trapping devices, direct band-to-band tunneling and mod-ified Fowler-Nordheim tunneling mechanisms are used. In the following sections,these mechanisms are discussed briefly.

3.1.1.Fowler-Nordheim Tunneling

One of the most important injection mechanisms used in floating gate devices is the so-called Fowler-Nordheim tunneling, which, in fact, is a field-assisted electron tunneling mechanism . When a large voltage is applied across a polysilicon-SiO2-silicon structure, its band structure will be

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influenced as indicated in Fig. 1.10.Due to the high electrical field, electrons in the silicon conduction band see a trian-gular energy barrier with a width dependent on the applied field. The height of the barrier is determined by the electrode material and the band structure of SiO2. At sufficiently high fields, the width of the barrier becomes small enough that electrons can tunnel through the barrier from the silicon conduction band into the oxide conduction band. This mechanism had already been identified by Fowler and Nordheim for the case of electrons tunneling through a vacuum barrier,

Figure 1.7 Energy band representationof Fowler-Nordheim tunneling through thin oxides: the injection field equals the average thin oxide field. Electrons in the silicon conduction band tunnel through the triangular energy barrier.

3.1.2-POLYOXIDE CONDUCTION

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In oxides thermally grown on monocrystalline silicon, the injection field is equal to the average field in the SiO2; therefore, thin oxides have to be used to achieve large injection fields at moderate voltages. Oxides thermally grown on polysilicon, called polyoxides, however, show an interface covered with asperities due to the rough texture of the polysilicon surface . This has led to the name "texturedpolyoxide." These asperities give rise to a local field enhancement at the interface and an enhanced tunneling of electrons . In polyoxides, the field at the injecting interface is, therefore, much larger than the average oxide field Consequently, the band diagram of a polysilicon-polyoxide interface is as shown schematically in Fig. 1.8. Average oxide fields of the order of 2 MV/cm are sufficien to yield injection fields of the order of 10 MV/cm. This has the big advantage tha large injection fields at the interface can be obtained at moderate voltages usingrelatively thick oxides, which can be grown much more reliably than the thin oxides necessary for Fowler-Nordheim injection from monocrystalline silicon.

Figure 1.8 Energy band representation of Fowler-Nordheim tunneling through oxides thermally grown on polysilicon: the injection field is much higher than the average oxide field. The high injection field is due to local field enhance-ment at polysilicon-oxide interface asperities.

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3.1.3.HOT ELECTRON INJECTION

At large drain biases, the minority carriers that flow in the channel of a MOS transistor are heated by the large electric fields seen at the drain side of the channel and their energy distribution is shifted higher. This phenomenon gives rise to impact-ionization at the drain, by which both minority and majority carriers are generated.The highly energetic majority carriers are normally collected at the substrate contact and form the so-called substrate current. The minority carriers, on the other hand,are collected at the drain. A second consequence of carrier heating occurs when some of the minority carriers gain enough energy to allow them to surmount the SiO2 energy barrier. If the oxide field favors injection, these carriers are injected over the barrier into the gate insulator and give rise to the so-called hot-carrier injection gate current . This mechanism is schematically represented for the case of an n-channel transistor in the energy band diagram shown in Fig. 1.15.For nonvolatile memory applications, n-channel transistors are generally used,and therefore, the discussion here will be limited to n-channel devices. In case of an n-channel transistor, the gate current of the transistor consists of those channel hot electrons that actually reach the gate of the transistor. In a floating gate transistor,these electrons change the charge content of the floating gate. An important differ-ence between hot-carrier injection and the two previously discussed injection mechanisms is that, with hot-electron injection, it is only possible to bring electrons onto the floating gate. They cannot be removed from the floating gate by the same mechanism. Although the use of hot-hole injection as a compensating programming mechanism has been tried , it has never found application due to the very small current levels that can be attained in this way.

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Figure 1.9 Energy band representation of hot-electron injection in the oxide; the oxide field is low, but the electrons are heated by the high lateral fields at the drain in the channel. Some of them acquire enough energy to overcome the interface energy barrier.

3.1.4.SOURCE-SIDE-INJECTION

The main disadvantage of the conventional channel hot-electron injection mechanism for programming a nonvolatile element stems from its low injection efficiency, and consequently, its high power consumption. This is due to the incom-patibility of having a high lateral field and a high vertical field, favorable for electron injection, at fixed bias conditions, as explained in the previous section. Indeed, thelateral field in a conventional MOS device is a decreasing function of the gatevoltage, while the vertical field increases with the gate voltage. Therefore, in orderto generate a large number of hot electrons, a low gate voltage is required, combined with a high drain voltage. However, for electron injection and collection on the floating gate of the memory device, a high gate voltage and a low drain voltage are required (see Fig. 1.10). In practice, both gate and drain voltages are kept high as a compromise. The main drawback is clearly the high drain current (on the order of mA's) and the correspondingly high power consumption.

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Figure 1.10Schematic representation of the problem of low-injection effi-ciency for channel hot-electron injection and the principle of source-side injection.

3.1.5.DIRECT BAND-TO-BAND TUNELING AND MODIFIED FOWLER-NORDHEIM TUNNELING.

In MNOS devices with ultra-thin oxides (< 3 nm), the injection current can either be direct silicon band to nitride band tunneling only through the oxide barrier, as illustrated in Fig. 1.20a, or modified Fowler-Nordheim tunneling through the oxide barrier and a nitride barrier, as shown in Fig. 1.11ft. Whether one or the other of these conditions applies depends strongly on the values of the oxide field and oxide thickness.

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Figure 1.11 Energy band representation of (a) direct band-to-band tunnel-ing and (b) modified Fowler-Nordheim tunneling between the silicon and the nitride conduction band.

Chapter:4

4.1 Multiple-Input Floating Gate MOS Transistors

hot-electron injection, this method can only introduce electrons ONTO the floating gate. There is another program method which is based on tunneling effect, and can induce positive or negative charge on the floating gate. When the floating gate transistor is

bathed in UV light for some time, the charge on the floating gate will disappear.Because of the very good insulation properties of SiO2, the charge on the floating gate leaks away very slowly, and the VT will keep high for a long time

( for decades in room temperature ).For analog circuits, there are some applications of this programming property of floating gate MOS transistors, such as circuit trimming and neural networks.

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Practically it is hard to control the charge on the floating gate exactly

fig-1.12

• Multiple-Input Floating Gate ( MIFG ) MOS Transistors– A Multiple-Input Floating Gate ( MIFG ) MOS Transistor is a floating gate

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– The n input control gates are capacitively coupled to the floating gate. Let’s assume QFG is the net charge on the floating gate, VFG is the voltageof the floating gate, and Vgi is voltage of the ith control gate, thus transistor with mutiple control gate

Chapter:5

. BASIC NVSM MEMORY PRODUCTS

5.1 EPROM/OTP

The electrically programmable read-only memory (EPROM) was, in fact, the first nonvolatile memory that could be electrically programmed by the user and that could be erased afterward. All EPROM products rely on the floating gate cell concept. Present EPROM devices all use channel hot-electron injection. Since thismechanism can only supply electrons to the floating gate, EPROM memories are not electrically erasable. UV light is used to erase the memory. For programming and reading, the memory is byte addressable, and each byte can be addressed separately. Obviously, the erase operation always affects the whole memory. It is the user who can perform both operations. For both operations, however, some additional tools are needed—an EPROM programmer and UV light for erasing.

ADVANTAGES:-

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-HIGH PACKING DENSITY

-SIMPLE IN OPERATION

- LOW COST

DISADVANTAGES:-

Since UV light is used for erasure, a quartz window has to be provided in the EPROM package, which makes this package quite expensive. The package also haS to be taken out of the circuit board in order to erase or reprogram the memory. In order to avoid these problems, a new product, which actually uses the same chips a the EPROM, called the one-time programmable (OTP) memory, was developed This device can be written only once and is used like a PROM. Since no erasur of the memory is intended, the quartz window is not necessary and the device can be housed in a cheaper plastic package.

5.2 EEPROM

Although EPROM memories are reprogrammable, the reprogramming of the device is not user-friendly. The circuit has to be taken off the circuit board. The erase operation takes about 20 minutes, and then the whole memory circuit has to be reprogrammed byte by byte. This rather tedious erase procedure must be performed even if the content of a single byte has to be changed. These drawbacks have been obviated in the electrically erasable programmable read-only memory (EEPROM).In this type of nonvolatile memory circuit, all operations are controlled by electrical signals. The circuit can be reprogrammed while residing on the circuit board. Each operation, including erasing, can be performed in a byte-addressable way.

This higher level of functionality results in a larger memory cell. Since the EEPROM is byte addressable for reading and for all programming operations, the memory cell has to consist of a

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memory transistor and a select transistor as shown in Fig. 1.13, thus leading to the so-called two-transistor memory cell. As a result, this memory cell is larger than the EPROM cell. Consequently, the densities of EEPROM products have always lagged behind EPROM densities by one to two generations, as illustrated in Fig. 1.25, with 1 Mbit to 2 Mbit memories as the present state-of-the-art EEPROM densities. Typical cell sizes of 1 Mbit parts range between 30 and 50p,m2.

.

Figure 1.13 Two-transistor EEPROM memory cell. In order to allow byte selective write and erase, a select transis-tor is added to the memory cell.

ADVANTAGES:-

- LOW PROGRAMMING VOLTAGE

- SUPPORTS 100000 ERASE/WRITE CYCLES

-DISADVANTAGES:-

- HIGH FAB. COST

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- LOW PACKING DENSITY AS REQUIRES THIN OXIDE LAYER

-TOO MUCH ERASURE MAY RESULT IN A DEPLETED DEVICE

5.3 Flash EEPROM

During the 1980s, a novel nonvolatile memory product was introduced, referredto as the Flash EEPROM [1.58]. The general idea was to combine the fast program-ming capability and high density of EPROMs with the electrical erasability of EEPROMs. The first products were merely the result of adapting EPROMs in such a way that the cell could be erased electrically. Consequently, these devices used channel hot-electron injection for programming and Fowler-Nordheim tunnel-ing through a thin gate oxide or through a polyoxide for erasure.All Flash EEPROM products are based on the floating gate concept. The memory can be erased electrically but not selectively. The content of the whole memory chip is always cleared in one step. The advantages over the EPROM are the faster (electrical) erasure and the in-circuit reprogrammability, which leads to a cheaper package. Its cost is lower than that of EEPROM devices, and the part was introduced partially to cope with the low volumes of the market that could be reached with the full-featured EEPROM, until recently.In the 1990s, Flash memory has become the largest market in nonvolatile tech-nology due to a highly competitive tradeoff between functionality and cost/bit. Since the cell size of Flash devices has the potential to track that of DRAM cells, compet-itively priced Flash concepts are expected to find a huge market and even to becomeone of the main technology drivers of the semiconductor industry. Apart from the replacement of EPROMs and EEPROMs, novel application fields have also arisen,such as solid-state disks for portable and handheld computers, and smart cards.Also, novel device structures have been proposed based on Fowler-Nordheim tun-neling for both programming and erasure in order to allow operation from a singlesupply voltage. Moreover, source-side injection Flash

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devices havegained considerable interest because of their unique combination of very fast pro-gramming capabilities with low power consumption.Currently, Flash products up to 32 Mbit are commercially available. The cell size attained in a 32 Mbit product is on the order of Finally,there is a strong demand for embedded Flash memory on ASICs, digital signal processing (DSP) chips, microcontrollers, and so on. In the case of microcontrollers,process compatibility, development cost, and single-supply voltage operation are more stringent requirements than high density and high performance.In 1995, Flash's cost/MB had already become smaller than DRAM's, and additional improvements are still to be expected because of its high scalability.Furthermore, due to the demand for ever higher Flash memory densities (also in embedded applications such as smart cards), the multilevel charge storage (MLCS)option has recently gained considerable interest. The MLCS principle is based on therelatively high stability of the charge level that can be stored inside the floating gate memory cell in a virtually continuous (or analog) manner. In this way, more than two levels, and hence, more than 1 bit, can be stored inside a single memory tran-sistor. This further increases memory capacity without the need for considerable changes in die size or aggressive technology scaling, hence drastically decreasing the cost/MB even further.

ADVANTAGES:-

- BLOCK LEVEL ERASURE

-HIGHER PACKING DENSITY THAN FLOTOX AS IT HAS ONLY 1 TRANSISTOR.

Chapter:6

APPLICATION

The nonvolatile memory cell concept has been used in several kinds of applications,and many different products have emerged

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in recent years. The core of the applica-tions are high-volume stand-alone nonvolatile memories, but besides these, it has also been applied to other purposes such as electrically programmable logic devices(EPLD), application specific integrated circuits (ASIC) (embedded memories), and redundancy. Before discussing the different types of nonvolatile cells, this section first treats some of the important features of the main nonvolatile memory products.The aim is not to be complete, however, for the application fields and the productrange for nonvolatile memory cells are so large that they cannot be covered within the limited focus .

Chapter:7

Conclusion

The future looks promising for floating-gate circuits.for floating gate circuits to continue on its ever –expanding trend,a few achievable hurdles must be overcome.first ,the floating gate charge must be quickly modified during initial test procedures to move all the floating gate circuits to a useful operating range .most floating gate citcuits exihibit very robust behavior once they are in the neiborhod of their proper operating range .typical constraints for industrial IC testing require characterization times in the milLisecond range,a requirement not satisfied by most current floating gate circuits,these constraints will be more significant for chip utilizing hundreds or thousands of floating gate devices,as is expected with the adaptive floating gate application.a second issue is to increase the industrial applications of floating gate devices ,and to look for applications to imbed these circuits in ti various system applications.a final issue is to strengthen the community of reasrchers working in this field, to encourage new research in this field ,and to build a common language to facilitate collaboration in this area.

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References

[1.1]- G. Groeseneken,H.E.Maes,J.VanHoudt,

and J.S. Witters”Basics of Nonvolatile Semiconductor Memory Devices”

[1.2]- Floating Gate Techniques and Applications

[1.3]-Paul Hasler,Bradley A. minch,chris diorio”floating gate device:they are not just for digital memory any more”.

[1.4]- Overview of Floating-Gate Devices, Circuits,and Systems” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 1, JANUARY 2001”

[1.5]- 1.Rabaey: Digital integrated circuits- A

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[1.6]- .Neamen : Semiconductor physics and devices, TMH,3/e.

[1.7]- 3.Streetman: Solid state electronic

devices,PHI, 5/e.

[1.8]-US Patent :FAMOS, Patent no.6965142B2, Diorio etal .

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