Wing-kei Yu, Shantanu Rajwade, Sung-En Wang, Bob Lian, G. Edward Suh, Edwin Kan

Cornell University

A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors

Self-Powered Devices • Autonomous wireless sensor networks

• RFIDs and RFID readers

•  In-body sensors and health monitoring

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Computation with Unstable Power •  Autonomous systems harvest power from environment

•  Many power sources unstable / unreliable •  Solar •  Wind •  RF signal

•  Limited computation •  Intel WISP active only

27% of the time

•  Ex: RF energy trace •  RF relatively reliable •  Yet voltage fluctuates

wildly

Source: Kevin Fu, U Mass. Amherst

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Non-Volatile Computing • Build non-volatile processors that remember state across

power interruptions

• Benefits •  Computation across power interruptions •  Idle time power gating without sacrificing response time

• Replace or augment volatile structures in processor with non-volatile structures

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Non-Volatile Processor • Processor has non-volatile storage • Reserve capacitor • Power cut-off at any time

• On power failure, store to non-volatile storage (NV store)

• On power restoration, load and resume computation (NV restore)

Processor

Capacitor

NV memory Volatile state

Power

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Outline • Non-volatile processor architecture

• Hybrid volatile/non-volatile memory cell

• Prototype microcontroller

• Results

• Conclusion

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Non-volatile Processor Requirements •  Fast and low-energy NV store and restore

•  Perform NV store with limited energy after power failure

•  Low impact on normal processor operation

•  Long lifetime •  Minimize program/erase cycles to NV memory

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Processor Design Options • Discrete

+ No impact on normal operation + Infrequent NV operations allow

long lifetime −  Expensive NV store and erase

• Fully non-volatile

+ No NV operation after power failure − High penalty on normal operation −  Short NV memory lifetime

Processing unit

Volatile memory

Volatile registers

NV memory

Processingunit

Non-Volatile memory

NV regs

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Our Approach: Hybrid Architecture • Hybrid volatile/non-volatile

•  Per-cell integration of volatile and non-volatile components

•  Enables non-volatile computing •  Low normal operation penalty •  Infrequent NV store and erase

gives long lifetime •  Low energy NV store and erase

•  Overheads •  Area of hybrid cell •  Energy and delay cost in normal

operation

Hybrid memory

Processingunit

Hybridregisters

cell

volatile

NV

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Outline • Non-volatile processor architecture

• Hybrid volatile/non-volatile memory cell

• Prototype microcontroller

• Results

• Conclusion

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Nanocrystal Flash Memory • Why Flash?

•  No current during program

• Nanocrystal Flash •  Long endurance (1012 cycles) •  Relatively low voltage (6 V)

•  Fabrication •  Devices made in lab •  Freescale has a similar type

in production

Gate

N-Si

SiO2 (2 nm)

Metal NC (4-10 nm)

SiO2 (7 nm)

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Hybrid Volatile/Non-volatile Memory • Combines two memory types at cell-level •  SRAM and Flash •  On power failure, data in

SRAM is moved to Flash (NV store)

•  On power restoration, data moved from Flash to SRAM (NV restore)

•  Also applied to D Flip-flop

• Data movement for array happens in parallel

SRAM

Flash

Memory Array

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Hybrid Volatile/Non-volatile Memory

• Start with an SRAM •  Augmented with 2 NV Flash transistors •  Connected to VDD via enable transistors

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Normal Read and Write Operation

• Enable and Program/Erase (PE) off • Acts identically to SRAM

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Non-Volatile Store Operation

• NV store records data from SRAM to Flash • Enables OFF • PE signal ON, high voltage (6V)

6V 6V

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Non-Volatile Restore Operation

• Enables ON •  The Flash with higher Vth will conduct less current •  Imbalance in current restores SRAM state

1V 1V

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Erase

• Negative high voltage applied to PE node • Enables OFF

-6V -6V

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NV D Flip-flop • Similar to NV-SRAM in operation

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Outline • Non-volatile processor architecture

• Hybrid volatile/non-volatile memory cell

• Prototype microcontroller

• Results

• Conclusion

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Prototype Microcontroller

•  8-bit low power microcontroller •  Modified Picoblaze clone •  Similar to microcontrollers in self-powered devices •  Small enough to perform detailed circuit-level simulation

Processing units (ALU)

GPR(16x8-bit)Inst reg

PC

Cond.

Program Flash (2KB)

Scratch pad (64B)

Stack(32x10-bit)

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Non-Volatile Architecture

• Architectural state augmented with hybrid memory •  NV-DFFs used

• Additional circuits •  Power monitor •  Non-volatile controller •  Charge pumps

Processing units (ALU)

Program Flash (2KB)

GPR(16x8-bit)

Scratch pad (64B)

Inst reg

PC

Cond.

Stack(32x10-bit)

Charge pumps

Power monitor

NV control

Capacitor

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Power Failure Energy Consumption P

ower

Time

Normal operation

store

Power-down Off Off

erase store

Pre-charge pump

Maintain charge

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Charge pump Charge pump

Evaluation • Study performance, area and energy overheads

•  Compare volatile vs. hybrid non-volatile architecture

• Hybrid memory study •  Layout and HSPICE simulation based on experimental data •  Area, delay, energy estimates

• System-level study •  Synopsys + Cadence std. cell flow with HSIM/Verilog co-simulation •  Normal instruction operation overheads •  NV save, restore and erase

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NV Memory Area

63% larger

Hybrid NV-SRAM SRAM

Nor

mal

ized

Are

a

40% larger

Hybrid NV-DFF DFF

Nor

mal

ized

Are

a

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0.00

1.00

2.00

3.00

4.00

5.00

6.00

7.00

8.00

0 to 1 1 to 0

DFF Hybrid NV-DFF

0.00

1.00

2.00

3.00

4.00

5.00

6.00

7.00

8.00

Read Write

SRAM Hybrid NV-SRAM

NV Memory Energy

19% more

SRAM Read/Write Energy

25% more

18% more

15% more

DFF Transition Energy fJ fJ

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0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00

100.00

0 to 1 1 to 0

DFF Hybrid NV-DFF

0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00

100.00

Read Write

SRAM Hybrid NV-SRAM

Cell Delay

28% more 38%

more

DFF Transition Delay

18% more

16% more

SRAM Read / Write Delay ps ps

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Prototype Microcontroller Area •  80,587 µm2 on a 65nm

process (w/o program Flash or charge pump, NV controller)

20% larger

Prototype

Baseline N

orm

aliz

ed A

rea

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Prototype Energy and Performance •  Each instruction in microcontroller ISA simulated 20x

•  Average 1.5% energy increase •  No impact on clock frequency due to slow operating speed

0.9 0.92 0.94 0.96 0.98

1 1.02 1.04

add

addc

y su

b su

bcy

com

pare

an

d or

xor

test

sh

iftR

0 sh

iftR

1 sh

iftR

x sh

iftR

a ro

tate

R

shift

L0

shift

L1

shift

Lx

shift

La

rota

teL

load

/sto

re

call

retu

rn

baseline hybrid NV

Nor

mal

ized

Ene

rgy

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NV Operation Energy and Performance • Dominated by charge pump energy •  Total 1Kbits storage

Operation Delay Energy NV store 10 µs 172 pJ

NV restore ~ 5 ns - NV erase ~ 10 µs, background ~ 172 pJ

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Handling Power Interruptions • Hybrid NV architecture

•  Store/Erase each need 1.390 pJ / byte

• Reserve capacitor needed •  NV store + NV erase •  280 pF

•  For larger processors, benefit increases

•  More state to save

• Discrete off-chip NV architecture •  Store needs 0.125 µJ / byte •  Restore needs 0.216 µJ / byte

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Related Work •  Hybrid volatile/non-volatile memory

•  Many NV-SRAM designs exist •  Use resistive memory technology

•  Self-checkpointing microprocessors •  Off-chip NV memory •  Periodic snapshots

•  Perpetual embedded devices •  Platforms targeting ultra-low power operation •  Still volatile

•  Non-volatile memory in system architecture •  PCM in DRAM, Flash as hard disk •  Focus on performance and energy efficiency

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Summary • Non-volatile computing

•  Allows computing in power-limited, embedded devices •  Compute across power outages

• Hybrid volatile/non-volatile memory •  Closely integrates nanocrystal flash •  Fast, low-energy save / restore

• Non-volatile microprocessor •  Fast save and restore on power down / up •  Less than 2% normal energy overhead •  20% area overhead

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