1

Field-Effect Transistors The field-effect transistor (JFET) is the simplest type of field effect

transistors.

• Structure

• Current-voltage Characteristics

• MOSFET as an Amplifier

• CMOS

• The CMOS Digital Logic Inverter

2

n-channel Enhancement mode MOSFET Two n-regions called source terminal and drain terminal. The current in

a MOSFET is the result of flow of charge in the inversion layer called the

channel region.

Source Drain Channel

For

The channel width is uniform

4

iD-vDS Characteristics Cutoff; Triode (switch); and Saturation (amplifier) regions

Channel) (Induced tGS Vv 

2mA/V 5.0'

V 1

 

  





L

W k

V

n

t

5

To operate the MOSFET in the triode region

 

 

  1

2

'

'

2

1 '



 

  

 



 

  

 



tGSn D

DS DS

DStGSnD

DSDStGSnD

tGSDS

Vv L

W k

i

v r

vVv L

W ki

vvVv L

W ki

Vvv

6

To operate the MOSFET in the saturation region

DSnD

DSnD

tGSDS

tGSDS

tGD

tGS

v L

W ki

v L

W ki

Vvv

Vvv

Vv

Vv

2

2

' 2

1

' 2

1













mA/V2) 0.5nW/Lk’ V, 1 (

Saturationin r transistoNMOS type-tenhancemenan for

sticsCharacteri -

t

GSD

V

vi

7

iD-vGS characteristics for an enhancement-type NMOS

transistor in Saturation (Vt= 1 V, k’nW/L=0.5 mA/V 2)

8

Increasing vDS beyond vDsat causes the channel pinch-off to

move away from the drain.

9

Effect of vDS on iD in the saturation region

10

Large-signal equivalent circuit model of the n-channel

MOSFET in saturation.

11

Exercise 5.3 • An Enhancement-type NMOS transistor with Vt = 2 V has its source

terminal grounded and a 3-V DC source connected to the gate. In what

region of operation does the device operate for:

• VD = +0.5 V (vDS  vGS-Vt: Triode)

• VD = 1 V (vDS  vGS-Vt: Saturation)

• VD = 5 V (vDS  vGS-Vt: Saturation)

12

The Current-Voltage Characteristics of the Depletion n-Channel MOSFET

for Which Vt = -4V and k’nW/L = 2 mA/V 2

13

The MOSFET as an Amplifier

DC Bias

 

tGSD

DDDDD

tGSnD

VVV

IRVV

VV L

W kI







Saturation Ensure To

' 2

1 2

14

The Signal Current in the Drain Terminal

 

 

 tGSn gs

d m

gstGSnd

dDD

tgsGSnD

gsGSGS

VV L

W k

v

i g

vVV L

W ki

iIi

VvV L

W ki

vVv











'

'

' 2

1 2

15

16

Small Signal Equivalent Circuit

17

The T Model

18

19

Basic Configurations of Single-Stage IC MOS

Amplifiers

• Common Source (CS)

• Common Gate (CG)

• Common Drain (CD)

20

Amplifier Source-Common CMOS

 21

2

2

// oom i

o v

REF

A

o

rrg v

v A

I

V r





21

Amplifier Gate-Common CMOS The

 

  

   





 



 

 



 





 



 

1

2

11

2111

2 1

11

1 1

//

// 1

o

o

mbmi

i

oombmv

oo o

mbm i

o v

r

r

ggi

v Ri

rrggA

rr r

gg v

v A

22

AmplifierFollower -Sourceor Drain -Common The

    2111

11

1

21 11

1

1

1

/////1///1

11

1

oombmo

mbm

m

oo mbm

m v

Sm

Sm

i

o v

rrggR

gg

g

rr gg

g A

Rg

Rg

v

v A



 





 

23

Loadt Enhancemenwith Amplifier NMOS

24

LoadDepletion with Amplifier NMOS The

25

CMOS Inverter

26

High is hen Inverter W CMOS theofOperation Iv

  

  

 



  

  tnDD

n

nDS VV L

W kr '/1

27

Low is hen Inverter W CMOS theofOperation Iv

   





 



 



  

  tpDD

p

pDSP VV L

W kr '/1

28

The Voltage Transfer Characteristics of the CMOS Inverter

and Noise Figures

 

 

OLILML

IHOHMH

tDDIL

tDDIH

VVN

VVN

VVV

VVV









23 8

1

25 8

1

 

 

 nn

pp

thtpDD

th

LWk

LWk r

r

VVVr V

/'

/'

1





 

29

Operation Dynamic

   

   

 Delayn Propagatio 2

High toLow /'

6.1

Low High to /'

6.1

PLHPHL p

DDpn PLH

DDnn PHL

tt t

VLWk

C t

VLWk

C t

 



