DATAFLOW Studio Clear, Safe, Efficient Dataflow Studio consists of tailor-made components that de-fine and support your development processes as a complete system or individual application. Thanks to its simplicity, clarity and conformity to standards, Dataflow Studio is perfect for the design of complex systems, too.

DATAFLOW Studio Consistent System ArchitectureWith the Dataflow tools, you model graphically supported sys-tems and software. Thus, you define a consistent, clear and comprehensible system architecture. At the same time, Data-flow Runtime provides you with a smart, event-based real-time operating system.

DATAFLOW Studio Concentrated Know-How for youDataflow is a result of our decades of experience in demanding projects in consistently regulated medical, industrial and infor-mation technology and the increasing demands on embedded devices. Since 2014, we successfully use Dataflow Studio and Runtime for our customers‘ efficient and secure development of sophisticated embedded systems.

Now Dataflow Studio is also available for the design of your em-bedded systems.

DATAFLOW Studio and RuntimeInnovations from IMT, Information Manage-ment Technology AG

Since the company was founded in 1991, we have been imple-menting over 2’500 projects for globally active companies as an engineering service provider. We are specialized in the develop-ment of high-precision measurement and control technology, innovative hardware and software solutions for life-supporting systems and smart embedded systems. As pioneers of “IoT” devices, we have realized successful hardware and software solutions for 30 years. We are experts in the design and imple-mentation of complex systems. Smart solutions, controlled by artificial intelligence (AI), are our daily routine.

RISER – this is our trade fair robot that demonstrates, how an embedded system is modelled with Dataflow Studio in a very short time.

RISER – comes from RISC-V Segway Robot

EmbeddedSystem Design

DATAFLOW Studio – Guarantees a Clear, Consistent System Architecture

With Dataflow Studio, you can model your system architecture – always graphically supported – clearly and comprehensibly, define interfaces, the software architecture and the distribution of the mechanics, electronics and software subsystems. You use it to design software components and implement them with automatically generated software code.

#include „TutorialApplication.h“

// imt.base.cpp includes#include <Imt.Base.Cpp.Erof.Tasking/Schedu#include <Imt.Base.Cpp.Hal/I2CMaster.h>#include <Imt.Base.Cpp.Hal/Hardware.h>#include <Imt.Base.Cpp.Hal/SystemClock.h>#include <Imt.Base.Cpp.Hal.STM32/AdcDriv#include <Imt.Base.Cpp.Hal.STM32/STM32I

// tutorial includes

// diagnostics, must be last include#include <Imt.Base.Cpp.Core/Diagnostics.h>

TutorialApplication::TutorialApplication() {}

TutorialApplication::~TutorialApplication() {}

void TutorialApplication::onAddController() { registerItem(m_readInputController); registerItem(m_writeOutputController); registerItem(m_applicationController);}

void TutorialApplication::initializeHardware() { // init assert handler initActionManager(); // initialize the hardware Hardware::initialize(); // init system clock SystemClock::initSystemClock(); // init adc// imt.base.cpp includes#include <Imt.Base.Cpp.Erof.Tasking/Schedu#include <Imt.Base.Cpp.Hal/I2CMaster.h>#include <Imt.Base.Cpp.Hal/Hardware.h>#include <Imt.Base.Cpp.Hal/SystemClock.h>#include <Imt.Base.Cpp.Hal.STM32/AdcDriv#include <Imt.Base.Cpp.Hal.STM32/STM32I

// tutorial includes

// diagnostics, must be last include#include <Imt.Base.Cpp.Core/Diagnostics.h>

TutorialApplication::TutorialApplication() {}

TutorialApplication::~TutorialApplication() {}

SystemArchitectureDesign

DATAFLOW Runtime – Fast, Reliable Real-time Operating System

The smart, event-based real-time operating system Dataflow Runtime guarantees best real-time performance and data race-free process communication. Basic functionalities such as in-terrupt handling, communication interfaces, file systems and task scheduling form the basis of your application. You can use Dataflow “Analysis” for real-time testing and debugging. The ap-plication level debugging of distributed systems, as well as the monitoring and recording of individual values and signals, are integrated.

Run-to-Completion Processes

We are a Silver Member of the RISC-V Foundation

As a silver member of the RISC-V Foundation since 2015, we have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. The RISC-V-Foundation has a Board of Directors comprising repre-sentatives from Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.

RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. The RISC-V Foundation comprises more than 100 member organizations building an open, collaborative community of software and hard-ware innovators powering innovation at the edge forward. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. The non-profit corporation directs future development and drives the adoption of the RISC-V ISA.

Fast, smallIt features a preemptive, priority based, time slice Run-to-com-pletion (RTC) task operating system that implements the inver-sion of control pattern. The processes are called Active Parts (AP). Separation of concerns is implemented as Communication separates Execution. The memory footprint of the core counts less than 10 KB of code and data.

Low power, smart an lean“Go-to-sleep after last activity executed” and triggered by ex-ternal events is the key for designing low power devices. the Managed Single Stack helps save memory. Reactive, event based message passingEvent based messages are issued in Active Part. Counter wise the information from other partners in the system will be re-ceived by active parts. The message content is freely definable by basic or compound data types. Dataflow runtime incorpo-rates a sophisticated hardware- and software interrupt solution that results in response and latency times far below than a microsecond.

Secure communication channelsUser defined messages were distributed over Channels. Com-munication channels offer different communication types like “one-to-one” one-to-many “one-to-any or many-to-one”. This leads to Lock-free and Data-race-free designs.

High computing powerFor high speed processing needs the runtime supports sym-metric multiprocessing until four cores. Asymmetric multiproc-essing is given by design of the kernel.

SafetyWe provide optional certification packages according medical standards EN-60101-1, EN 62304 as well as MISRA compliancy. Many CPU architectures and platforms are supported like ARM, ColdFire and RISC-V.

New Era ofMicro Processor Innovation

DATAFLOW RISC-V – Supports Multicore, High Speed on Chip Network Communication and DebuggingFor a high-performance multicore application, we designed a grid network computing system, which supports applications like “Artificial Intelligence” and high-performance on-the-edge “IoT” solutions. This design supports ideally our Dataflow Runt-ime (RTOS).

DATAFLOW RISC-V – is Developed Under Clean Safety Provisions By following a strict V-Modell based development according to EN62304 and EN60101-1, the DATAFLOW RISC-V carries an extensive quality and safety documentation for the use in medi-cal and certified environments.

DATAFLOW RISC-V – is Supported by Standard Development Tool ChainsThe standard GCC/GDB toolchain supports the RISC-V ISA for C and C++ application developments. By providing the JTAG interface and appropriate drivers, most IDE’s with RISC-V sup-port can be used for programming. With Dataflow Studio, we provide an integrated development solution.

DATAFLOW RISC-V – Carries out a High Performance 5 Stage Single-Cycle Instruction ImplementationIt features a complete RV32-G and RV64-G 5-stage pipeline according to Instruction Set Manual, User-Level ISA Version 2.2 and Privileged Architecture Version 1.9. It supports med-ical grade implementation certified according to EN 62304. High-performance Integer- and Floating point Multiplication- and Division Unit guarantees best performance results in the benchmarks.

DATAFLOW RISC-V – Prepared for Customized SolutionsIt is completely written in VHDL and is highly configurable for custom implementations. Thanks to modular software architec-ture, we are able to easily add new costumer features from the upcoming standard or the customer needs.

DATAFLOW RISC-V – Offers a Complete System on Chip Solution with a Strict Harvard ArchitectureWe provide memory interface and -controller, data and instruc-tion memory Interfaces. Peripherals like SPI master and slave, UART’s, Master Debug Acces Port (MDAP), PWM, GPIO. The CLINT device handles all exception states of the CPU. JTAG per core is natively supported. For event-based system function-ality, the configurable PLIC Interrupt Controller guarantees the highest system performance and lowest latency.

IMT Information Management Technology AGGewerbestrasse 8 . 9470 Buchs

Phone +41 81 750 06 40 . Fax +41 81 750 06 40info@imt.ch . www.imt.ch