Dataflow Model

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    VLSISYSTEMDESIGNMODULEI 1

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    Dataflow Modelin 1 2

    but not for complex designs.

    Desi ners can desi n more effectivel if the concentrate on

    implementing the function at a level of abstraction higher

    than gate level.

    Dataflow modeling provides a powerful way to implement a

    design.

    Verilog allows a circuit to be designed in terms of the data

    flow between registers and how a design processes data

    rather than instantiation of individual gates.

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    Dataflow Modelin 2 2

    With ate densities on chi s increasin ra idl , dataflow

    modeling has assumed great importance.

    Currently, automated tools are used to create a gate-level

    circuit from a dataflow design description. This process is

    called logic synthesis.

    The data flow modeling allows the designer to concentrate on

    optimizing the circuit in terms of data flow.

    In the digital design community, the term RTL (Register

    Transfer Level) design is commonly used for a combination of

    dataflow modeling and behavioral modeling.

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    This level of abstraction level resembles like that of boolean

    equation representation of digital systems.

    The dataflow assignments are called Continuous Assignments.

    Continuous assignments are always active.

    Syntax: assign #(delay) target = expression;

    A Verilog module can contain any number of continuous

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    ass gnmen s a emen s, an a s aemen s execu e concurren y.

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    LHS target -> always a net, not a register.

    RHS -> registers, nets or function calls.

    Delay values can be specified in terms of time units.

    Whenever an event (change of value) occurs on any operand

    used on the RHS of an expression, the expression is

    evaluated and assigned to the LHS target.

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    Regular continuous assignment.

    wire mux_out, a_in, b_in, sel_in;

    ass gn mux_ou = se _ n _ n : a_ n;

    .

    wire a_in, b_in, sel_in;

    wire mux_out = sel_in ? b_in : a_in;

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    wire and_out;

    assign and_out = i1 & i2; // regular continuous assignment

    wire exor_out = i1[31:0] ^ i2[31:0] // implicit assignment

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    Example

    module enerate_mux

    (data,select,out);input [0:7] data;

    OUTMUXATA

    input [0:2]select;

    output out;w re ou ;

    assign out = data[select];SELECT

    Note: Non- constant index in expression on RHS generates MUX

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    Exam le

    module enerate decoder

    (data,select,out);input data;

    DECODERAT

    A

    input [0:1]select;

    output [0:3] out;

    OUT

    w re : ou ;

    assign out[select]=data;SELECT

    -

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    Example

    module enerate_mux

    (a,b,f,s);input a,b;

    fMUX

    a

    b

    input s;

    output f;w re ;

    assign f = s? a : b;s

    Note: Conditional Operator generate MUX

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    Delay values control the time between the change in a right

    hand-side operand and when the new value is assigned to

    - .

    Regular assignment delay

    mp c con nuous ass gnmen e ay

    Net declaration dela

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    The delay value is specified after the keyword assign.

    Any change in values of in1 or in2 will result in a delay of 10 time units before

    recomputation of the expression in1 & in2, and the result will be assigned to out.

    Example:

    module and_ex(and_out , a_in, b_in);

    in ut a in b in_ _

    output and_out;

    wire and_out;

    ass gn an _ou = a_ n _ n;endmodule

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    wire out;

    ass gn out = ; egu ar ass gnment e ay

    The inertial delay of real circuits is modeled through

    regular assignment delay.

    An event on the RHS si nals which is not lastin for the

    amount of inertial delay specified will not have any effect on

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    .

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    in1in1

    in2in2

    outout

    1010 2020 3030 6060 7070 8080 8585

    VLSISYSTEMDESIGN7/24/2011 VERILOG HDL PRESENTATION 15MODULEI 15

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    An equivalent method is to use an implicit continuous assignment to

    Exam le:

    specify both a delay and an assignment on the net.

    module and_ex(and_out , a_in, b_in);

    npu a_ n, _ n;

    output and_out;

    wire #10 and_out = a_in & b_in;

    endmodule

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    A delay can be specified on a net when it is declared without

    putting a continuous assignment on the net.

    If a delay is specified on a net out, then any value change applied

    Example:

    o e ne ou s e aye accor ng y.

    _ _ , _ , _

    input a_in, b_in;

    output and_out;

    wire #10 and_out;assign and_out = a_in & b_in;

    endmodule

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