ELEC 2200-002 Digital Logic Circuits Fall 2015 Switching Algebra (Chapter 2) Vishwani D. Agrawal...

ELEC 2200-002Digital Logic Circuits

Fall 2015Switching Algebra (Chapter 2)

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal

[email protected]

Fall 2015, Sep 30 . . .Fall 2015, Sep 30 . . . ELEC2200-002 Lecture 4ELEC2200-002 Lecture 4 11

Switching Algebra

A Boolean algebra, where Set K contains just two elements, {0, 1}, also

called {false, true}, or {off, on}, etc. Two operations are defined as, + ≡ OR, · ≡

AND.


+ 0 1

0 0 1

1 1 1

· 0 1

0 0 0

1 0 1

Claude E. Shannon (1916-2001)Claude E. Shannon (1916-2001)


http://www.kugelbahn.ch/sesam_e.htm

Shannon’s Legacy

A Symbolic Analysis of Relay and Switching Circuits, Master’s Thesis, MIT, 1940. Perhaps the most influential master’s thesis of the 20th century.

An Algebra for Theoretical Genetics, PhD Thesis, MIT, 1940.

Founded the field of Information Theory.

C. E. Shannon and W. Weaver, The Mathematical Theory of Communication, University of Illinois Press, 1949. A “must read.”


Switching Devices

Electromechanical relays (1940s)

Vacuum tubes (1950s)

Bipolar transistors (1960 - 1980)

Field effect transistors (1980 - )

Integrated circuits (1970 - )

Nanotechnology devices (future)


Example: Automobile Ignition

Engine turns on when

Ignition key is applied ANDCar is in parking gear OR

Brake pedal is on

ANDSeat belt is fastened OR

Car is in parking gear


Switching logicSwitching logic


Battery

Key

Parking gear

Brake pedal Parking gear

Seat belt

Motor

Define Boolean VariablesDefine Boolean Variables


Battery

Key

Parking gear


Seat belt

Motor

K = {0, 1}

P = {0, 1}

B = {0,1} P = {0, 1}

S = {0, 1}

0 means switch “off” or “open”1 means switch “on” or “closed”

M = {0, 1}

Write Boolean FunctionWrite Boolean Function


Battery

Key

Parking gear


Seat belt

Motor

K = {0, 1}

P = {0, 1}

B = {0,1} P = {0, 1}

S = {0, 1}

Ignition function:

M = K AND (P OR B) AND (S OR P) = K(P + B)(S + P)

M = {0, 1}

Simplify Boolean FunctionSimplify Boolean Function


M = K AND (P OR B) AND (S OR P)

= K(P + B)(S + P)

= K(P + B)(P + S) Commutativity

= K (P + B S) Distributivity

Construct an Optimum CircuitConstruct an Optimum Circuit


Battery

Key

Parking gear

Brake pedal Seat belt

Motor

K = {0, 1}

P = {0, 1}

B = {0,1} S = {0, 1}

M = K (P + B S)

M = {0,1}

This is a relay circuit.Earlier logic circuits, even computers,were built with relays.

Implementing with Relays

An electromechanical relay contains:Electromagnet

Current source

A switch, spring-loaded, normally open or closed

Switch has two states, open (0) or closed (1).

The state of switch is controlled by “not applying” or “applying” current to electromagnet.


One Switch Controlling Other

Switches X and Y are normally open.

Y cannot close unless a current is applied to X.


XY

Y = X

Inverting Switch

Switch X is normally closed and Y is normally open.

Y cannot open unless a current is applied to X.


XY

Y = X

Boolean Operations

AND – Series connected relays.

OR – Parallel relays.


A BF

F = A B

BF

A

F = A + B

Complement (Inversion)


AF

F = A

B

F

A

F = A + B

= A · B

Relay ComputersRelay ComputersConrad Zuse (1910-1995)Conrad Zuse (1910-1995)


Z1 (1938)

Z3 (1941)

Electronic Switching DevicesElectronic Switching Devices


Electron TubeFleming, 1904

de Forest, 1906

Point Contact TransistorBardeen, Brattain, Shockley, 1948

Transistor, 1948 Transistor, 1948


The thinker, the tinkerer, the visionary and the transistorJohn Bardeen, Walter Brattain, William Shockley

Nobel Prize, 1956

Bell Laboratories, Murray Hill, New Jersey


Bipolar Junction Transistor (BJT)Bipolar Junction Transistor (BJT)

Fall 2015, Sep 30 . . .Fall 2015, Sep 30 . . . ELEC2200-002 Lecture 4ELEC2200-002 Lecture 42222

Field Effect Transistor (FET)Field Effect Transistor (FET)


a.k.a.metal oxidesemiconductor(MOS) FET.

(metaloxide)

Integrated Circuit (1958)Integrated Circuit (1958)


Jack Kilby (1923-2005), Nobel Prize, 2000

MOSFET (Metal Oxide Semiconductor MOSFET (Metal Oxide Semiconductor Field Effect Transistor)Field Effect Transistor)


Gate

Drain

Source

Gate

Drain

Source

NMOSFET PMOSFET

Shortor

Open

Shortor

Open

VGS VGS

VGS = 0, openVGS = high, short

VGS = 0, shortVGS = high, open

Reference:R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Third Edition, McGraw Hill.

NMOSFET NOT Gate (Early Design)NMOSFET NOT Gate (Early Design)


Ground = 0 volt

Power supplyVDD volts

w.r.t. ground

AA

Problem: When A = 1,current leakage causespower dissipation.

Solution: ComplementaryMOS design proposed by

F. M. Wanlass and C.-T. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes,” International Solid State Circuits Conference Digest of Technical Papers, Feb 20, 1963, pp. 32-33.

A: Boolean variable

A = VDD volts; 1, true, onA = 0 volt; 0, false, off

CMOS CircuitCMOS Circuit


Wanlass, F. M. "Low Stand-By Power Complementary Field Effect Circuitry.“U. S. Patent 3,356,858 (Filed June 18, 1963. Issued December 5, 1967).

CMOS NOT Gate (Modern Design)CMOS NOT Gate (Modern Design)


VDD = 1 volt; voltage depends on technology.

Ground

A A

A = VDD = 1 volt is state “1”A = GND = 0 volt is state “0”

Power supply

GND

Truth Table

A A

0 1

1 0

A A

ElectricalCircuit

Symbol

Boolean Function

CMOS Logic Gate: NANDCMOS Logic Gate: NAND


VDD

A F

GND

Truth Table

A B F

0 0 1

0 1 1

1 0 1

1 1 0

A

B

B

F

ElectricalCircuit

Boolean FunctionSymbol

CMOS Logic Gate: NORCMOS Logic Gate: NOR


VDD

A

F

GND

Truth Table

A B F

0 0 1

0 1 0

1 0 0

1 1 0

A

B

B

F

ElectricalCircuit

Boolean Function

Symbol

CMOS Logic Gate: ANDCMOS Logic Gate: AND


Truth Table

A B F

0 0 0

0 1 0

1 0 0

1 1 1

A

BF

Boolean Function

Symbol

A

BFF ≡

CMOS Logic Gate: ORCMOS Logic Gate: OR


Truth Table

A B F

0 0 0

0 1 1

1 0 1

1 1 1

F

Boolean Function

Symbol

FF≡

A

B

A

B

CMOS Gates

Logic functionNumber of transistors

1 or 2 inputs N inputs

NOT 2 -

AND 6 2N + 2

OR 6 2N + 2

NAND 4 2N

NOR 4 2N


Optimized Ignition LogicOptimized Ignition Logic


M = K (P + B S) = KP + KBS

K

P

KP

SB

KBS

M

3 gates, 20 transistors. Can we reduce transistors?

Further OptimizationFurther Optimization


M = K (P + B S) = KP + KBS (Distr. law)

= KP + KBS (Theorem 3, involution)

= KP · KBS (De Morgan’s theorem)

K

P

KP

SB

KBS

M

3 gates, 14 transistors.

NAND gates4+6 transistors

BinaryArithmetic

Switching

Theory

Semiconductor

Technology

Digital SystemsDigital Systems


Boolean

Algebra

DIGITALCIRCUITS

Digital Logic Design

Representation of switching function:Truth table

Canonical forms

Karnaugh map

Logic minimization: Minimize number of literals.

Technology mapping: Implement logic function using predesigned gates or building blocks from a technology library.


Truth TableTruth table is an exhaustive description of a switching function. Contains 2n input combinations for n variables.

Example: f(A,B,C) = A B +A,B,C) = A B +A C + AA C + ACC


n Input variables, n = 3 Output

A B C f(A,B,C)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 1

2n = 8 rows

How Many Switching Functions?Output column of truth table has length 2n for n input variables.

It can be arranged in ways for n variables.

Example: n = 1, single variable.


n22

Input Output functions

A F1(A) F2(A) F3(A) F4(A)

0 0 0 1 1

1 0 1 0 1

DefinitionsBoolean variable: A variable denoted by a symbol; can assume a value 0 or 1.

Literal: Symbol for a variable or its complement.

Product or product term: A set of literals, ANDed together. Example, a bc.

Cube: Same as a product term.

Sum: A set of literals, Ored together. Example, a + b +c.


More DefinitionsSOP (sum of products): A Boolean function expressed as a sum of products.


POS (product of sums): A Boolean function expressed as a product of sums.

Example:f(A,B,C) = (A +B +C) (A + B +C) ( A +B + C)


MintermA product term in which each variable is present either in true or in complement form.

For n variables, there are 2n unique minterms.


Minterm Product

m0 A BCm1 A B Cm2 A BCm3 A B Cm4 A BCm5 A B Cm6 A B Cm7 A B C

Minterms are Canonical FunctionsMinterms are Canonical Functions


000 001 010 011 100 101 110 111

Input

Val

ue

of

min

term

1

0

m0 m1 m2 m3 m4 m5 m6 m7

Canonical SOP Forma.k.a. Disjunctive Normal Form (DNF)

A Boolean function expressed as a sum of minterms.


= = AABC +BC +ABC + AABC + ABBC + ABC + ABC + ABCC + ABC

= m= m11+m+m33+m+m44+m+m66+m+m77 = = m(1, 3, 4, 6, 7) m(1, 3, 4, 6, 7)


Row No. A B C f(A,B,C)

0 0 0 0 0

1 0 0 1 1

2 0 1 0 0

3 0 1 1 1

4 1 0 0 1

5 1 0 1 0

6 1 1 0 1

7 1 1 1 1Tru

th ta

ble

with

ro

w n

um

bers

MaxtermA summation term in which each variable is present either in true or in complement form.

For n variables, there are 2n unique maxterms.


Maxterm Sum

M0 A + B + CM1 A + B +CM2 A +B + CM3 A +B +CM4 A + B + C M5 A + B +C M6 A +B + C M7 A + B + C

Canonical POS Forma.k.a. Conjunctive Normal Form (CNF)

A Boolean function expressed as a product of maxterms.


= (A + B + C)(A += (A + B + C)(A +B + C)(B + C)(A + B +A + B +C)C)

= M= M00 M M22 M M55 = = M(0, 2, 5) M(0, 2, 5)


Row No. A B C f(A,B,C)

0 0 0 0 0

1 0 0 1 1

2 0 1 0 0

3 0 1 1 1

4 1 0 0 1

5 1 0 1 0

6 1 1 0 1

7 1 1 1 1Tru

th ta

ble

with

ro

w n

um

bers

Canonical Forms are UniqueA canonical form completely defines a Boolean function. That is, for every input the canonical form specifies the value of the function.

To determine canonical form:Construct truth table and sum minterms corresponding to 1 outputs, or multiply maxterms corresponding to 0 outputs.

Alternatively, use Shannon’s expansion theorem (see Section 2.2.3, page 101).

Two Boolean functions are identical if and only if their canonical forms are identical.


Why Generate Canonical Form?

Example: Are the following Boolean Functions Identical?

Generate canonical forms, e.g., minterms, and compare.


D BD C B AF3

D C BD B AD C AF2

D C AD B AD B

AF1

Algebraic Procedure

Expand each term to contain all variables

RememberPostulate 6: Complement

Postulate 2: Identity elements

a + 0 = a, 0 is identity element for +

a · 1 = a, 1 is identity element for dot (·)


0aa

1aa


identical. are functions three ,Hence

)15 ,13 ,11 ,7 ,5(m3F

)15 ,13 ,11 ,7 ,5(mF2

Similarly,

)15 ,13 ,11 ,7 ,5(m

mmmmm

CDBAABCDDCABABCDDCBABCD

)BB(ACD)CC(ABD)CC(BD

ACDABDBD

11131557

A

A

A F1

Karnaugh Map

1952: Edward M. Veitch invented a graphical procedure for digital circuit optimization.

1953: Maurice Karnaugh perfected the map procedure:

“The Map Method for Synthesis of Combinational Logic Circuits,” Trans. AIEE, pt I, 72(9):593-599, November 1953.


Karnaugh Map: 2 Variables, A, BKarnaugh Map: 2 Variables, A, B


A = 0 A = 1

B = 0

B = 1

m0

m1

m2

m3

m3 = AB = 11(numerical interpretation)

00

01

10

11

UnitHammingdistancebetweenadjacent cells

Each cell isa minterm

Representing a FunctionRepresenting a Function


A = 0 A = 1

B = 0

B = 1

m0

m1

m2

m3

0

1

2

3

Place 1 in cellscorresponding tominterms in canonical form.For example, see F = A B + ABrepresented on the left.

1

1

Truth Table

A B F

0 0 0

0 1 0

1 0 1

1 1 1

Grouping Adjacent MintermsGrouping Adjacent Minterms


A = 0 A = 1

B = 0

B = 1

m0

m1

m2

m3

0

1

2

3

Adjacent cells differ inone variable, which iseliminated.

For example, F = A B + AB = A(B +B) = A1

1

Product term A

Karnaugh Map MinimizationCanonical SOP form represented on map

Example: F = AB + A B +A B

Find minimal cover (fewest groups of largest sizes),

F = A + B


A = 0 A = 1

B = 0

B = 1

m0

m1

m2

m3

1

11

product A

product B

A

B

F

Karnaugh Map: 3 Variables, A, B, CKarnaugh Map: 3 Variables, A, B, C


0 2 6 4

1 3 7 5

A

B

C

000

001

010

011

110

111

100

101

Check unit Hamming distance between adjacent cells.

Synthesizing a Digital FunctionStart with specification.

Create a truth table from specification.

Minimize (SOP with fewest literals):Either write canonical SOP

Reduce using postulates and theorems

Or find largest cubes from Karnaugh map

Minimized SOP gives a two-level AND-OR circuit.

NAND or NOR circuit for CMOS technology can be found using de Morgan’s theorem.


Example: Multiplexer

Inputs: A, B, C

Output: F

Function:F = A, when C = 1

F = B, when C = 0


3-Input Function: Multiplexer

Truth Table

row A B C F

0 0 0 0 0

1 0 0 1 0

2 0 1 0 1

3 0 1 1 0

4 1 0 0 0

5 1 0 1 1

6 1 1 0 1

7 1 1 1 1


0 2 6 4

1 3 7 5

A

B

C

1

1

1

1

F = A C + BC

A C

BC

A

C

B

F

Technology Optimization


F = A C + BCA

C

B

F

A

C

B

F

2 + 6 + 6 + 6 = 20 transistors

Optimized Multiplexer


A

C

B

F

X

Y

theorem sMorgan' de from

YXYXF

A

C

B

F

X

Y2 + 4 + 4 + 4 = 14 transistors

Karnaugh Map: 4 Variables, A, B, C, DKarnaugh Map: 4 Variables, A, B, C, D

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


Check unit Hamming distance between adjacent cells.

A

B

D

C

Adjacency of Edge CellsAdjacency of Edge Cells


0

1

3

2

8

9

11

10

0 4 12 810 14 6 2

Reexamine Three Functions from Slide 48

Example: Are the following Boolean Functions Identical?

This time generate Karnaugh maps, and compare.


D BD C B AF3

D C BD B AD C AF2

D C AD B AD B

AF1

Karnaugh Map of F1Karnaugh Map of F1

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


.

A

B

D

C

D C AD B AD B AF1

F1 = Σm(5, 7, 11, 13, 15)

1 1

1 1 1


0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


.

A

B

D

C

D C BD B AD C AF2

F2 = Σm(5, 7, 11, 13, 15) ⇒ F1 and F2 cover same area on map.

1 1

1 1 1


0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


.

A

B

D

C

D BD C B AF3

F3 = Σm(5, 7, 11, 13, 15) ⇒ F1, F2 and F3 cover exactly thesame area on map, hence, they are identical.

1 1

1 1 1

Ignition FunctionMinterm K P B S M

0 0 0 0 0 0

1 0 0 0 1 0

2 0 0 1 0 0

3 0 0 1 1 0

4 0 1 0 0 0

5 0 1 0 1 0

6 0 1 1 0 0

7 0 1 1 1 0

8 1 0 0 0 0

9 1 0 0 1 0

10 1 0 1 0 0

11 1 0 1 1 1

12 1 1 0 0 1

13 1 1 0 1 1

14 1 1 1 0 1

15 1 1 1 1 1Fall 2015, Sep 30 . . .Fall 2015, Sep 30 . . . ELEC2200-002 Lecture 4ELEC2200-002 Lecture 4 7171

M = K AND (P OR B) AND (S OR P)

= K(P + B)(S + P)

Karnaugh Map: M(K, P, B, S)Karnaugh Map: M(K, P, B, S)

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


.

K

P

S

B

1

1

1 1

1

Karnaugh Map: Minimum CoverKarnaugh Map: Minimum Cover

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10


.

K

P

S

B

1

1

1 1

1

KP

KBS

Minimized FunctionMinimized Function


M = KP + KBS

KP

BS

M

Using Inverting GatesUsing Inverting GatesBecause They Need Fewer TransistorsBecause They Need Fewer Transistors


M = KP + KBS

= KP · KBS Using de Morgan’s Theorem

KP

BS

M

Karnaugh Map on the WebKarnaugh Map on the Web


http://www.ee.calpoly.edu/media/uploads/resources/KarnaughExplorer_1.html

Minterm Clusters, Cubes or ProductsMinterm Clusters, Cubes or Products

0

14 12 8

1 5

113

19

3 7 15

111

1

2 6 14

110

1


Larger clusters are products with fewer variables.

A

B

D

C

DCBA

DCB

AC

ABD

ProductProduct


More variables in a product mean more transistors (hardware).

ABCD

DCBADCBAP 1

P1A

B

C

D

GROUND

VDD = 1 volt

PM

OS

tra

nsi

sto

rs

NMOS transistors

Signals are voltagesw.r.t. GROUNDA = 0 or 1 voltB = 0 or 1 voltC = 0 or 1 voltD = 0 or 1 volt

P1 =0 or 1 volt

ProductProduct


Fewer variables in a product mean fewer transistors (hardware).

A

C

ACACP 2

P2

A

C

GROUND

VDD = 1 volt

Signals are voltagesw.r.t. GROUNDA = 0 or 1 voltB = 0 or 1 voltC = 0 or 1 voltD = 0 or 1 volt P1 =

0 or 1 volt

ObservationsA larger minterm cluster is a product with fewer variables; requires fewer transistors.

Each gate input needs two transistors.

Smaller number of clusters is more efficient: Fewer gates to generate products.

Fewer inputs for the OR gate to produce the function.

Direct minterm implementation is most inefficient.


ELEC 2200-002 Digital Logic Circuits Fall 2015 Switching Algebra (Chapter 2) Vishwani D. Agrawal...

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