Vishwani D. Agrawal James J. Danaher Professor

Spring 2014, Mar 5 . . .Spring 2014, Mar 5 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2014Spring 2014A Linear Programming Solution to Clock A Linear Programming Solution to Clock

Constraint ProblemConstraint ProblemVishwani D. AgrawalVishwani D. Agrawal

James J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn University, Auburn, AL 36849ECE Department, Auburn University, Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html


A General Sequential CircuitA General Sequential Circuit

CombinationalLogic

Registers

Clock

Inputs Outputs


A Level-Sensitive LatchA Level-Sensitive LatchD

CK

Q

QN

Clock period, Tck

CKtime

Latch open Latch closed Latch open


Alternative ImplementationAlternative Implementation

D

CK

Q

J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,How It Fails, Wiley Interscience, 2004, p.137.


Data Must be Stable Before Latch ClosesData Must be Stable Before Latch Closes

1

1

0

01

D = 0 → 1 → 1

CK = 1 → 1 → 0Q

QN

Clock period, Tck

CKtime

Latch open Latch closed

0→1→0→0→

1→1→0→0→

0→0→1→0→1→

1→0→1→0→1→

Unstable state

Stable data

delays


Data and Clock ParametersData and Clock Parameters

Clock period, Tck

CKtimeLatch open Latch closed

Dtime

Stable data

Stable QQtime

Setup time Hold time

CK-to-Q delay


Design With Level-Sensitive LatchesDesign With Level-Sensitive Latches

Comb.Logic

Lev

el-s

ens

. La

tch

es

PI

PO

Comb.Logic

Lev

el-s

ens

. La

tch

es

PI

POCK


Edge-Triggered Flip-flopEdge-Triggered Flip-flop

D

CK

Q

QN

Clock period, Tck

CKtime

Master open Slave open

Master latch Slave latch

Trigger edgesSetup time

Hold time

CK-to-Q delay


A Dynamic ImplementationA Dynamic Implementation

D Q

CK

CK

CK

CK

VDD

GND

J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 229.


A Static ImplementationA Static Implementation

D

Q

CK

CK

CK

CK

VDD

GND

J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 230.


Design With Edge-Triggered Flip-FlopsDesign With Edge-Triggered Flip-Flops

CombinationalLogic

Flip-flops

Clock

Inputs Outputs


Setup Time ConstraintSetup Time Constraint

FF i FF jCombinational path delay

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

Tsi Thi

Tc.Qi

Clock edge

time

Tck

Tsj

Constraint: si + Tc.Qi + Δ(i,j) ≤ sj + Tck – Tsj

i.e., Δ(i,j) ≤ Tck – Tsj – Tc-Qi + sj – si

This is known as long path constraint – prevents zero clocking

Note: All times for aFF should be adjustedby its clock skew.

Arrive nolater thanthis

Traveltime

Skew si Skew sj


Hold Time ConstraintHold Time Constraint

FF i FF jCombinational path delay

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

Tsi Thi

Tc.Qi

Clock edge (si)

time

Tck

Tsj

Constraint: si + Tc.Qi + δ(i,j) ≥ sj + Thj

i.e., δ(i,j) ≥ Thj – Tc.Qi + sj – si

sj – si + Thj

This is known as short path constraint – avoids double clocking

Note: All times for aFF should be adjustedby its clock skew.

Skew si Skew sj


Solving Hold Time Problem (1)Solving Hold Time Problem (1)

PO(FFi)

PO(FFj)PI

(FFi)

PI(FFj)

POPI

Fanout node

Internal edges (fixed delays)External edges (variable delays)



Variables:Variables: Shortest arrival time at node i = aiShortest arrival time at node i = ai Longest arrival time at node i = AiLongest arrival time at node i = Ai Buffer delay on external edge (i,j) = wijBuffer delay on external edge (i,j) = wij

Constants:Constants: At PI i: Ai = At PI i: Ai = ΛΛi i and ai = and ai = λλi, i, user specified.user specified. At PI (FF) i: Ai = ai = Tc.Qi At PI (FF) i: Ai = ai = Tc.Qi



Constraints:Constraints: At PO i: Ai At PO i: Ai ≤ Ri and ai ≥ ri, user defined.≤ Ri and ai ≥ ri, user defined. At PO (FF) i:At PO (FF) i:

ai ≥ Thi, short path constraint.ai ≥ Thi, short path constraint. Ai ≤ Tck – Tsi, long path constraint.Ai ≤ Tck – Tsi, long path constraint.

Optimization function (a linear approximation to Optimization function (a linear approximation to minimum number of delay buffers):minimum number of delay buffers):

minimize minimize ∑ ∑ wijwijall externalall externaledges (i,j)edges (i,j)


Linear Programming Solution (1)Linear Programming Solution (1)minimize minimize ∑ ∑ wijwij

all externalall externaledges (i,j)edges (i,j)

Subject to: Aj ≥ Ai + wij for all i ε Fanin(j)aj ≤ ai + wij for all i ε Fanin(j)

Ai ≤ Ri for all i ε POai ≥ ri for all i ε PO

Ai ≤ Tck – Tsi for all i ε PO(FF i)ai ≥ Thi for all i ε PO(FF i)

Ai = Λi for all i ε PIai = λi for all i ε PI

Ai = Tqi for all i ε PI(FF i)ai = Tqi for all i ε PI(FF i)


Linear Programming Solution (2)Linear Programming Solution (2)

Solution inserts smallest delays in interconnects Solution inserts smallest delays in interconnects to satisfy short path constraints.to satisfy short path constraints.

Maintains the specified clock period and Maintains the specified clock period and satisfies setup time constraints.satisfies setup time constraints.

Reference: N. Maheshwari and S. S. Sapatnekar, Timing Analysisand Optimization of Sequential Circuits, Springer,

1999.

Shift Register Example 1 (Long Path)Shift Register Example 1 (Long Path)


F1 F2 F3

CK

s1 s2 s3

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

Δ ≤ Delay

s1 s2 s3

Δ Δ

Δ ≤ Delayt

0

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

Δ ≤ Delay Δ ≤ Delayt

0

T 2T

T 2T

Zero skew

Shift Register Example 1 (Short Path)Shift Register Example 1 (Short Path)


F1 F2 F3

CKs1 s2 s3

δ δ

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

t

0 T 2T

Zero skew F1

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

δ≥ Delay

t

0 T 2T Zero skew F2



F1 F2 F3

CKs1 s2 s3

δ δ

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

t

0 T 2T

F1

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

δ≥ Delay

t

0

T 2T

nonzero skew F2

F2

s1

s2



F1 F2 F3

CKs1 s2 s3

δ δ

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

δ ≥ Delay

t

0

T 2TF1

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

t

0 T 2T

F2

s2

s1

Shift Register Example 2 (Long Path)Shift Register Example 2 (Long Path)

Spring 2014, Mar 5 . . .Spring 2014, Mar 5 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)

2323

F1 F2 F3

CK

s1 s2 s3

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

Δ ≤ Delay

s1 s2 s3

Δ Δ

Δ ≤ Delayt

0

su ho

Ck-2-Q

su suho ho

Ck-2-Q Ck-2-Q

Δ ≤ Delay Δ ≤ Delayt

0

T 2T

T 2T

Zero skew

Vishwani D. Agrawal James J. Danaher Professor

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