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ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design
Spring 2008Spring 2008VerificationVerification
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
ECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL 36849
[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
VLSI Realization ProcessVLSI Realization Process
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22
Determine requirements
Write specifications
Design synthesis and Verification
Fabrication
Manufacturing test
Chips to customer
Customer’s need
Test development
Design
Manufacture
Origin of “Debugging”Origin of “Debugging”
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 33
D. Gizopoulos (Editor), Advances in Electronic Testing: Challenges and Methodologies, Springer, 2006, Chapter 3, “Silicon Debug,” by D. Josephson and B. Gottlieb.
Thomas Edison wrote in a letter in 1878: “It has been just so in all of my inventions. The first step is an intuition, and comes with a burst, then difficulties arise—this thing gives out and [it is] then that “Bugs” — as such little faults and difficulties are called — show themselves and months of intense watching, study and labor are requisite before commercial success or failure is certainly reached.” An interesting example of “debugging” was in 1945 when a computer failure was traced down to a moth that was caught in a relay between contacts (Figure 3-1).
Verification and TestingVerification and Testing
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44
Specification
Testing
Manufacturing
Verification
Hardware design
Silicon
50-70% cost 30-50% cost
DefinitionsDefinitions
Verification: Predictive analysis to ensure that the Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will synthesized design, when manufactured, will perform the given I/O function.perform the given I/O function.
Alternative Definition: Verification is a process used Alternative Definition: Verification is a process used to demonstrate the functional correctness of a to demonstrate the functional correctness of a design.design.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55
What is Being Verified?What is Being Verified?
Given a set of specification,Given a set of specification, Does the design do what was specified?Does the design do what was specified?
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66
Specification
Interpretation
RTL coding
Verification
J. Bergeron, Writing Testbenches: Functional VerificationOf HDL Models, Springer, 2000.
Avoiding Interpretation ErrorAvoiding Interpretation Error
Use redundancyUse redundancy
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77
Specification
Interpretation
RTL coding
Verification
Interpretation
Methods of VerificationMethods of Verification
Simulation: Verify input-output behavior for Simulation: Verify input-output behavior for selected cases.selected cases.
Formal verification: Exhaustively verify input-Formal verification: Exhaustively verify input-output behavior:output behavior: Equivalence checkingEquivalence checking Model checkingModel checking Symbolic simulationSymbolic simulation
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 88
Equivalence CheckingEquivalence Checking
Logic equivalence: Two circuits implement Logic equivalence: Two circuits implement identical Boolean function.identical Boolean function.
Logic and temporal equivalence: Two finite state Logic and temporal equivalence: Two finite state machines have identical input-output behavior machines have identical input-output behavior (machine equivalence).(machine equivalence).
Topological equivalence: Two netlists are Topological equivalence: Two netlists are identical (graph isomorphism).identical (graph isomorphism).
Reference: S.-Y. Hwang and K.-T. Cheng, Reference: S.-Y. Hwang and K.-T. Cheng, Formal Equivalence Checking and Design Formal Equivalence Checking and Design DebuggingDebugging, Springer, 1998., Springer, 1998.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99
Compare Two CircuitsCompare Two Circuits
Graphs isomorphic?Graphs isomorphic? Boolean functions identical?Boolean functions identical? Timing behaviors identical?Timing behaviors identical?
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010
a c
b
a c b
f f
Model CheckingModel Checking Construct an abstract model of the system, usually Construct an abstract model of the system, usually
in the form of a finite-state machine (FSM).in the form of a finite-state machine (FSM). Analytically prove that the model does not violate Analytically prove that the model does not violate
the properties (assertions) of original specification.the properties (assertions) of original specification. Reference: E. M. Clarke, Jr., O. Grumberg, and D. Reference: E. M. Clarke, Jr., O. Grumberg, and D.
A. Peled, A. Peled, Model CheckingModel Checking, MIT Press, 1999., MIT Press, 1999.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1111
Specification
Interpretation
RTL coding
Model checking
Assertions
RTL
Symbolic SimulationSymbolic Simulation
Simulation with algebraic symbols rather than Simulation with algebraic symbols rather than numerical values.numerical values.
Self-consistency: A complex (more advanced) Self-consistency: A complex (more advanced) design produces the same result as a much design produces the same result as a much simpler (and previously verified) design.simpler (and previously verified) design.
Reference: R. B. Jones, Reference: R. B. Jones, Symbolic Simulation Symbolic Simulation Methods for Industrial Formal VerificationMethods for Industrial Formal Verification, , Springer, 2002.Springer, 2002.
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Simulation: TestbenchSimulation: Testbench
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Design under
verification(HDL)
Testbench (HDL)
TestbenchTestbench HDL code:HDL code:
Generates stimuliGenerates stimuli Checks output responsesChecks output responses
Approaches:Approaches: BlackboxBlackbox WhiteboxWhitebox GreyboxGreybox
Metrics (unreliable):Metrics (unreliable): Statement coverageStatement coverage Path coveragePath coverage Expression or branch coverageExpression or branch coverage
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1414
Equivalence CheckingEquivalence Checking
Definition: Establishing that two circuits are Definition: Establishing that two circuits are functionally equivalent.functionally equivalent.
Applications:Applications: Verify that a design is identical to specification.Verify that a design is identical to specification. Verify that synthesis did not change the function.Verify that synthesis did not change the function. Verify that corrections made to a design did not Verify that corrections made to a design did not
create new errors.create new errors.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1515
Compare Two CircuitsCompare Two Circuits
Are graphs isomorphic?Are graphs isomorphic? YesYes Else, are Boolean functions identical?Else, are Boolean functions identical? YesYes Then, are timing behaviors identical?Then, are timing behaviors identical? YesYes
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a c
b
a c b
f f
ATPG Approach (Miter)ATPG Approach (Miter)
Redundancy of a stuck-at-0 fault, checked by ATPG, establishes equivalence of the corresponding output pair.
If the fault is detectable, its tests are used to diagnose the differences.
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Circuit 1(Verified design)
Circuit 2(Sythesized or
modified design)
stuck-at-0
stuck-at-0
Difficulties with MiterDifficulties with Miter
ATPG is NP-complete.ATPG is NP-complete. When circuits are equivalent, proving When circuits are equivalent, proving
redundancy of faults is computationally redundancy of faults is computationally expensive.expensive.
When circuits are different, test vectors are When circuits are different, test vectors are quickly found, but diagnosis is difficult.quickly found, but diagnosis is difficult.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1818
A Heuristic ApproachA Heuristic Approach
Derive V1, test vectors for all faults in C1.Derive V1, test vectors for all faults in C1. Derive V2, test vectors for all faults in C2.Derive V2, test vectors for all faults in C2. If the combined set, V1+V2, produces the same If the combined set, V1+V2, produces the same
outputs from the two circuits, then they are outputs from the two circuits, then they are probablyprobably equivalent. equivalent.
Reference: V. D. Agrawal, “Choice of Tests for Reference: V. D. Agrawal, “Choice of Tests for Logic Verification and Equivalence Checking Logic Verification and Equivalence Checking and the Use of Fault Simulation,” and the Use of Fault Simulation,” Proc. 13Proc. 13thth International Conf. VLSI DesignInternational Conf. VLSI Design, January 2000, , January 2000, pp. 306-311.pp. 306-311.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1919
Example Circuit C1Example Circuit C1
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2020
x1 x2 x3 x4
C1
C1 = x1 x3 x4 + x2 x3 + x2 x41 1 1
1 1 1 1
1
x3
x2
x4
x1
Tests
Example Circuit C2Example Circuit C2
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2121
x1 x2 x3 x4
C2
C2 = x1 x3 x4 + x2 x3 + x2 x41 1 1
1 1 1 1
1
x3
x2
x4
x1
Tests
C1 C1 ≡≡ C2 C2
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2222
1 1 1
1 1 1 1
1
x3
x2
x4
x1
Tests
1 1 1
1 1 1 1
1
x3
x2
x4
x1
Tests
C1 C2
C2’: Erroneous Implementation of C2C2’: Erroneous Implementation of C2
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x1 x2 x3 x4
C2’
C2 = x1 x3 x4 + x2 x3 + x2 x41 1 1
1 1 1
1
x3
x2
x4
x1
TestsC2’ = x1 x2 x3 x4 + x2 x3 + x2 x4
minterm deleted
Incorrect Result: C1 Incorrect Result: C1 ≡ ≡ C2’C2’
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C1 = x1 x3 x4 + x2 x3 + x2 x4
1 1 1
1 1 1
1
x3
x2
x4
x1
Tests
C2’ = x1 x2 x3 x4 + x2 x3 + x2 x4
minterm deleted
1 1 1
1 1 1 1
1
x3
x2
x4
x1
Tests
Additional SafeguardAdditional Safeguard
Simulate V1+V2 for equivalence: Output always 0 No single fault on PI’s detected Still not perfect
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C1(Verified design)
C2(Sythesized or
modified design)
s-a-0
s-a-1
0
Probabilistic EquivalenceProbabilistic Equivalence Consider two Boolean functions F and G of the same set Consider two Boolean functions F and G of the same set
of input variables {X1, . . . , Xn}.of input variables {X1, . . . , Xn}. Let f = Prob(F=1), g = Prob(G=1), xi = Prob(Xi=1)Let f = Prob(F=1), g = Prob(G=1), xi = Prob(Xi=1) For any arbitrarily given values of xi, if f = g, then F and G For any arbitrarily given values of xi, if f = g, then F and G
are equivalent with probability 1.are equivalent with probability 1. References:References:
J. Jain, J. Bittner, D. S. Fussell and J. A. Abraham, “Probabilistic J. Jain, J. Bittner, D. S. Fussell and J. A. Abraham, “Probabilistic Verification of Boolean Functions,” Formal Methods in System Verification of Boolean Functions,” Formal Methods in System Design, vol. 1, pp 63-117, 1992.Design, vol. 1, pp 63-117, 1992.
V. D. Agrawal and D. Lee, “Characteristic Polynomial Method for V. D. Agrawal and D. Lee, “Characteristic Polynomial Method for Verification and Test of Combinational Circuits,” Proc. 9Verification and Test of Combinational Circuits,” Proc. 9thth International Conf. VLSI Design, January 1996, pp. 341-342.International Conf. VLSI Design, January 1996, pp. 341-342.
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Simplest ExampleSimplest Example
F = X1.X2, F = X1.X2, f = x1 x2f = x1 x2 G = X1+X2, G = X1+X2, g = (1 – x1)(1 – x2)g = (1 – x1)(1 – x2)
= 1 – x1 – x2 + x1 x2= 1 – x1 – x2 + x1 x2 Input probabilities, x1 and x2, are randomly Input probabilities, x1 and x2, are randomly
taken from {0.0, 1.0}taken from {0.0, 1.0} We make a wrong decision if f = g, i.e.,We make a wrong decision if f = g, i.e.,
x1x2 = 1 – x1 – x2 + x1 x2x1x2 = 1 – x1 – x2 + x1 x2oror x1 + x2 = 1x1 + x2 = 1
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2727
Probability of Wrong DecisionProbability of Wrong Decision
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x1
x2
0
Randomly selected point (x1,x2)
x1 + x2 = 1
1.0
1.0
Probability of wrong decision= Random point falls on line {x1 + x2 = 1}= (area of line)/(area of unit square)= 0
Calculation of Signal ProbabilityCalculation of Signal Probability
Exact calculationExact calculation Exponential complexity.Exponential complexity. Affected by roundoff errors.Affected by roundoff errors.
Alternative: Monte Carlo methodAlternative: Monte Carlo method Randomly select input probabilitiesRandomly select input probabilities Generate random input vectorsGenerate random input vectors Simulate circuits F and GSimulate circuits F and G If outputs have a mismatch, circuits are not If outputs have a mismatch, circuits are not
equivalent.equivalent. Else, stop after “sufficiently” large number of vectors Else, stop after “sufficiently” large number of vectors
(open problem).(open problem).
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2929
References on Signal ProbabilityReferences on Signal Probability
S. C. Seth and V. D. Agrawal, “A New Model for S. C. Seth and V. D. Agrawal, “A New Model for Computation of Probabilistic Testability in Computation of Probabilistic Testability in Combinational Circuits,” Combinational Circuits,” INTEGRATION, The INTEGRATION, The VLSI JournalVLSI Journal, vol. 7, pp. 49-75, 1989., vol. 7, pp. 49-75, 1989.
V. D. Agrawal and D. Lee and H. WoV. D. Agrawal and D. Lee and H. Woźźniakowski, niakowski, “Numerical Computation of Characteristic “Numerical Computation of Characteristic Polynomials of Boolean Functions and its Polynomials of Boolean Functions and its Applications,” Applications,” Numerical AlgorithmsNumerical Algorithms, vol. 17, pp. , vol. 17, pp. 261-278, 1998. 261-278, 1998.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3030
More on Equivalence CheckingMore on Equivalence Checking
Don’t caresDon’t cares Sequential circuitsSequential circuits
Time-frame expansionTime-frame expansion Initial stateInitial state
Design debugging (diagnosis)Design debugging (diagnosis) Reference: S.-Y. Hwang and K.-T. Cheng, Reference: S.-Y. Hwang and K.-T. Cheng,
Formal Equivalence Checking and Design Formal Equivalence Checking and Design DebuggingDebugging, Springer, 1998., Springer, 1998.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3131
Methods of Equivalence CheckingMethods of Equivalence Checking
Satisfiability algorithmsSatisfiability algorithms ATPG methodsATPG methods Binary decision diagrams (BDD)Binary decision diagrams (BDD)
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3232
Shannon’s Expansion TheoremShannon’s Expansion Theorem
C. E. Shannon, “A Symbolic Analysis of Relay and C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” Switching Circuits,” Trans. AIEETrans. AIEE, vol. 57, pp. 713-723, , vol. 57, pp. 713-723, 1938.1938.
Consider:Consider: Boolean variables, X1, X2, . . . , XnBoolean variables, X1, X2, . . . , Xn Boolean function, F(X1, X2, . . . , Xn)Boolean function, F(X1, X2, . . . , Xn)
Then F = Xi F(Xi=1) + Xi’ F(Xi=0)Then F = Xi F(Xi=1) + Xi’ F(Xi=0) WhereWhere
Xi’ is complement of XiXi’ is complement of Xi Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1Cofactors, F(Xi=j) = F(X1, X2, . . , Xi=j, . . , Xn), j = 0 or 1
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Claude E. Shannon (1916-2001)Claude E. Shannon (1916-2001)
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3434
http://www.kugelbahn.ch/sesam_e.htm
Shannon’s LegacyShannon’s Legacy
A Symbolic Analysis of Relay and Switching CircuitsA Symbolic Analysis of Relay and Switching Circuits, , Master’s ThesisMaster’s Thesis, MIT, 1940. , MIT, 1940. Perhaps the most influential Perhaps the most influential master’s thesis of the 20master’s thesis of the 20thth century. century.
An Algebra for Theoretical Genetics, PhD ThesisAn Algebra for Theoretical Genetics, PhD Thesis, MIT, , MIT, 1940.1940.
Founded the field of Information Theory.Founded the field of Information Theory. C. E. Shannon and W. Weaver, C. E. Shannon and W. Weaver, The Mathematical The Mathematical
Theory of Communication, Theory of Communication, University of Illinois Press, University of Illinois Press, 1949. 1949. A “must read.”A “must read.”
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3535
TheoremTheorem
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(1)(1) F = Xi F(Xi = 1) + Xi’ F(Xi = 0)F = Xi F(Xi = 1) + Xi’ F(Xi = 0) ∀∀ i = 1,2,3, . . . n i = 1,2,3, . . . n
(2)(2) F = (Xi + F(Xi = 0)) (Xi’ + F(Xi = 1))F = (Xi + F(Xi = 0)) (Xi’ + F(Xi = 1)) ∀ ∀ i = 1,2,3, . . . ni = 1,2,3, . . . n
F
Xi
F(Xi = 0) F(Xi = 1)
0 1
Expansion About Two InputsExpansion About Two Inputs
F = XiXj F(Xi = 1, Xj = 1) F = XiXj F(Xi = 1, Xj = 1) + XiXj’ F(Xi = 1, Xj = + XiXj’ F(Xi = 1, Xj = 0)0)
+ Xi’Xj F(Xi = 0, Xj = + Xi’Xj F(Xi = 0, Xj = 1)1)
+ Xi’Xj’ F(Xi = 0, Xj = + Xi’Xj’ F(Xi = 0, Xj = 0)0)
In general, a Boolean function can be expanded In general, a Boolean function can be expanded about any number of input variables.about any number of input variables.
Expansion about k variables will have 2Expansion about k variables will have 2kk terms. terms.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 3737
Binary Decision TreeBinary Decision Tree
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a c
b
f
a
b b
cccc
0 0 1 0 0 1 1 1
0 1
0 0 0
01
11 1
1
1
0
0Graph representation of a Boolean function.
Leaf nodes
Binary Decision DiagramsBinary Decision Diagrams Binary decision diagram (BDD) is a graph representation Binary decision diagram (BDD) is a graph representation
of a Boolean function, directly derivable from Shannon’s of a Boolean function, directly derivable from Shannon’s expansion.expansion.
References:References: C. Y. Lee, “Representation of Switching Circuits by Binary C. Y. Lee, “Representation of Switching Circuits by Binary
Decision Diagrams,” Decision Diagrams,” Bell Syst. Tech JBell Syst. Tech J., vol. 38, pp. 985-999, July ., vol. 38, pp. 985-999, July 1959.1959.
S. Akers, “Binary Decision Diagrams,” S. Akers, “Binary Decision Diagrams,” IEEE Trans. ComputersIEEE Trans. Computers, , vol. C-27, no. 6, pp. 509-516, June 1978.vol. C-27, no. 6, pp. 509-516, June 1978.
Ordered BDD (OBDD) and Reduced Order BDD Ordered BDD (OBDD) and Reduced Order BDD (ROBDD).(ROBDD).
Reference:Reference: R. E. Bryant, “Graph-Based Algorithms for Boolean Function R. E. Bryant, “Graph-Based Algorithms for Boolean Function
Manipulation,” Manipulation,” IEEE Trans. ComputersIEEE Trans. Computers, vol. C-35, no. 8, pp. 677-, vol. C-35, no. 8, pp. 677-691, August 1986.691, August 1986.
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Binary Decision DiagramBinary Decision Diagram BDD of an n-variable Boolean function is a tree:BDD of an n-variable Boolean function is a tree:
Root node is any input variable.Root node is any input variable. All nodes in a level are labeled by the same input All nodes in a level are labeled by the same input
variable.variable. Each node has two outgoing edges, labeled as 0 and Each node has two outgoing edges, labeled as 0 and
1 indicating the state of the node variable.1 indicating the state of the node variable. Leaf nodes carry fixed 0 and 1 labels.Leaf nodes carry fixed 0 and 1 labels. Levels from root to leaf nodes represent an ordering Levels from root to leaf nodes represent an ordering
of input variables.of input variables. If we trace a path from the root to any leaf, the label If we trace a path from the root to any leaf, the label
of the leaf gives the value of the Boolean function of the leaf gives the value of the Boolean function when inputs are assigned the values from the path.when inputs are assigned the values from the path.
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Ordered Binary Decision Diagram Ordered Binary Decision Diagram (OBDD)(OBDD)
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a c
b
f
a
b b
cc
0 1 0 0 1 1
0 1
0 0
01
1 110
a
b bcccc
0 0 1 0 0 1 1 1
0 1
0 0 0
01
11 1
1
1
0
0
TreeOBDD
OBDD OBDD With Different Input OrderingWith Different Input Ordering
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a c
b
f
a
b b
cc
0 1 0 0 1 1
0 1
0 0
01
1 110
c
b b
a
0 1 0 1 1
0 1
0
0
1
1
0 a
01 0 1
Evaluating Function from OBDDEvaluating Function from OBDD
Start at leaf nodes and work toward the root – Start at leaf nodes and work toward the root – leaf node functions are 0 and 1.leaf node functions are 0 and 1.
Function at a node with variable x isFunction at a node with variable x isf = x’.f(low) + x.f(high)f = x’.f(low) + x.f(high)
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4343
x
highlow
0 1
Cannot Compare Two CircuitsCannot Compare Two Circuits
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a c
b
a c b
f f
c
b b
a
0 1 0 1 1
0 1
0
0
1
1
0 a
01 0 1
c
b
a
0 1 0 1
0
1
010
1
OBDD Graph IsomorphismOBDD Graph Isomorphism Two OBDDs are isomorphic if there is one-to-Two OBDDs are isomorphic if there is one-to-
one mapping between the vertex sets with one mapping between the vertex sets with respect to adjacency, labels and leaf values.respect to adjacency, labels and leaf values.
Two isomorphic OBDDs represent the same Two isomorphic OBDDs represent the same function.function.
Two identical circuits may not have identical Two identical circuits may not have identical OBDDs even when same variable ordering is OBDDs even when same variable ordering is used.used.
Comparison is possible if:Comparison is possible if: Same variable ordering is used.Same variable ordering is used. Any redundancies in graphs are removed.Any redundancies in graphs are removed.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4545
Reduced Ordered BDD (ROBDD)Reduced Ordered BDD (ROBDD) Directed acyclic graph (DAG) Directed acyclic graph (DAG) (*)(*).. Contains just two leaf nodes labeled 0 and 1.Contains just two leaf nodes labeled 0 and 1. Variables are indexed, 1, 2, . . . n, such that the Variables are indexed, 1, 2, . . . n, such that the
index of a node is greater than that of its child index of a node is greater than that of its child (*)(*)..
A node has exactly two child nodes, low and A node has exactly two child nodes, low and high such that low high such that low ≠ high.≠ high.
Graph contains no pair of nodes such that Graph contains no pair of nodes such that subgraphs rooted in them are isomorphic.subgraphs rooted in them are isomorphic.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4646
* Properties common to OBDD.
ROBDDsROBDDs
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4747
a c
b
a c b
f f
c
b
a
0 1
01
0
1
1
c
b
a
0 1
01
0
1
10 0
Isomorphic graphs
Reduction: Reduction: OBDD to ROBDDOBDD to ROBDD
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4848
a c
b
f
a
b b
cc
0 1 0 0 1 1
0 1
0 0
01
1 110
a
10
cc
b b
0
00 0
1
1
1 1
1
0
Properties of ROBDDProperties of ROBDD Unique for given variable ordering – graph isomorphism Unique for given variable ordering – graph isomorphism
verifies logic equivalence.verifies logic equivalence. Size (number of nodes) changes with variable ordering – Size (number of nodes) changes with variable ordering –
worst-case size is exponential (e.g., integer multiplier).worst-case size is exponential (e.g., integer multiplier). Other applications: logic synthesis, testing.Other applications: logic synthesis, testing. For algorithms to derive ROBDD, seeFor algorithms to derive ROBDD, see
R. E. Bryant, “Graph-Based Algorithms for Boolean Function R. E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” Manipulation,” IEEE Trans. ComputersIEEE Trans. Computers, vol. C-35, no. 8, pp. 677-, vol. C-35, no. 8, pp. 677-691, August 1986.691, August 1986.
G. De Micheli, G. De Micheli, Synthesis and Optimization of Digital CircuitsSynthesis and Optimization of Digital Circuits, , New York: McGraw-Hill, 1994.New York: McGraw-Hill, 1994.
S. Devadas, A. Ghosh, and K. Keutzer, S. Devadas, A. Ghosh, and K. Keutzer, Logic SynthesisLogic Synthesis, New , New York: McGraw-Hill, 1994.York: McGraw-Hill, 1994.
Spring 2010, Jan 15 . .Spring 2010, Jan 15 . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 4949