EEGN-494 HDL Design Principles for VLSI/FPGAs
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Transcript of EEGN-494 HDL Design Principles for VLSI/FPGAs
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Kazi Fall 2006 EEGN 494 1
EEGN-494
HDL Design Principles for VLSI/FPGAs
Khurram Kazi
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2Kazi Fall 2006 EEGN 494
Fundamental Steps to a Good design
If you have a good start, the project will go smoothly
Partitioning the Design is a good start Partition by:
Functionality Don’t mix two different clock domains in a single block
Don’t make the blocks too large Optimize for Synthesis
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3Kazi Fall 2006 EEGN 494
Partitioning
Partition Design into smaller components:Partition can be done in HDLorDuring Synthesis
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4Kazi Fall 2006 EEGN 494
Recommended rules for Synthesis
When implementing combinatorial paths do not have hierarchy
Register all outputs Do not implement glue logic between block, partition
them well Separate designs on functional boundary Keep block sizes to a reasonable size Separate core logic, pads, clock and JTAG
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5Kazi Fall 2006 EEGN 494
Avoid hierarchical combinatorial blocks
The path between reg1 and reg2 is divided between three different block
Due to hierarchical boundaries, optimization of the combinatorial logic cannot be achieved
Synthesis tools (Synopsys) maintain the integrity of the I/O ports, combinatorial optimization cannot be achieved between blocks (unless “grouping” is used).
Not recommended Design Practice
CombinatorialLogic1
CombinatorialLogic2
CombinatorialLogic3
Block A Block B Block C
reg1 reg2
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6Kazi Fall 2006 EEGN 494
Recommend way to handle Combinatorial Paths
All the combinatorial circuitry is grouped in the same block that has its output connected the destination flip flop
It allows the optimal minimization of the combinatorial logic during synthesis
Allows simplified description of the timing interface
Recommended practice
CombinatorialLogic1 &
Logic2& Logic3
Block A Block C
reg1reg2
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7Kazi Fall 2006 EEGN 494
Register all outputs
Simplifies the synthesis design environment: Inputs to the individual block arrive within the same relative delay (caused by wire delays)
Don’t really need to specify output requirements since paths starts at flip flop outputs.
Take care of fanouts, rule of thumb, keep the fanout to 16 (dependent on technology and components that are being driven by the output)
Register all outputs
Block X Block Y
reg1reg2
Block Y
reg3
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8Kazi Fall 2006 EEGN 494
NO GLUE LOGIC between blocks
No Glue Logic between Blocks, nomatter what the temptation
Block X
reg1
Block Y
reg3
Top
Due to time pressures, and a bug found that can be simply be fixed by adding some simple glue logic. RESIST THE TEMPTATION!!!
At this level in the hierarchy, this implementation will not allow the glue logic to be absorbed within any lower level block.
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9Kazi Fall 2006 EEGN 494
Separate design with different goals
reg1
Slow Logic
Top
Timecritical path
reg3
reg1 may be driven by time critical function, hence will have different optimization constraints
reg3 may be driven by slow logic, hence no need to constrain it for speed
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10Kazi Fall 2006 EEGN 494
Optimization based on design requirements
reg1
Slow Logic
Top
Timecritical path
reg3
Area optimized block
Speed optimized block Use different entities to
partition design blocks Allows different
constraints during synthesis to optimize for area or speed or both.
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11Kazi Fall 2006 EEGN 494
Separate FSM with random logic
Separation of the FSM and the random logic allows you to use FSM optimized synthesis
reg1
RandomLogic
Top
FSM
reg3
Standard optimizationtechniques used
Use FSM optimization tool
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12Kazi Fall 2006 EEGN 494
Maintain a reasonable block size
Partition your design such that each block is between 1000-10000 gates (this is strictly tools and technology dependent)
Larger the blocks, longer the run time -> quick iterations cannot be done.
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13Kazi Fall 2006 EEGN 494
Partitioning of Full ASIC
Top-level block includes I/O pads and the Mid block instantiation
Mid includes Clock generator, JTAG, CORE logic
CORE LOGIC includes all the functionality and internal scan circuitry
Clockgenerator(PLL etc)
JTAG
CORELogic
Mid
Top
I/O Pads
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14Kazi Fall 2006 EEGN 494
Synthesis Constraints
Specifying an Area goal Area constraints are vendor/library dependent
(e.g. 2 input-nand gate, square mils, grid etc) Design compiler has the Max Area constraint
as one of the constraint attributes.
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15Kazi Fall 2006 EEGN 494
Timing constraints for synchronous designs
Define timing paths within the design, i.e. paths leading into the design, internal paths and design leading out of the design Define the clock Define the I/O timing relative to the clock
reg2
Block to be synthesized
reg3A EDCB
clk
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16Kazi Fall 2006 EEGN 494
Define a clock for synthesis
Clock source Period Duty cycle Defining the clock constraints the internal timing
paths
reg2
Block to be synthesized
reg3DCB
clk
Duty cycle
Clock period
QD QD
1 Clock cycle
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17Kazi Fall 2006 EEGN 494
Timing goals for synchronous design
Define timing constraints for all paths within a design Define the clocks Define the I/O timing relative to the clock
reg2
Block to be synthesized
reg3DCB QD QD
Constrained by clk
Paths B and D still unconstraint
A E
clk
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18Kazi Fall 2006 EEGN 494
Constraining input path
Input delay is specified relative to the clock External logic uses some time within the clock period and i.e. TclkToQ(clock to Q delay) + Tw (net delay) ->{At input to B} Example command for this in synopsys design compiler:
Dc_shell> set_input_delay –clock clk 5 (where 5 represents the input delay) (This command is Synopsys centric)
reg2
Block to be synthesized
B QDA
clk
Q W
TclkToQ Tw
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19Kazi Fall 2006 EEGN 494
Constraining output path
Output delay is specified relative to the clock How much of the clock period does the external logic
(shown by cloud b) use up? Tb + Tsetup; The amount to be specified as the output delay
reg2
Block to be synthesized
b QDA
clk
Q
TclkToQ
Tsetup
Tb
External logic
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20Kazi Fall 2006 EEGN 494
Timing paths
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21Kazi Fall 2006 EEGN 494
Combinatorial logic may have multiple paths
•Static Timing Analysis uses the longest path to calculate a maximum delay or the shortest path to calculate a minimum delay.
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22Kazi Fall 2006 EEGN 494
Schematic converted into a timing graph
Each arrow represents a net or a cell delay (timing arc)
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23Kazi Fall 2006 EEGN 494
Calculating a path’s delay1.0
0.50.34
0.25
0.12
Path delay = 1.0 + 0.5 + 0.34 + 0.25 + 0.12 = 2.21
0.0
0.75
0.450.56
0.2
0.1
Path delay = 0.75 + 0.45 + 0.56 +0.1 + 0.2 +0.1 = 2.16 0.1