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Transcript of CAD Flow for FPGAs...
![Page 1: CAD Flow for FPGAs “Introduction”islab.soe.uoguelph.ca/sareibi/PROJECTS_dr/URA_INFO_dr/FPGA-CAD... · FPGA tool flow HDL (VHDL / Verilog) Synthesize Net list Map Place Route Bit](https://reader030.fdocuments.net/reader030/viewer/2022021711/5cc7c5e888c993d63c8bfd1b/html5/thumbnails/1.jpg)
CAD Flow for FPGAs“Introduction”
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What is EDA?o EDA � Electronic Design Automation or (CAD)
o Methodologies, algorithms and tools, which assist and automate the design, verification, and testing of electronic systems.
o A general methodology for refining a high-level description down to a detailed physical implementation for designs ranging from – Integrated circuits (including system-on-chips),
– Field Programmable Gate Arrays,
– Printed circuit boards (PCBs) and
– Electronic systems.
o Why?• Manual design is unrealistic
• Fewer errors
• Time to market.
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Areas & Domain Knowledge in EDA
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FPGA tool flow
HDL(VHDL /Verilog)
Synthesize
Net list
Map
Place
Route
Bit stream
� Hardware design is traditionally done by modeling the system in a hardware description language
� An FPGA “compiler” (synthesis tool) generates a netlist
� which is then mapped to the FPGA technology
� the inferred components are placed on the chip
� and the connecting signals are routedthrough the interconnection network
� A bit stream is finally produced which can be used to program the FPGA.
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Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
EDA (CAD) Flow for FPGAs
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“Synthesis”
Synthesis is the process by which the system specifications and constraints are translated to an implementation (a net list of connected components).o Synthesis is considered to be a key stage in
automated design tools (CAD Tools).o A significant area of research in EDA is in the
development of tools that can synthesize hardwarefrom a design written in the form of high-level programming language such as C.
o It is believed that these ``hardware compilers” will help to decrease development time , thus shortening the crucial time to market for designs.
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Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA or Fabricate IC
Simulation
CAD for IC Design: SynthesisTechnology Independent logic optimization
Technology Dependent Optimization
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Objective Function for Synthesis
• Minimize area– in terms of literal count, cell count, register count, etc.
• Minimize power– in terms of switching activity in individual gates, deactivated circuit
blocks, etc.
• Maximize performance– in terms of maximal clock frequency of synchronous systems,
throughput for asynchronous systems
• Any combination of the above– combined with different weights– formulated as a constraint problem
• “minimize area for a clock speed > 300MHz”
• More global objectives– feedback from layout
• actual physical sizes, delays, placement and routing8
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Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
CAD for FPGAs: Mapping & Covering
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Mapping
Input: A Boolean network Output: A netlist of k-LUTs implementing the Boolean network optimizing some cost function
The mapped netlist
TechnologyMapping
a b c d
f
The subject graphe
a b c d e
f
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Technology Mapping: A Simple Example
FA
A B
Co Ci
S
A Full Adder Implementation:
S = A+B
Logic synthesis tool reduces circuit toSOP form
Co = ABCi + ABCi + ABCi + ABCi
S = ABCi + ABCi + ABCi + ABCi
LUT CoCiBA
LUT SCiBA
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Logic Synthesis in FPGAs
� Logic Optimization
� Technology Mapping
� Definitions
� Technology Mapping� Logic Optimization� Logic Synthesis = Logic Optimization + Tech Mapping
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Mapping and Packingab
cfNetlist of basic gates
Technology Independent logic optimization
Technology map to lookup tables (LUTS)
Pack LUTs into logic blocks
Netlist of logic blocks
LUTLUT
LUT
LUT
CLB
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Objective Function for Mapping
o Minimize area� in terms of number of LUTs
o Minimize power� in terms of switching activity in individual LUTs.
o Maximize performance� in terms of connectivity (depth of LUT implementation)
o Any combination of the above (multi-objective)� combined with different weights
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Mapping: Example
In this example, the circuit in Figure (a) can be implemented by:
� the circuit of three 5-input lookup tablesshown in Figure (b)
� Notice that one of the lookup tables uses only 4 of the available 5 inputs.
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FPGA CAD Flow: Packing
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
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Packing LUTs into CLBs
o Logic block packing groups several LUTs and registers into one logic block.
o This step is necessary whenever the FPGA logic block contains more than a single LUT.
Highly connected LUTs
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Packingo Logic Block packing groups several LUTs and
registers into one Configurable Logic Block (CLB), respecting limitations such as:i. Number of LUTs a CLB may containii. The number of distinct input signals/clocks a CLB
may containo The optimization goals in this phase are to pack
connected LUTs together to Minimize:i. The number of signals to be routed between logic
blocksii. The number of logic blocks used (by filling each
logic block to its capacity)o This problem is a form of clustering .
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Clustering “Packing”
A
C
B
D
net1
net2
before clustering
A
C
B
D
net1
net2
cluster
clustering
A
C
B
Dnet2
cluster
after clustering
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CAD for FPGAs: Place & Route
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
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Problem Formulation
Given : • Set of modules M = { m1, m2, ….mn}• Set of signals S = { s1, s2, ….sq}• Set of location L = { l1, l2, ….lp}, p ≥ |M|
• ∀ mi ∈ M, there is a set of signals • ∀ si ∈ S, there is a set of modules
• is said to be a signal net
SimS ⊆
}|{,jmSisjm
isM
isM ∈=
isM
Goal : To assign each module mi ∈ M to a location lj ∈ L such that the chosen objective function is optimized.
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FPGA Placement Problem
• Input – A technology mapped netlist of Configurable Logic Blocks ( CLB ) realizing a given circuit.
• Output – CLB netlist placed in a two dimensional array of slots such that total wirelength is minimized.
CLB Netlist
i1 i2 i3 i4
f1 f2
1 2 3
4 5 6 7 8
9 10
FPGA
Placement
i1 i2 i3
i4
f2
f1
1
2
3
4
5 6
7
8
9
10
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VLSI Design Flow and Physical Design
Definitions:•Cell: a circuit component to be placed on the chip area. In placement, the functionality of the component is ignored.•Net: specifying a subset of terminals, to connect several cells.•Netlist: a set of nets which contains the connectivity information of the circuit.Global
Placement
Detail Placement
Clock Tree Synthesisand Routing
Global Routing
Detail Routing
Power/Ground Stripes, Rings Routing
Extraction and Delay Calc.
Timing Verification
IO Pad Placement
Placement
Placement is an NP-Complete problem, therefore we seek to simplify the solution to the problem by breaking it down further into smaller problems:• Global Placement• Detailed Placement
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Global and Detailed PlacementGlobal and Detailed Placement
Global Placement
Detailed Placement
In global placement, we decide the approximate locations for cells by placing cells in global bins.
In detailed placement, we make some local adjustment to obtain the final non-overlapping placement.
• Legalization• Local Improvement
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Placement Makes a Difference
MCNC Benchmark circuit e64 (contains 230 4-LUT). Placed to a FPGA.
Random InitialPlacement
GlobalPlacement
After DetailedRouting
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Placement and Routing
o Two critical phases of layout design:�Placement of components on the chip;�Routing of wires between components.
o Placement and routing interact , but separating layout design into phases:�Reduces the complexity of the problem.�Due to interaction solutions obtained are
suboptimal (lose critical information).
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FPGA Compile Time
o Compiling time ≈
(placement time) + (routing time)�Currently, placement and routing time for large
FPGAs can easily take hours or even days to complete.
�These prohibitively long compiling times definitely nullified the time-to-market advantages of FPGAs!!.
o Heuristic methods are used to find sub -optimal solutions in reasonable amount of time.
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Placement: Why Important?
Reasons:
�Serious interconnect issues (delay, routability, noise) in deep-submicron design
�Need placement information even in the early designing stages, e.g., logic synthesis
� Cong et al. [ASPDAC-03, ISPD-03, ICCAD-03] point out that existing placers are far from optimal , not scalable, and not stable
2.0 µ 1.5 µ 1.0 µ 0.8 µ 0.5 µ
0.1
1.0
De
lay (
ns)
Minimum Feature Size
Gate Delay
InterconnectDelay
0.35 µ
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Placement: Objectiveso Placement is the procedure to determine the physical
location of each CLBs and I/O pads on the target FPGA based on some specific objective:1. Wire length, 2. Delay,3. Power,4. Congestion, 5. Routability, ….
o Placement has been proven to be an NP-hard problem(Non-Deterministic Polynomial)� It cannot be solved exactly in linear time (i.e., If there are N
blocks need to be placed, the complexity of the problem will be N!)
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Placement metrics
o Area, delay, congestion and power are determined partly by wiring.
o How do we judge a placement Quality?1. Perform exact wire length measurement.2. Estimate wire length without actually performing
routing.
o Design time may be important for FPGAs� Designers might want to experiment with different
architectures and therefore compile time becomes crucial.
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Total Wire -length
a
b
c
e
d g
f
h
i
j
l
k
c ed
g
f h
il
k
j
a
b
• Wire-length can be measured or estimated using several techniques:• Half Perimeter Wire Length (HPWL) � Good estimate• Steiner Trees (most accurate!)• Spanning Trees (close to Steiner Trees)• Star Model• …..
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Total wirelength with net weights (weighted wirelength)
� For a placement P, an estimate of total weighted wirelength is
where w(net) is the weight of net, and L(net) is the estimated wirelength of net.
� Example:
∑∈
⋅=Pnet
netLnetwPL )()()(
33314472)()()( =⋅+⋅+⋅=⋅= ∑∈Pnet
netLnetwPL
a
b
d
c
f
eb1 e1
c1
a1
d1
d2 f2
f1
Nets WeightsN1 = (a1, b1, d2) w(N1) = 2N2 = (c1, d1, f1) w(N2) = 4N3 = (e1, f2) w(N3) = 1
Total Wire -Length Cost
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Wire length measures
� Estimate wire length by distance between components.
� Possible distance measures:1. Euclidean distance (sqrt(x2 + y2));2. Manhattan distance (x + y).3. HPWL is also a measure .
� Multi-point nets must be broken up into trees for good estimates.
Euclidean
Manhattan
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Wirelength estimation for a given placement
Wire-length Estimation
Half-perimeterwirelength (HPWL)
HPWL = 9
4
5
Complete graph (clique)
8
6
5
33
4
Clique Length =(2/p)Σe ∈ cliquedM(e) = 14.5
Monotone chain
Chain Length = 12
63
3
Star model
Star Length = 15
83
4
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Preferred method : Half-perimeter wirelength (HPWL)• Fast (order of magnitude faster than RSMT)• Equal to length of RSMT for 2- and 3-pin nets• Margin of error for real circuits approx. 8% [Chu, ICCAD 04]
hwL +=HPWL
RSMT Length = 10
31
6
HPWL = 9
4
5
w
h
Wirelength estimation for a given placement (cont‘d .)
HPWL
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Placement Phases
o Construction Phase�Generate a good/feasible initial solution
o Iterative Improvement Phase�Local search techniques are applied to
improve current initial solution
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Placement Techniques
Placement Algorithms
Constructive Placement
Iterative Improvement
Partitioning Placement
NumericalOptimization
ClusterGrowth
Technique
SimulatedAnnealing
Force-directedPlacement
Genetic Placement
Local Search
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Cluster Growth Constructive
Construction Phase
(1,4) (2,4) (3,4)
(0,3)
(0,2)
(0,1)
(1,3) (2,3) (3,3) (4,3)
(1,2) (2,2) (3,2) (4,2)
(1,1) (2,1) (3,1) (4,1)
(1,0) (2,0) (3,0)0 2V
V
V V
V
V1
3
5
4
CLBs array
I/O pads array
0 1 32 4 5 6
1 2 3 4 50
Seed
0512346 V
V V V
V V
V
V
FPGA Chip
Empty BlockCLB
I/O pad
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Heuristic methods for FPGA Placement
o Partitioning-based placement.o Iterative placement.
�Simulated-annealing algorithm.�Simple local search.
Currently, simulated-annealing is one of the dominant methods used by both academia and industry.
VPlace (VPR) is the leading tool for FPGA placement that developed in UNIV. of Toronto.
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Partitioning -based AlgorithmPartitioning -based Algorithm
Partitioning Process
New Cut Existing Cut
New Cut
New Cuts
Existing CutsExisting
Cuts
New Cuts
The smallest partition part containing only one block
Start with a random placement of modules on the FPGA
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Iterative improvement
o Start from a feasible (legal) solution.� Random start� Constructive based
o Seek improvements by making small perturbations.�Create a neighboring solution (candidate
solution).�Select (randomly) two blocks, then swap their
locations.
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Create a neighboring solution:
3
6
2
1
0
4
5
7
V
2
1
4
V
V
6
3
9 7
0 5 8
3
6
2
1
0
4
7
5
V
2
1
4
V
V
6
3
9 7
0 5 8
Accept this swap
Don’t Accept this
swap
Swap between two CLBs
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Create a neighboring solution:
3
6
2
1
0
4
5
7
V
2
1
4
V
V
6
3
9 7
0 5 8
3
6
2
1
0
4
5
7
V
2
1
4
5
V
6
3
9 7
0 V 8
Accept this swap
Swap between two I/O pads
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Iterative Improvement
General method to solve combinatorial optimization problems
Principle:� Start with initial configuration� Repeatedly search neighborhood and select a neighbor as
candidate� Evaluate some cost function (or fitness function) and accept
candidate if "better"; if not, select another neighbor� Stop if:
� quality is sufficiently high, or� no further improvement can be found, or � after some fixed time or iterations
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Iterative Improvement
Simple Iterative Improvement or Hill Climbing :o Candidate is always and only accepted if cost is lower
(or fitness is higher) than current configurationo Stop when no neighbor with lower cost (higher fitness)
can be found
Disadvantages:o Local optimum as best resulto Local optimum depends on initial configurationo Generally no upper bound on iteration length
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Criteria of accepting swaps
o Improving swaps are always accepted.o Non-improving swaps:
�Simple local search:� Do Not Accept!
�Meta-Heuristic (Simulated-annealing: Accept)� Based on a controlled probability. ( e-∆C/T)
� In the initial start phase accept with high probability and as we proceed accept bad moves with low probability
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Simulated Annealing Placement
�An Initial Placement is Improved through Swaps and Moves
�Always accept a Swap/Move if it improves (reduces) cost
�Conditionally accept a Swap/Move that degrades cost under some probability conditions
Time
Cost
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Simulated Annealing
o Motivated by the Physical Annealing Process
� Material is heated and slowly cooled down, so that all particles arrange in the ground energy state into a uniform structure (i.e., create perfec t crystals).
� At each temperature wait until the solid reaches its thermal equilibrium.
o Simulated annealing mimics this process
o The first SA algorithm was developed in 1953.
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Simulated Annealing
o Compared to hill climbing the main difference is that SA allows upwards moves
o In Simulated Annealing:
� Good moves are always accepted .
� Bad moves accepted with probability
o Simulated annealing also differs from hill climbing in that a move is selected at random and then decides whether to accept it
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To accept or not to accept?
P = exp(- ∆ cost /T ) > r
Where:� P: Probability of accepting a move� ∆ cost : change in the evaluation function� T: the current temperature� r is a random number between 0 and 1
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When to Accept?
∆ cost Temp exp(-C/T) ∆ cost Temp exp(-C/T) 0.2 0.95 0.810157735 0.2 0.1 0.1353352830.4 0.95 0.656355555 0.4 0.1 0.0183156390.6 0.95 0.53175153 0.6 0.1 0.0024787520.8 0.95 0.430802615 0.8 0.1 0.000335463
P = exp(- ∆ cost /T) > r
o When the temperature is high (at the start of the s earch) the value ofP = exp(- ∆ cost /T) is high and in most cases will be higher than the random number generated “r”.
o However, as we decrease the temperature (at the end of the search T is getting smaller) the value of P = exp(- ∆ cost /T) is low and P is not going to be greater than the random number generated “r”.
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Simulated Annealing
Step 1: Initialize – Start with a random initial placement. Initialize T to a very high value or “temperature”.
Step 2: Move – Perturb the placement through a defined move.
Step 3: Calculate score – calculate the change in the score due to the move made.
Step 4: Choose – Depending on the change in score, accept or reject the move. The prob of acceptance depending on the current “temperature”.
Step 5: Update and repeat – Update the temperature value by lowering the temperature. Go back to Step 2.
The process is done until “Freezing Point” is reached.
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Simulated Annealing
� Initialize temperature T initial =(High Value), T final, = (Low Value)� Create an initial random solution S = Random Placem ent� While (T initial > Tfinal )
{Repeat step 1, 2 and 3 a fixed number of times:
1. Generate a new solution S’2. If cost(S’) < cost (S),
accept S’, i.e., S ⇐ S’3. Else
if random() < e -k∆cost/T
accept S’else
reject S’Decrease T
}report (best solution)
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Simulated Annealing
State
CostTemperature
droppingDrop back
TemperatureHigh
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Pros and Cons of SA
o Pros:�Can Reach Globally Optimal Solution (given “enough” time)�Open Cost Function.�Can Optimize Simultaneously all Aspects of Physical Design�Can be Used for End Case Placement
o Cons:�Extremely Slow Process of Reaching a Good Solution�We may revisit solutions visited before (unproductive)
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Analytic Placement• Also referred to as force-directed or quadratic
placement
• Analytic Placement minimizes a given objective, such as wire-length or circuit delay, using mathematical techniques such as numerical analysis or linear programming.
• Such methods often require certain assumption such as the differentiability of the obj Function.
• Algorithm: Solve a set of linear equations to find an intermediate solution
Repeat the process until equilibrium
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Quadratic Placement• Write down the placement problem as an analytical mathematical problem• Suppose that all nets in the circuit are 2-pin nets
– Consider a net {i,j}, the wire-length is given by Manhattan distance:– L {i,j} = |xi – xj| + |yi – yj|
• This is usually referred to as a linear wire-length (non-differentiable)!!!.• Solution?• A common idea is to consider the squared Euclidean distance between
modules instead: – L~
{i,j} = (xi – xj)2 + (yi – yj)2
– So the wire-length minimization problem can be formulated as a quadratic program.
– It can be proved that the quadratic program is convex, hence polynomial time solvable
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• Objective function is quadratic; sum of (weighted) squared Euclidean distancerepresents placement objective function
where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
• Only two-point-connections
• Minimize objective function by equating its derivative to zero which reduces to solving a system of linear equations
• Similar to Least-Mean-Square Method (root mean Square)
( ) ( )( )∑=
−+−=n
jijijiij yyxxcPL
1,
22
2
1)(
Quadratic Placement
NOTE: In quadratic placement techniques, it is more convenient to set the cost function L(P) to half of the total weighted quadratic wirelength so that the derivatives will have simpler forms
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where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
• Each dimension can be considered independently:
• Convex quadratic optimization problem: any local minimum solution is also a global minimum
• Optimal x- and y-coordinates can be found by setting the partial derivatives of Lx(P) and Ly(P) to zero
( ) ( )( )∑=
−+−=n
jijijiij yyxxcPL
1,
22
2
1)(
2
1,1
)(),()( ji
n
jix xxjicPL −= ∑
==
2
1,1
)(),()( ji
n
jiy yyjicPL −= ∑
==
Quadratic Placement
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where n is the total number of cells, and c(i,j) is the connection cost between cells i and j.
• Each dimension can be considered independently:
• where A is a matrix with A[i][j] = -c(i,j) when i ≠ j, and A[i][i] = the sum of incident connection weights of cell i.
• X is a vector of all the x-coordinates of the non-fixed cells, and bx is a vector with bx[i] = the sum of x-coordinates of all fixed cells attached to i.
• Y is a vector of all the y-coordinates of the non-fixed cells, and by is a vector with by[i] = the sum of y-coordinates of all fixed cells attached to i.
( ) ( )( )∑=
−+−=n
jijijiij yyxxcPL
1,
22
2
1)(
2
1,1
)(),()( ji
n
jix xxjicPL −= ∑
==
2
1,1
)(),()( ji
n
jiy yyjicPL −= ∑
==
0)( =−=
∂∂
xx bAXX
PL0
)(=−=
∂∂
yy bAYY
PL
Quadratic Placement
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x2x1
x=100 x=200ToyExample:
Cost= (x1 −100)2 + (x1 −x2)2 +(x2 −200)2
setting the partial derivatives = 0 we solve for the minimum Cost:
Ax + B = 0
= 04 −2−2 4
x1
x2+ −200
−400
= 02 −1−1 2
x1
x2+ −100
−200
x1=400/3 x2=500/3
x2Cost=− 2(x1 −x2) +2(x2 −200)∂
∂
x1Cost=2(x1 −100) +2(x1 −x2)∂
∂where A is a matrix with A[i][j] = -c(i,j) when i ≠ j, and A[i][i] = the sum of incident connection weights of cell i.
X is a vector of all the x-coordinates of the non-fixed cells, and bx is a vector with bx[i] = the sum of x-coordinates of all fixed cells attached to i.
Y is a vector of all the y-coordinates of the non-fixed cells, and by is a vector with by[i] = the sum of y-coordinates of all fixed cells attached to i.
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setting the partial derivatives = 0 we solve for the minimum Cost:
Ax + B = 0
= 04 −2
−2 4x1x2
+ −200−400
= 02 −1
−1 2x1x2
+ −100−200
x1=400/3 x2=500/3
x2x1
x=100 x=200
Interpretation of matrices A and B:
The diagonal values A[i,i] correspond to the number of connections to xiThe off diagonal values A[i,j] are -1 if object i is connected to object j, 0 otherwiseThe values B[i] correspond to the sum of the locations of fixed objects connected to object i
Example:
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p1
p2
a b c
Example II:Given:1.Placement P with two fixed points P1 (100,175) and P2 (200,225)2.Three free blocks a,b,c3.Four nets N1 – N4
N1 (P1, a), N2 (a,b), N3 (b,c) and N4 (c,P2)
Task : find the coordinates of blocks (xa,ya), (xb,yb) and (xc,yc)
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P1
P2
bac
Solution of Example II:First1.Solve for x-coordinates2.Lx(P) = (100 – xa)2 + (xa – xb)2 + (xb – xc)2 + (xc – 200)2
0)( =
∂∂
Xa
PLx 0)( =
∂∂
Xb
PLx 0)( =
∂∂
Xc
PLxxbAX =
Solve for X: xa = 125, xb = 150, xc = 175
Then:1.Solve for y-coordinates2.Ly(P) = (175 – ya)2 + (ya – yb)2 + (yb – yc)2 + (yc – 225)2
0)(
=∂
∂Ya
PLy
0)(
=∂
∂Yb
PLy
0)(
=∂
∂Yc
PLy
ybAY =
Solve for Y: ya = 187.5, yb = 200, yc = 212.5Final Solution: a(125,187.5), b(150,200) and c(175,212.5)
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Solution of the Original QP
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• Second stage of quadratic placers: cells are spread out to remove overlaps
• Methods:
− Adding fake nets that pull cells away from dense regions toward anchors
− Geometric sorting and scaling
− Repulsion forces, etc.
Quadratic Placement
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Partitioning
• Find a good cut direction and position.
• Improve the cut value using FM.
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• Before every level of partitioning, do the Global Optimization again with additional constraints that the center of gravities should be in the center of regions.
• Always solve a single QP (i.e., global).
Applying the Idea Recursively
Center of Gravities
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Analytic Placement
(a) Global placement with 1 region (b) Global placem ent with 4 region (c) Final placements
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Pros and Cons of AP (QP/FD)
�Pros:Very Fast Analytical Solution
Can Handle Large Design Sizes
Can be Used as an Initial Seed Placement Engine
�Cons:�Can Generate Overlapped Solutions: Postprocessing
Needed
�Might not be suitable for Timing Driven Placement
�Not Suitable for Simultaneous Optimization of Other Aspects of Physical Design (clocks, crosstalk…)
�Gives Trivial Solutions without Pads ..
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Xilinx ISE vs. Xilinx Vivado
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FPGA Physical Design
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
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Global vs. Detailed Routing
� Global routing
LB LB LB
SB SB
LB LB LB
SB SB
LB LB LB
SB
SB
LB LB LB
SB SB
LB LB LB
SB SB
LB LB LB
SB
SB
� Detailed routing
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Routing is Architecture Dependent
� Connection Boxes “C”� Flexibility, FC (# of wires each
logic pin can connect to)� Topology (pattern of switches)
� Switch Boxes “S”� Flexibility, FS� Topology
� Length of wires:� Single Length Lines� Double Length Lines
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FPGA Routing: VPR
VPR – Versatile Place and Route [Betz, et al., 1997]� Uses a Pathfinder algorithm� Increase performance over original Pathfinder algorithm� Routability-driven routing
� Goal: Use fewest tracks possible� Timing-driven routing
� Goal: Optimize circuit speed
Routing Resource GraphResource
Graph
Route
Rip-up
Done!
congestion?illegal?
no
yes
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1
1
1
1
1
1
11
1
FPGA Routing: PathFinder
� Pathfinder [Ebeling , et al., 1995]� Introduced negotiated congestion� During each routing iteration, route
nets using shortest path� Allows overuse (congestion) of routing
resources
� If congestion exists (illegal routing)� Update cost of congested resources
based on the amount of overuse� Rip-up all routes and reroute all nets
2
congestion
2
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FPGA Physical Design
Design Entry
Logic Optimization
Synthesis
Mapping to k-LUT
Packing LUTs to CLBs
Placement
Routing Configure an FPGA
Simulation
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FPGA Configuration� Following all CAD steps the end result is a configuration file which
contains the information that will be uploaded into the FPGA in order to program it to perform a specific function.
� Interfaces available to configure the FPGA?.
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