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EE141EE141--Fall 2006Fall 2006Digital Integrated Digital Integrated CircuitsCircuits

Lecture 13Lecture 13CMOS logicCMOS logicDesign for speedDesign for speed

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AnnouncementsAnnouncementsHardware lab this week

Lab 4 due this weekHomework #6 due next Tuesday

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Class MaterialClass Material

Last lectureCMOS logic gates

Today’s lectureDesign for speed

Reading (Chapter 6)

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Static CMOS Static CMOS DesignDesign

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Switch Delay ModelSwitch Delay Model

A

Req

A

Rp

A

Rp

A

Rn CL

A

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

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Input Pattern Effects on DelayInput Pattern Effects on DelayDelay is dependent on the pattern of inputsLow to high transition

both inputs go low– delay is 0.69 Rp/2 CL

one input goes low– delay is 0.69 Rp CL

High to low transitionboth inputs go high

– delay is 0.69 2Rn CL

CL

B

Rn

ARp

BRp

A

Rn Cint

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Delay Dependence on Input PatternsDelay Dependence on Input Patterns

-0.5

0

0.5

1

1.5

2

2.5

3

0 100 200 300 400

A=B=1→0

A=1, B=1→0

A=1 →0, B=1

time [ps]

Vol

tage

[V]

81A= 1→0, B=1

80A=1, B=1→0

45A=B=1→0

61A= 0→1, B=1

64A=1, B=0→1

67A=B=0→1

Delay(psec)

Input DataPattern

NMOS = 0.5μm/0.25 μmPMOS = 0.75μm/0.25 μmCL = 100 fF

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Transistor SizingTransistor Sizing

CL

B

Rn

A

Rp

B

Rp

A

Rn Cint

B

Rp

A

Rp

A

Rn

B

Rn CL

Cint

2

2

2 2

11

4

4

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Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate

OUT = D + A • (B + C)

DA

B C

D

AB

C

1

2

2 2

4

48

8

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Transistor Sizing a Complex Transistor Sizing a Complex CMOS GateCMOS Gate

OUT = D + A • (B + C)

DA

B C

D

AB

C

1

2

2 2

6

36

6

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FanFan--In ConsiderationsIn Considerations

DCBA

D

C

B

A CL

C3

C2

C1

Distributed RC model(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.

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ttpp as a Function of Fanas a Function of Fan--InIn

tpLH

t p(p

sec)

fan-in

Gates with a fan-in greater than 4 should be avoided.

0

250

500

750

1000

1250

2 4 6 8 10 12 14 16

tpHL

quadratic

linear

tp

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ttpp as a Function of Fanas a Function of Fan--OutOut

2 4 6 8 10 12 14 16

tpNOR2

t p(p

sec)

eff. fan-out = CL/Cin

All gates have the same drive current.

tpNAND2

tpINV

Slope is a function of “driving strength”

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ttpp as a Function of Fanas a Function of Fan--In and FanIn and Fan--OutOut

Fan-in: quadratic due to increasing resistance and capacitanceFan-out: each additional fan-out gate adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

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Fast Complex Gates:Fast Complex Gates:Design Technique 1Design Technique 1

Transistor sizingas long as fan-out capacitance dominates

Progressive sizing

InN CL

C3

C2

C1In1

In2

In3

M1

M2

M3

MNDistributed RC line

M1 > M2 > M3 > … > MN(the FET closest to theoutput is the smallest)

Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinks

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Fast Complex Gates:Fast Complex Gates:Design Technique 2Design Technique 2

Transistor ordering

C2

C1In1

In2

In3

M1

M2

M3 CL

C2

C1In3

In2

In1

M1

M2

M3 CL

critical path critical path

charged1

0→1charged

charged1

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

1

1

0→1 charged

discharged

discharged

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Fast Complex Gates:Fast Complex Gates:Design Technique 3Design Technique 3Alternate logic structures

F = ABCDEFGH

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Fast Complex Gates:Fast Complex Gates:Design Technique 4Design Technique 4

Isolating fan-in from fan-out using buffer insertion

CLCL

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Fast Complex Gates:Fast Complex Gates:Design Technique 5Design Technique 5

Reducing the voltage swing

linear reduction in delayalso reduces power consumption

But the following gate is much slower!Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design)

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

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Logical Logical EffortEffort

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Buffer ExampleBuffer Example

( )∑=

+=N

iifDelay

11

For given N: Ci+1/Ci = Ci/Ci-1To find N: Ci+1/Ci ~ 4How to generalize this to any logic path?

CL = CN+1

In Out

1 2 N

(in units of τinv)

fi = Ci+1/Ci

C1 C2 CN

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Logical EffortLogical Effort

( )fgpCCCRkDelay

in

Lunitunit

⋅+=

⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅=

τγ

1

p – intrinsic delay (3kRunitCunitγ) - gate parameter ≠ f(W)g – logical effort (kRunitCunit) – gate parameter ≠ f(W)f – electrical effort (effective fanout)

Normalize everything to an inverter:ginv =1, pinv = 1

Divide everything by τinv(everything is measured in unit delays τinv)Assume γ = 1.

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Delay in a Logic GateDelay in a Logic Gate

Gate delay:

d = h + p

effort delay intrinsic delay

Effort delay:

h = g f

logical effort effective fanout = Cout/Cin

Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size

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Logical EffortLogical EffortInverter has the smallest logical effort and intrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same currentLogical effort increases with the gate complexity

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Logical EffortLogical EffortLogical effort is the ratio of input capacitance of a gate (input) to the input capacitance of an inverter with the same output current

g = 1 g = 4/3 g = 5/3

B

A

A B

F

VDDVDD

A B

A

B

F

VDD

A

A

F

1

2 2 2

2

21 1

4

4

Inverter 2-input NAND 2-input NOR

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Logical Effort of GatesLogical Effort of Gates

Fan-out (f)

Nor

mal

ized

del

ay (d

)

t

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g=p=d=

g=p=d=

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Logical Effort of GatesLogical Effort of Gates

Fan-out (f)

Nor

mal

ized

del

ay (d

)t

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

g=1p=1d=h+1

g=4/3p=2d=(4/3)h+2

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Logical Effort of GatesLogical Effort of Gates

�IntrinsicDelay

EffortDelay

1 2 3 4 5Fanout f

1

2

3

4

5

Inverter:

g = 1; p = 1

2-inp

ut NAND: g

= 4/3;

p = 2

Nor

mal

ized

Del

ay

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Add Branching EffortAdd Branching Effort

Branching effort:

pathon

pathoffpathon

CCC

b−

−− +=

Coff-path

Con-path

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Multistage NetworksMultistage Networks

Stage effort: hi = gifiPath electrical effort: F = Cout/Cin

Path logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

Path effort: H = GFB

Path delay D = Σdi = Σpi + Σhi

( )∑=

⋅+=N

iiii fgpDelay

1

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Optimum Effort per StageOptimum Effort per Stage

HhN =

When each stage bears the same effort:

N Hh =

( ) PNHpfgD Niii +=+= ∑ /1ˆ

Minimum path delay

Effective fanout of each stage: ii ghf =

Stage efforts: g1f1 = g2f2 = … = gNfN

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Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing

∑+= iN pNHD /1

NHh ˆ/1=The ‘best stage effort’

Remember: we can always add inverters to the end of the chain

is around 4 (3.6 with γ=1)

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Logical EffortLogical Effort

From Sutherland, Sproull

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Example: Optimize PathExample: Optimize Path

Effective fanout, F =G = H =h =a =b =

1a

b c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

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Example: Optimize PathExample: Optimize Path1

ab c

5

g = 1f = a

g = 5/3f = b/a

g = 5/3f = c/b

g = 1f = 5/c

Effective fanout, F = 5G = 25/9H = 125/9 = 13.9h = 1.93a = 1.93b = ha/g2 = 2.23c = hb/g3 = 5g4/f = 2.59

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Example Example –– 88--Input ANDInput AND

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Method of Logical EffortMethod of Logical EffortCompute the path effort: H = GBFFind the best number of stages N ~ log4HCompute the stage effort h = H1/N

Sketch the path with this number of stagesWork either from either end, find sizes: Cin = Cout*g/h

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.