EE141-Fall 2007 Digital Integrated...

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EECS141 1Lecture #1

EE141EE141--Fall 2007Fall 2007Digital Integrated Digital Integrated CircuitsCircuits

TuThTuTh 3:303:30--5pm5pm155 Donner155 Donner

Instructor: Elad Alon

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EECS141 2Lecture #1

What is this class all about?What is this class all about?Introduction to digital integrated circuit design engineering

Will describe models and key concepts needed to be a good digital IC designer

Models allow us to reason about circuit behaviorAllow analysis and optimization of the circuit’s performance, power, cost, etc.Understanding circuit behavior is key to making sure it will actually work

Teach you how to make sure your circuit worksDo you want your transistor to be the one that screws up a 1 billion transistor chip?

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EECS141 3Lecture #1

Detailed TopicsDetailed TopicsCMOS devices and manufacturing technologyCMOS inverters and gatesPropagation delay, noise margins, powerCombinational and sequential circuits Timing and clocking Arithmetic building blocksInterconnectMemoriesDesign methodologies

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EECS141 4Lecture #1

What will you learn?What will you learn?Understanding, designing, and optimizing digital circuits for various quality metrics:

Performance (speed)

Power dissipation

Cost

Reliability

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EECS141 5Lecture #1

Practical InformationPractical InformationInstructor

Prof. Elad Alon565 Cory Hall, 642-0237, elad@eecsOffice hours: TuTh 11am-12pm

TAs:Eric Chin, eychin@eecs (OH: Wed. 4-5pm)Kenny Duong, keduong@berkeley (OH: Wed. 3-4pm)Adam Abed aabed@berkeley (OH: Tues. 2-3pm)Kevin Chao kchao21@berkeley (OH: Tues. 2-3pm)

Web page: http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f07/

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EECS141 6Lecture #1

Discussions and LabsDiscussions and LabsDiscussion sessions

F 2-3pm, Kenny M 5-6pm, EricF 9-10am, AdamSame material in all sessions!

Labs (353 Cory)M 10am-1pmW 12-3pmF 3-6pmTu 12-3pm (most likely will be cancelled)

Please choose one lab session and stick with it!

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EECS141 7Lecture #1

Lab(Kenny)353 Cory

M

T

W

R

F

8 9 10 11 12 1 2 3 4 5 6

Lab(Eric)

353 Cory

Lab(Kevin)353 Cory

DISC*(Kenny)

293 Cory

DISC*(Adam)293 Cory

Lec(Elad)

155 Donner

ProblemSets Due

Lec(Elad)

155 Donner

* Discussion sections will cover identical material

OH(Elad)565 Cory

Your EECS141 WeekYour EECS141 WeekDISC*(Eric)

293 Cory

OH(Elad)565 Cory

Lab(TBD)353 Cory

OH(Eric)

TBD Cory

OH(Kenny)TBD Cory

OH(Adam,Kevin)

TBD Cory

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EECS141 8Lecture #1

Class OrganizationClass Organization

10 AssignmentsOne design project (with a few phases)Labs: 5 software, 1 hardware2 midterms, 1 final

Midterm 1: Thurs., October 4, evening (TBD)Midterm 2: Thurs., November 1, evening (TBD)Final: Thurs., December 20, 12:30-3:30pm (TBD)

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EECS141 9Lecture #1

Some Important AnnouncementsSome Important AnnouncementsPlease use the newsgroup for asking questions (ucb.class.ee141)Can work together on homework

But you must turn in your own solutionPlease don’t bring food/drinks to 353 CoryLab reports due 1 week after the lab sessionProject is done in pairsNo late assignments

Solutions available shortly after due date/timeDon’t even think about cheating!

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EECS141 10Lecture #1

Grading PolicyGrading Policy

Homeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%

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Class MaterialClass MaterialTextbook: “Digital Integrated Circuits – A Design Perspective”, 2nd ed, by J. Rabaey, A. Chandrakasan, B. NikolicClass notes: Web pageLab Reader: Web pageCheck web page for the availability of tools

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The Web SiteThe Web SiteThe sole source of information

http://bwrc.eecs.berkeley.edu/icdesign/eecs141_f07

Class and lecture notesAssignments and solutionsLab and project informationExamsMany other goodies …

Print only what you need: Save a tree!

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SoftwareSoftware

CadenceWidely used in industryOnline tutorials and documentation

HSPICE for simulation

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Getting StartedGetting Started

Assignment 1: Getting SPICE to work –see web-pageDue next Thursday, September 6, 5pmNO discussion sessions or labs this week.First discussion sessions in Week 2First software lab in Week 3

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IntroductionIntroduction

Why is designing digital ICs different today than it was before?

Will it change in future?

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The First ComputerThe First Computer

The Babbage Difference Engine

25,000 partscost: £17,470

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ENIAC ENIAC -- The First Electronic Computer (1946)The First Electronic Computer (1946)

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The Transistor RevolutionThe Transistor Revolution

First transistorBell Labs, 1948

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The First Integrated Circuits The First Integrated Circuits

Bipolar logic1960’s

ECL 3-input GateMotorola 1966

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Intel 4004 MicroprocessorIntel 4004 Microprocessor

Intel, 1971.2,300 transistors (12mm2)740 KHz operation (10µm PMOS technology)

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Intel Pentium 4 MicroprocessorIntel Pentium 4 Microprocessor

Intel, 2005.125,000,000 transistors (112mm2)3.8 GHz operation (90nm CMOS technology)

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Intel Core 2 MicroprocessorIntel Core 2 Microprocessor

Intel, 2006.291,000,000 transistors (143mm2)3 GHz operation (65nm CMOS technology)

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MooreMoore’’s Laws Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that semiconductor technology will double its effectiveness every 18 months

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MooreMoore’’s Laws Law16151413121110

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LOG

2 OF

THE

NU

MB

ER O

FC

OM

PON

ENTS

PER

INTE

GR

ATE

D F

UN

CTI

ON

Electronics, April 19, 1965.

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Evolution in ComplexityEvolution in Complexity

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Transistor CountsTransistor Counts

Doubles every 2 years

Transistor Counts in Intel's Microprocessors

0.001

0.01

0.1

1

10

100

1000

1970 1975 1980 1985 1990 1995 2000 2005

Tran

sist

ors

[in m

illio

ns]

4004

80088080

80868088

80286 386DX

486DX486DX4

PentiumPentium Pro

Pentium II

Pentium MMX

Pentium III

Pentium 4

Itanium

Itanium II

Core2

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FrequencyFrequency

Has been doublingevery 2 years, but is now slowing down

Frequency Trends in Intel's Microprocessors

0.1

1

10

100

1000

10000

1970 1975 1980 1985 1990 1995 2000 2005

Freq

uenc

y [M

Hz]

40048008

8080

8086

8088

80286386DX

486DX 486DX4

PentiumPentium Pro

Pentium II

Pentium MMX

Pentium III

Pentium 4

ItaniumItanium II

Core2

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Power Dissipation Prediction (2000)Power Dissipation Prediction (2000)5KW

18KW

1.5KW 500W

400480088080

80858086

286386

486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Pow

er (W

atts

)

Courtesy, Intel

Did this really happen?

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Power Dissipation DataPower Dissipation Data

Has been > doublingevery 2 years

Has to stay ~constant

Power Trends in Intel's Microprocessors

0.1

1

10

100

1000

1970 1975 1980 1985 1990 1995 2000 2005

Pow

er [W

]

4004

8008 8080

8086

8088

80286

386DX

486DX

Pentium

Pentium Pro

Pentium II

Pentium IIIPentium 4

ItaniumItanium II Core 2

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Cause: Power DensityCause: Power Density

400480088080

8085

8086

286 386 486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (W

/cm

2)

Hot Plate

Nuclear Reactor

Rocket Nozzle

S. Borkar

Sun’s Surface

Power density too high for cost-effective coolingPower density too high for cost-effective cooling

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Not Only MicroprocessorsNot Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)(data from Texas Instruments)

CellPhone

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Productivity TrendsProductivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000Logic Tr./ChipTr./Staff Month.

xxx

xxx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

Chi

p(M

)

0.01

0.1

1

10

100

1,000

10,000

100,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo.

Source: Sematech

Complexity outpaces design productivity

Com

plex

ity

Courtesy, ITRS Roadmap

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Challenges in Digital DesignChallenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Complexity• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

∝ DSM ∝ 1/DSM

?

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Why Scaling?Why Scaling?Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xBut …

How to design chips with more and more functions?Design engineering population does not double every two years…

Hence, a need for more efficient design methodsExploit different levels of abstraction

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Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

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Next LectureNext Lecture

Introduce basic metrics for design of integrated circuits – how to measure delay, power, cost, etc.

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