ECE680: Physical VLSI Design - George Mason Universityece.gmu.edu/~qli/ECE680/chapter8 Memory...

ECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI Design

Chapter VIIIChapter VIII

Semiconductor MemorySemiconductor Memory

(chapter 12 in textbook)(chapter 12 in textbook)

GMU, ECE 680 Physical VLSI Design 1

Chapter Overview

Memory ClassificationMemory ClassificationMemory Architectures The Memory Core Periphery Periphery Reliability Case Studies

2GMU, ECE 680 Physical VLSI Design

Semiconductor Memory Classificationy

Read-Write MemoryNon-VolatileRead-Write

MemoryRead-Only Memory

EPROM

E2PROM

RandomAccess

Non-RandomAccess Mask-Programmed

Programmable (PROM)

FLASHSRAM

DRAM

Programmable (PROM)

FIFO

LIFODRAMShift Register

CAM


Memory Timing: Definitionsy g

Read cycle

Write cycle

y

READ

Write cycleRead access Read access

WRITE

Write accessData valid

DATA

Data written

DATA


Memory Architecture: DecodersM bits M bits

S0 S0Word 0

Word 1

Word 2 Storagecell

S0

S1

S2A0

A1

Word 0

Word 1

Word 2 Storagecell

0

Word N2 2Nwords

SN2 2AK2 1

SWord N2 2

Decoder

Word N2 1K 5 log2N

SN2 1 Word N2 1

Input-Output(M bits)

Intuitive architecture for N x M memoryToo many select signals: K l N

Decoder reduces the number of select signals

Input-Output(M bits)

Too many select signals:N words == N select signals K = log2N


Array‐Structured Memory Architecture

Bit line2L 2 KStorage cell

Problem: ASPECT RATIO or HEIGHT >> WIDTH

Dec

oder

Word line

AK

AK1 1R

owAL 2 1

M.2K

A0

M.2

Sense amplifiers / Drivers Amplify swing torail-to-rail amplitude

0

AK2 1Column decoder

Input-Output

Selects appropriateword

p p(M bits)


Hierarchical Memory ArchitectureBlock 0

Rowdd

Block i Block P 2 1

address

Columnaddress

Blockaddress

Globalamplifier/driver

Controlcircuitry

Global data busBlock selector

Advantages:Advantages:1 Sh t i ithi bl k1 Sh t i ithi bl k

I/O

1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savings


Block Diagram of 4 Mbit SRAMClock

generatorZ ‐addressbuffer

X ‐addressbuffer

Subglobal row decoderBlock 30 128 K Array Block 0

Predecoder and block selectorBit line load

Subglobal row decoder

Global row d d

Subglobal row decoderBlock 31 Block 1

decoder

Transfer gateColumn decoder

Sense amplifier and write driver Local ro decoder

CS, WEbuffer

I/Obuffer

Y ‐addressbuffer

X ‐addressbuffer

x1/x4controller

Sense amplifier and write driver Local row decoder

[Hirose90] 8GMU, ECE 680 Physical VLSI Design

Contents‐Addressable Memory

Data (64 bits)

Buf

fers

I/O B

Comparandman

ds

der

Comparand

MaskCom

ts er

ddre

ss D

ecod

CAM Array29 words 3 64 bitsControl Logic R/W Address (9 bits)

29 Val

idity

Bit

riorit

y E

ncod

Ad 2 P


Memory Timing: ApproachesMemory Timing: Approaches

Addressbus

RAS

Row Address

Address

Column Address

RAS AddressBus

Address transitioninitiates memory operation

Address

CAS

DRAM Timing SRAM Ti i

RAS-CAS timing

DRAM TimingMultiplexed Adressing

SRAM TimingSelf‐timed


Read‐Only Memory Cellsy y

BL BLBLV

WLWL

1WL

VDD

BL BL BL

WL WL

0WL

GND

Diode ROM MOS ROM 1 MOS ROM 2


MOS OR ROMBL [0] BL [1] BL [2] BL [3]

WL [0]

VDD

WL [1]WL [1]

WL [2]

WL [3]

VDD

V bias

Pull‐down loads


MOS NOR ROMVDD

Pull up devices

WL [0]

Pull‐up devices

GND

WL [1]

WL [2]

GND

BL [0]

WL [3]

BL [1] BL [2] BL [3]BL [0] BL [1] BL [2] BL [3]


MOS NOR ROM LayoutCell (9.5 x 7)

Programmming using theActive Layer Onlyy y

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion


MOS NOR ROM LayoutCell (11 x 7)

Programmming usingthe Contact Layer Onlyy y

Polysilicon

Metal1

Diffusion

Metal1 on Diffusion


MOS NAND ROMVDD

Pull‐up devices

WL [0]

p

BL [3]BL [2]BL [1]BL [0]

[ ]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row


MOS NAND ROM LayoutCell (8 x 7)

P i iProgrammming usingthe Metal-1 Layer Only

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion


NAND ROM LayoutCell (5 x 6)

P i iProgrammming usingImplants Only

Polysilicon

Threshold‐alteringimplant

Metal1 on DiffusionMetal1 on Diffusion


Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM VDD

C bit

rwordWL

BL

C bit

cword

• Word line parasitics– Wire capacitance and gate capacitance

Wire resistance (polysilicon)– Wire resistance (polysilicon)• Bit line parasitics

– Resistance not dominant (metal)Drain and Gate Drain capacitance

Page 642

– Drain and Gate‐Drain capacitance

Equivalent Transient Model for MOS NAND ROM

Model for NAND ROMVDD

C Lrbit

BL

rword

cword

cbitWL

Word line parasitics Similar to NOR ROM

Bit line parasitics Bit line parasitics Resistance of cascaded transistors dominates Drain/Source and complete gate capacitance


Decreasing Word Line Delay

Polysilicon word lineWLDriver

Metal word line

Metal bypass

(a) Driving the word line from both sides

Polysilicon word lineK cellsWL

(b) Using a metal bypass

(c) Use silicides( )


Precharged MOS NOR ROMVDD

Precharge devices

pref

WL [0]

GND

WL [1]WL [1]

WL [2]

WL [3]

GND

PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design

BL [0] BL [1] BL [2] BL [3]

but clock driver becomes harder to design.


Non‐Volatile Memoriesh l ( )The Floating‐gate transistor (FAMOS)

Floating gate

Source

Gate

DrainD

Source Drain

tox

tox

G

Substraten+ n+_p

oxS

Device cross‐section Schematic symbol


Floating‐Gate Transistor Programming

0 V 5 V20 V 0 V

2 5 V 0 V

5 V

2 2.5 V 5 V

20 V

10 V 5 V 20 V

DS DSDS

Removing programming voltage leaves charge trapped

Programming results inhigher V T .

Avalanche injection


A “Programmable‐Threshold” Transistor

“ 0” t t “ 1” t tI “ 0” -state “ 1” -state

“ ON ”

ID

DVT

O

VWL VGS

“ OFF”


FLOTOX EEPROMFLOTOX EEPROM

Floating gate

Source

Gate

Drain

20 30 10 V

I

V

Substraten1 n1

20–30 nm ‐10 V

10 V

V GD

Substratep

Fowler‐Nordheim

10 nm

FLOTOX transistorFowler‐NordheimI‐V characteristic


EEPROM CellBL

WL

VDD

Absolute threshold controlis hardUnprogrammed transistor might be depletionVDD might be depletion 2 transistor cell


Flash EEPROMFlash EEPROM

Control gate

Floating gate

erasure

g g

Thin tunneling oxide

1 1 d i

p-substrate

n 1 source n1 drainprogramming

Many other options …


Cross‐sections of NVM cells

EPROMFlashCourtesy Intel 29GMU, ECE 680 Physical VLSI Design

Basic Operations in a NOR Flash Memory―p yErase

G

cell arrayBL 0 BL 1

S D

12 VG

WL 00 V

S D

WL 10 V

12 V

open open

1

p p


Basic Operations in a NOR Flash Memory―p yWrite

BL BL12 V

6 VG

BL 0 BL 1

S D

WL 012 V

0 V

WL 10 V

6 V 0 V


Basic Operations in a NOR Flash Memory―p yRead

BL BL5 V

1 VG

BL 0 BL 1

WL5 V

S D

WL 05 V

0 V

WL 10 V

1 V 0 V


NAND Flash Memory

Word line(poly)

Unit Cell GateONO

FGGateOxide

Source line Courtesy Toshiba(Diff. Layer)

Courtesy Toshiba


NAND Flash Memoryy

Word linesSelect transistor

Active area

STISTI

Bit line contact Source line contact

Courtesy Toshiba 34GMU, ECE 680 Physical VLSI Design

Characteristics of State‐of‐the‐art NVM


Read‐Write Memories (RAM) STATIC (SRAM)

D t t d l l i li dData stored as long as supply is appliedLarge (6 transistors/cell)FastDifferential

DYNAMIC (DRAM)

Periodic refresh requiredSmall (1‐3 transistors/cell)SlowerSingle Endedg


6‐transistor CMOS SRAM Cell

WLWL

VDD

M4M2

M5M6

42

QQ

M1 M3

BLBL


CMOS SRAM Analysis (Read)WL

VDD

BL

DD

M5

M6

M4BL

Q = 1Q = 0

M1V DDV DD V DD

C bit C bit


CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)

1.2

0.8

1

1.2V)

0.4

0.6

ge Rise (V

0

0.2Voltage rise [V]Volta

0 0.5 1 1.2 1.5 2Cell Ratio (CR)

2.5 3


CMOS SRAM Analysis (Write)

VDD

WL

Q = 0Q = 1

M4

M5

M6

BL = 1 BL = 0

M1VDD


CMOS SRAM Analysis (Write)y ( )


6T‐SRAM — Layout

VDD

M4M2

QQ

M1 M3

GND

M1 M3

WL

BLBL

M5 M6


Resistance‐load SRAM Cell

VDD

WL

M3

R L R L

Q QM43

M1 M2

4

BL BL

Static power dissipation -- Want R L largeBit lines precharged to V DD to address t p problemp


SRAM Characteristics


Page 663

3‐Transistor DRAM Cell

WWL

BL 1 BL 2

RWL

WWL

WWL

M3

RWL

VDD

VDD -VT

BL 1

XM1 XM2

C S

ΔVVDD -VTBL 2

No constraints on device ratiosReads are non‐destructiveValue stored at node X when writing a “1” = V VValue stored at node X when writing a 1 = VWWL ‐VTn


3T‐DRAM — Layout

BL2 BL1 GND

RWLM3M3

M2

WWLM1


Area: 50% of 6‐T SRAM

1‐Transistor DRAM CellWL

BL

WLWrite 1 Read 1

M1

CS

VDD 2 VTX GND

V

CBL

sensing

BLVDD

VDD /2 VDD /2

Write: C S is charged or discharged by asserting WL and BL.

BL

Write: C S is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

V BL VPRE– VBIT VPRE–CS

CS CBL+------------= =V

Voltage swing is small; typically around 250 mV.


DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read‐out.

DRAMmemory cells are single ended in contrast to SRAM cells DRAM memory cells are single ended in contrast to SRAM cells.

The read‐out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.

Unlike 3T cell 1T cell requires presence of an extra capacitance that must be explicitly Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD


Sense Amplifiers

t C Vmake V as smallas possibletp Iav

----------------= as possible

smalllargeg

Idea: Use Sense Amplifer

s.a.smalltransition

outputinput


Differential Sense AmplifierpVDD

M4M3

Outy

M1 M2 bitbit

M5SE

Directly applicable toSRAMs


Sense Amp Operation

V (1)V V (1)V BL

D V (1)VPRE

V (0)

S i d tSense amp activatedWord line activated


1‐T DRAM CellCapacitor

M1wordlineMetal word line

SiO 2

Diffusedbit line

P l

2

Field Oxiden+ n+

Inversion layer

Poly

Polysilicongate

Polysiliconplate

Cross‐section Layout

Polyy

induced byplate bias

Uses Polysilicon‐Diffusion Capacitance

Layout

Expensive in Area


SEM of poly‐diffusion capacitor 1T‐DRAM


Advanced 1T DRAM Cells

Capacitor dielectric layerCell plateWord line

Insulating Layer

Cell Plate Si

Capacitor Insulator Refilling PolyIsolationTransfer gate

Storage electrode

Storage Node Poly

2nd Field Oxide

Si Substrate

Trench Cell Stacked‐capacitor Cell


Static CAM Memory Celly

Bit Bit Bit Bit

CAM

Bit

Word

Bit

••• CAM

Bit Bit

M4 M5M8 M9

Bit Bit

••• •••Word

M7M6

SWord S

CAM

Match M1

M2M3int

Word

••• CAM

Wired‐NOR Match Line


CAM in Cache Memory

CAM

ARRAY

SRAM

Add D d

Hit LogicARRAY ARRAY

Address Decoder

Input Drivers Sense Amps / Input Drivers

Tag HitAddress DataR/W


Peripheryp y

Decoders Sense Amplifiers Sense Amplifiers Input/Output Buffers C t l / Ti i Ci it Control / Timing Circuitry


Row DecodersCollection of 2M complex logic gatesOrganized in regular and dense fashion

(N)AND Decoder

NOR Decoder


Hierarchical Decoders

•• •

Multi‐stage implementation improves performance

WL 1

WL 0

• • •

A 2A 3A 2A 3A 2A 3A 2A 3A 0A 1A 0A 1A 0A 1A 0A 1

A 2A 2A 3 A 3A 0A 0A 1 A 1

NAND decoder usingNAND decoder using22‐‐input preinput pre‐‐decodersdecoders


Dynamic Decoders

Precharge devices GND GND VDD

WL 3

WL 3

WL

VDD

WL 2

WL 1

WL 2

WL 1

VDD

V DD

VDD

WL 0

A 0A 0 A 1A 1A 0A 0 A 1A 1

WL 0

2‐input NOR decoder 2‐input NAND decoder


4‐input pass‐transistor based column decoder4 input pass transistor based column decoder

AS0

BL 0 BL 1 BL 2 BL 3

A 0

S 1

S 2

A 1

S 2

S 3

2-input NOR decoder

D

Advantages: speed (tpd does not add to overall memory access time)Only one extra transistor in signal path

Disadvantage: Large transistor count


4‐to‐1 tree based column decoderBL 0 BL 1 BL 2 BL 3

A 0

A 0

A 1A 1

A 1

DNumber of devices drastically reducedDelay increases quadratically with # of sections; prohibitive for large decoders

buffersprogressive sizing

Solutions: p g gcombination of tree and pass transistor approaches


ECE680: Physical VLSI Design - George Mason Universityece.gmu.edu/~qli/ECE680/chapter8 Memory...

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Transcript of ECE680: Physical VLSI Design - George Mason Universityece.gmu.edu/~qli/ECE680/chapter8 Memory...