Advanced VLSI Design Memory CMPE 640

1

Adv CMPE 640

Me

ses dynamic DRAM hysical location of data.ter) and Content Access

h larger than read time.

tion.ata. More difficult to

anced VLSI Design Memory

mory

Can be categorized into: Read Write Memory (RWM)

Random Access Memory (RAM): static SRAM (faster) ver(smaller) structures possible. Access time independent of p

Non-RAM: Serial Access Memory (FIFO, LIFO, Shift regisMemory (CAM). Non-uniform access time.

Non-volatile Read Write Memory (NVRWM): write time muc

EPROM, E2PROM, FLASH Read Only Memory (ROM)

A second classification for RAMs and ROMs: Static-load: no clock required. Synchronous: require a clock edge to enable memory opera Asynchronous: recognize address changes and output new d

build.

2

Adv CMPE 640

Meide (typically 1, 4 or 8

g exactly, high.

or small memoriesge memories

rd (where word = 8 bits) lines, provided by someice.


mory ArchitectureIn order to build an N-word memory where each word is M bits wbits), a straightforward approach is to stack memory:

This approach is not practical.What can we do?

S0

S1

S2

SN-2

SN-1

N w

ords

Word 0

Word 1

Word 2 Storage cell

Word N-2

Word N-1

Input-Output(M bits)

A word is selected by settinone of the select bits, Sx

This approach works well fbut has problems for lar

For example, to build a 1Mwo memory, requires 1M select

off-chip dev

3

Adv CMPE 640

Me

since the vertical wires

l

es the number of ex

ss pins from

to 20.


mory ArchitectureAdd a decoder to solve the package problem:

This does not address the memory aspect ratio problem:

The memory is 128,000 time higher than wide (220/23) !Besides the bizarre shape factor, the design is extremely slow

are VERY long (delay is at least linear to length).

S0

S1

S2

SN-2SN-1

Word 0Word 1Word 2 Storage cel

Word N-2

Word N-1


Dec

oder

A0A1

A2

AK-1

K = log2N

one-hot

Bin

ary

enco

ded

addr

ess

This reduc

addre

1M

4

Adv CMPE 640

Mer an aspect ratio of unity.:

Storage cell

Word line

Sense amps and drivers not shown


mory ArchitectureThe vertical and horizontal dimensions are usually very similar, foMultiple words are stored in each row and selected simultaneously

S0

S1

S2

SN-2SN-1


AKAK+1

AK+2

AL-1

Column address = A0

AK-1

Bit line

A0 to AK-1

Row address = AK to AL-1

A column decoder is added to select the desired word from a row.

Column decoder

Row

Dec

oder

5

Adv CMPE 640

Mes.nes.blem:

RA

CA

BA

ck P-1

A

32 blocks withblock.ock: 1024 rowslumns.


mory ArchitectureThis strategy works well for memories up to 64 Kbits to 256 KbitLarger memories start to suffer excess delay along bit and word liA third dimension is added to the address space to solve this pro

Global Data bus

owddress

olumnddress

lockddress

Block 0 Block i Blo

Globalamplifier/driver

I/O

ddress: [Row][Block][Col]

Block selector

4 Mbit: P =128Kbits/128Kbit bland 128 co

6

Adv CMPE 640

Me

te memory.

r word = 28 = 256 words.

e buffers

2n-k bits


mory: Architecture

An example:

For example: Let N = 1,048,576 and M = 8 bits for a 1 million byn = log2N = 20, k = 8 and m = log2M = 3.

Then there are 2n-k rows = 212 = 4096 and 2k+m columns/23 bits pe

Row decoder

Row decoder

Row decoder

Row decoder

Column decoder column mux, sense amp, writ

2m+k bits

A0

Ak

Ak+1

An-1

Ak-1[An-1..Ak][Ak-1..A0]

7

Adv CMPE 640

RO

BL

BL

S used to holdh. n-MOSes pull-down

S

fe


MROM cells are permanently fixed: Several possibilities:

BLWL

1

0

BLWL

Diode supplies currentto raise BL (bitline) forall cells on the row.

BLWL

BJT supplies currentto raise BL for eachcell on the row. RequiresVDD to be routed.

WL

WL

WL

p-MOBL higprovidpath.

psuedo n-MONOR gate.

Resistance on/p should bat least 4.

8

Adv CMPE 640

No

h modifications to

in create high electric

leaving it negatively

ate does not permit the

in

20V


n-volatile Read-Write MemoriesVirtually identical in structure to ROMs.Selective enabling/disabling of transistors is accomplished througthreshold voltage. This is accomplished through a floating gate.

Applying a high voltage (15 to 20 V) between source and gate-drafield and causes avalanche injection to occur.

Hot electrons traverse first oxide and get trapped on floating gate,charged.

This increases the threshold voltage to ~7V. Applying 5V to the gdevice to turn on.

tox

tox

Source Dra

Substrate

n+ n+

Gate

Floating Gate- - - - - - - -

-5V afterprogrammingthis device off

-

20V

9

Adv CMPE 640

No

he various classes of

ing and access device.


n-volatile Read-Write Memories

The method of erasing is the main differentiating factor between treprogrammable nonvolatile memories.

EPROM:UV light renders oxide slightly conductive.Erase is slow (seconds to several minutes).Programming is slow (5-10 microsecs per word).Limited number of programming cycles - about 1000.Very dense - single transistor functions as both the programm

10

Adv CMPE 640

No

via Fowler-Nordheim

riting.in

10V

ults in a

or.

oblem:

turned off.


n-volatile Read-Write Memories

EEPROM or E2PROM:Very thin oxide allows electrons to flow to and from the gatetunneling with VGD applied.

Erasure is achieved by reversing the voltage applied during w

tox

tox

Source Dra

Substrate

n+ n+

Gate


thin tunneling ox

BLWL

VDD

Removing too much charge res

Remedy: Add an access transist

Threshold control becomes a pr

depletion device that cannot be

11

Adv CMPE 640

No

M.

ld during erasure - mak-ent device.

in

12V


n-volatile Read-Write Memories Flash EEPROM:

Combines density adv. of EPROM with versatility of EEPROUses avalanche hot-electron-injection approach to program.Erasure performed using Fowler-Nordheim tunneling.Monitoring control hardware checks the value of the threshoing sure the unprogrammed transistor remains an enhancem

Programming performed by applying 12V to gate and drain.Erasure performed with gate grounded and source at 12V.

tox

Source Dra

Substrate

n+ n+

Gate


thin tunneling ox

-

erasure

- programming

12V

12V

12

Adv CMPE 640

Re

w


ad-Write Memories (RAM)SRAM:

ord line

VDD

bit bit

13

Adv CMPE 640

Re


ad-Write Memories (RAM)Generic RAM circuit:

Bit LineConditioning

clocks

RAM cell

Sense AmpColumn MuxWrite Buffers

n-1;k

k-1;0

read-data write-dataAddress

bit bit

word linerow decoder

column decoder

14

Adv CMPE 640

Re

ine improves perfor-

w

ize speed, annels as

ge devices.

precharge

bit, bit

word

data


ad-Write Memories (RAM)SRAM: Read Operation

Precharging bit and bit_bar to 5V before enabling the word lmance.

precharge

ord

bit bit

data

To optimuse n-chprechar

VDD

15

Adv CMPE 640

Re

w

write-data

bit, bit

word

w

w

write

cell, cell

ginally.o pull Pbit below.


ad-Write Memories (RAM)SRAM: Write Operation:

ord

bit bit

N5 N6

N3 N4

N1 N2

rite-data

rite

cell cell

Zero stored in cell ori

Nd

Nd, N1, and N3 have tthe inverter threshold

0->11->0 Pbit

1

0

16

Adv CMPE 640

Re

read-data1

a

-read-port

Adv: Nomatterwhat theload, cellcannot beflipped.

d


ad-Write Memories (RAM)Register files:

4/1

2/2

2/3

2/1

8/1

4/1

4/1

4/1

4/1

write-data read-data0

ddr<3:0>

Single-write-port, doubleOverpowersweak feedbackinverter

Biased towardVSS to help write.

ecode

17

Adv CMPE 640

Re

g the cell contents.

SRAM cell.


ad-Write Memories (RAM)DRAM:

Refresh: Compensate for charge loss by periodically rewritinRead followed by a write operation.Typical refresh cycles occur every 1 to 4 milliseconds.

4 transistor DRAM created by simply eliminating the p tree in an

Logic 1 values are, of course, a threshold below VDD.

word line

bit bit

18

Adv CMPE 640

Re

n bit1 and assert write.rent).licity in both design and

write

bit1

read

bit2

X

V


ad-Write Memories (RAM)3T DRAM:

Most common method of refresh is to read bit2, place its inverse oPrecharge method of 'setting' bit2 is preferred (no steady-state curMemory structure of choice in ASICs because of its relative simpoperation.

write

readbit1 bit2

X

VDD-VTbit2 is either clamped to VDD or is precharged to either VDD or VDD-VT.

No device ratioing necessary here !

Note that this cell is inverting

19

Adv CMPE 640

Re

node X and node bit. the delta-V value is typ-

word-line

bit

X-VT

ng

V

e)Cx

(Cx + Cbit)


ad-Write Memories (RAM)1T DRAM

During read operation, charge redistribution occurs between Cx is typically 1 or 2 orders of magnitude smaller than Cbit so

ically 250 mV.

Most pervasive DRAM cell in commercial memory design.

word-line

bit

VDD

write read

X

Vpre = VDD/2

VDD

sensi

V = Vbit - Vpre = (Vx - Vpr

Cx Cbit

20

Adv CMPE 640

Re

ry in order for the cell to

operation.mposed onto the bit line

tance). Capacitance must

ts VT loss on storage


ad-Write Memories (RAM)1T DRAM observations:

Amplification of delta-V (through a sense amplifier) is necessabe functional.

Other cell designs used sense amps only to speed up the read The read-out operation is destructive ! Output of sense amp is iwith word-line high during read-out.

1T transistor requires an explicit capacitor (3T used gate capacibe large (~30fF) but area small - key challenge in design. Bootstrapping word-line to a value larger than VDD circumven

capacitor.

Vpre

V(1)Sense amp activated

Word-line activated

V(0)

21

Adv CMPE 640

Re

ed word.

t of the wordo the match line.

MOS ble.

ANY SRAM celll or bit/cell.


ad-Write Memories (RAM)Content Access Memory (CAM):

Determines if a match exists between a data word with a storUsed in Translation-look-aside buffers.

word line

VDDbit bit

cellcell

matchXOR function.

SRAMwith extran-channels

Each biis tied t

Dynamic or Pseudo n-implementations possi

to implement

Match is 0 ifhas bit/celequal to 1

Advanced VLSI Design Memory CMPE 640

Documents

Transcript of Advanced VLSI Design Memory CMPE 640