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1

Bipolar Digital Circuits(Chapter 17)

• There are two major classes of bipolar digital logic circuits:

• Emitter Coupled Logic (ECL)• Transister-TransisterLogic (TTL)

ECL is the fastest bipolar technology is used in applications where high speed is required such as high speed circuits utilized in superconductors.

A bipolar technology that has a higher noise margin is TTL. Transistors in this technology are driven between cutoff and saturation. 2

The Current Switch (Emitter-Coupled Pair)

• The building block of emitter-coupled logic (ECL) is the current switch circuit which consists of matched components

3

Basic Concept of a Differential Amplifier Circuit

• The emitter coupled logic circuit (ECL) is based on the differential amplifier. In digital applications , the diff-amp transistors are either cutoff or in the active region. Saturation is avoiding in order to minimize switching timesand propagation delay time.

• For digital applications, the input voltages are large, because one transistor is needed to remain biased in its active region while the opposite transistor in cutoff.

TBE

TBE

vvSC

vvSC

eII

eII/

2

/1

2

1

=

=

4

Differential Amplifier Circuit (cont.)

Case I: when Q1 is on and Q2 is cutoff:

This condition can be achieved ifvBE1 of Q1 is 120mV greater thanthe vBE2 of Q2. Under this conditionthe collector current of Q1 is 100times that of Q2.

Case II: when Q1 is effectively cutoff and Q2 is on:

Again this condition can be achievedif v1 is less than v2 by at least120mV.

Under above two conditions the diff-amp operates as a current switch.Why?

2

5

The Current Switch • Depending on how much higher or lower the

input voltage vI is compared to VREF, the reference current will switch to one of the legs creating a voltage vC1or vC2

6

Basic ECL Logic OR/NOR Gate

Case I:If both VX and VY are less thanthe reference voltage VR( at least 120 mV), then Q1 and Q2

are cut off and QR is in activemode.This implies that;VO1>VO2

Case II:

If either Vx or Vy become greaterthan VR then VO2>VO1

The OR logic is at the V02 output and NOR logicis at the VO1output

An advantage of ECL is its complementary outputs.

7

The ECL OR-NOR Gate

Three variations of a 3-input ECL OR-NOR Gate

8

One Problem with the ECL circuit ?(the output voltage is not compatible with the input

voltage)

Normal operation of the circuit shown in the figure, requiring that, base collector junction must be reversebiased all the times but this is not alwayspossible.

For example:

In the ECL circuit shown in the Figure, If either VX or VY=V+

then Q1 and Q2 would turn on and thecollector voltage Vo1 would decrease below V+.

At this condition the base collector would then become forward biased and transistor switch into saturation region.

Emitter followers ECL circuit has been design to overcome this problem.

3

9

ECL Logic Gate with Emitter Followers• In the circuit shown in the figure the

output voltage is measured as emitter-collector voltage, which has the advantage of less noise sensitivity.

Case I: If either VX or Vy is a logic 1.

Then, QR is cutoff, ICR=0, VO2=0, Q3 is on and

VOR = VO2 – VBE (on) = - 0.7V (largest output).

Case II: if both VX and VY are a logic 0.

Then, both Q1 and Q2 are off, VO1=0 andVNOR = 0 – VBE (on) = - 0.7V (largest output)

This implies that the largest possible voltage that can be achieved at either output is -0.7V, which is defined as the logic 1 level.

In the present circuit V+

is set equal to zero10

ECL circuit analysis

Case I

Case II

on

VE

Case I

11

Case II

For symmetrical complementary output, RC1 and RC2 are not equal.

12The power dissipation is significantly large.

4

13

ECL Logic gate with reference circuit

1. Power Dissipation

The power dissipation of standard ECL logic circuit is given by,

• PD=(iCxy+iCR+i5+i1+i3+i4)(0 – V-) Complete Two input ECL OR/NOR logic circuit with reference voltage VR.

The reference circuit consist of resistors R1, R2and R5, diodes D1 and D2 and transistor Q5.

14

Example 17.4

15

Propagation Delay Time • The major advantage of ECL circuit is their

small propagation delay time.• The change in voltage in ECL from logic 0 to

logic 1 is very small (0.7V), which means that voltage across the output capacitors do not have to change up to VDD as changed in CMOS circuits.

• Trade-offs for the small propagation delay time are higher power dissipation and smaller noise margins.

16Is this a realistic fanout?

5

17

Voltage Transfer Characteristics(DC Analysis ref. example 17.3)

Case I: NOR gate output (VNOR)If input VX and VY are a logic 0 or -1.40V.Then Q1 and Q2 are cut off andVNOR=V+-VBE(on)= 0 - 0.7V = - 0.7V (logic

1)

OR gate output (VOR)Under the above condition, the QR is on,

and VB3= - 0.7V and VOR= VB3-VBE(on)= - 0.7- 0.7= - 1.40V

(logic 0)Case II: When VX=VY=logic 1 orVR + 0.12V= -0.93V , then Q1 and Q2 are

on and QR is off, and VNOR=-1.36V and VOR=-0.7V as shown in the figure.

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Noise Margin

• As we know the noise margins are defined as

• NML=VIL- VOL (noise margin for low input)

• NMH=VOH -VIH (noise margin for high input)

• From given figure we have,• VIL= -1.17V and VIH = - 0.93V,

which are the point of discontinuity in the VT curves.

Similarly the high logic level is VOH =- 0.7V and the low logic value is

VOL= - 1.40V.Using given data we have NMH=

0.23V and NML=0.23V

The noise margins in ECL logic circuits are considerably lower than those for NMOS and CMOS.

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Modified ECL Circuit Configurations: Low power ECL

• In some applications, both complementaryoutputs may not be required.

• If for example OR output is required, then we can eliminate resister RC1.

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Analysis of modified ECL logic gateCase I:If VX=VY=logic 1>VRUnder this condition Q1 and Q2 are

turn on and QR is off and logic 1 output voltage is: VOR=VCC

Case II: If VX=Vy=logic 0<VRUnder this condition, transistors Q1

and Q2 are off and QR is on, then,

And the output voltage is VOR=VCC – iCRRC2

CRE

BERE i

RonVVI ≅

−=

)(

Problem: The logic 0 is not well define because RE and RC2 may vary fromOne circuit to another during fabrication process.Problem: The logic 0 is not well define because RE and RC2 may vary fromOne circuit to another during fabrication process.

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21

ECL Logic Gate with Emitter Followers• In the circuit shown in the figure the

output voltage is measured as emitter-collector voltage, which has the advantage of less noise sensitivity.

Case I: If either VX or Vy is a logic 1.

Then, QR is cutoff, ICR=0, VO2=0, Q3 is on and

VOR = VO2 – VBE (on) = - 0.7V (largest output).

Case II: if both VX and VY are a logic 0.

Then, both Q1 and Q2 are off, VO1=0 andVNOR = 0 – VBE (on) = - 0.7V (largest output)

This implies that the largest possible voltage that can be achieved at either output is -0.7V, which is defined as the logic 1 level.

In the present circuit V+

is set equal to zero22

ECL Logic gate with reference circuit

1. Power Dissipation

The power dissipation of standard ECL logic circuit is given by,

• PD=(iCxy+iCR+i5+i1+i3+i4)(0 – V-) Complete Two input ECL OR/NOR logic circuit with reference voltage VR.

The reference circuit consist of resistors R1, R2and R5, diodes D1 and D2 and transistor Q5.

23

Example 17.4

24

Propagation Delay Time • The major advantage of ECL circuit is their

small propagation delay time.• The change in voltage in ECL from logic 0 to

logic 1 is very small , which means that voltage across the output capacitors do not have to change up to VDD as changed in CMOS circuits.

• Trade-offs for the small propagation delay time are higher power dissipation and smaller noise margins.

7

25Is this a realistic fanout?

26

Voltage Transfer Characteristics(DC Analysis ref. example 17.3)

Case I: NOR gate output (VNOR)If input VX and VY are a logic 0 or -1.40V.Then Q1 and Q2 are cut off andVNOR=V+-VBE(on)= 0 - 0.7V = - 0.7V (logic

1)

OR gate output (VOR)Under the above condition, the QR is on,

and VB3= - 0.7V and VOR= VB3-VBE(on)= - 0.7- 0.7= - 1.40V

(logic 0)Case II: When VX=VY=logic 1 orVR + 0.12V= -0.93V , then Q1 and Q2 are

on and QR is off, and VNOR=-1.36V and VOR=-0.7V as shown in the figure.

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Noise Margin

• As we know the noise margins are defined as

• NML=VIL- VOL (noise margin for low input)

• NMH=VOH -VIH (noise margin for high input)

• From given figure we have,• VIL= -1.17V and VIH = - 0.93V,

which are the point of discontinuity in the VT curves.

Similarly the high logic level is VOH =- 0.7V and the low logic value is

VOL= - 1.40V.Using given data we have NMH=

0.23V and NML=0.23V

The noise margins in ECL logic circuits are considerably lower than those for NMOS and CMOS.

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Modified ECL Circuit Configurations: Low power ECL

• In some applications, both complementaryoutputs may not be required.

• If for example OR output is required, then we can eliminate resister RC1.

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29

Analysis of modified ECL logic gateCase I:If VX=VY=logic 1>VRUnder this condition Q1 and Q2 are

turn on and QR is off and logic 1 output voltage is: VOR=VCC

Case II: If VX=Vy=logic 0<VRUnder this condition, transistors Q1

and Q2 are off and QR is on, then,

And the output voltage is VOR=VCC – iCRRC2

CRE

BERE i

RonVVI ≅

−=

)(

Problem: The logic 0 is not well define because RE and RC2 may vary fromOne circuit to another during fabrication process.Problem: The logic 0 is not well define because RE and RC2 may vary fromOne circuit to another during fabrication process. 30

How can we establish a well define logic 0 output?

• A well define logic 0 value can be achieved by inserting a Schottky diode in parallel with resister RC.

• When VX=VY=0, Q1 and Q2 are off and QR is on .Under this condition the Schottky diode is turn on and,

VOR= VCC-Vγ,where γ is turn on voltage of the

diode. Clearly VOR is independent of any resister in the circuit.

Also iR(max)= V γ/RCAnd iD=iE-iR(max)

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VOR(Logic 1): when VX and VY=logic 1

VOR(Logic 0): when VX and VY=logic 0

Power dissipation when output is logic 0

Power dissipation when output is logic 1

How the power dissipation is reduced?

If VR is the average oflogic 1 and logic 0, thenoutput is compatible within input.

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Diode transistor logic gate (DTL) • The ECL circuits have very low noise margin (i. e. 0.23V). In order to

overcome this problem, TTL circuits have been introduced.

• The basic building block of transistor transistor logic gate (TTL) is diode transistor logic gate (DTL). Therefore, it is important to first understand DTL.

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33

Basic BJT transfer characteristics revisited

• In TTL and DTL technology transistors are driven between cutoff and saturation.

• This mode of operation reduced the switching speed of TTL compared to that of ECL.

• However, higher speed in TTL is achieved in Schottky TTL circuits.

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Basic Diode Transistor Logic (DTL) NAND Gate

• Case I: If Vx = V y= logic 0=0.1V,then DX and Dy are forward bias, and V1=Vx + Vγ= 0.8V( v1 is clamped)Under this condition diode D1 andD2 and transistor Qo are

nonconducting and off and V0=VCC =5V, which is logic 1.

Case II: when Vx = V y= logic 1=5VUnder this condition Dx and Dy are cutoff

and D1 and D2 are on, and QO driven into saturation region.

Hence V0=VCE(sat)=0.1V, which is logic 0Similarly, other possible inputs canbe tested to satisfied NAND gate

operation.

NAND gate : 0 0 11 0 10 1 11 1 0

VX VY Vo

VOL= VCE(sat

VIL=1.4V VIH= 1.5V

VOH

QO(off) Edge of conduction

Edge of saturation

VO

35

Basic Diode Transistor Logic (DTL) NAND Gate

• Case I: If Vx = V y= logic 0=0.1V,then DX and Dy are forward bias, and V1=Vx + Vγ= 0.8V( v1 is clamped)Under this condition diode D1 andD2 and transistor Qo are

nonconducting and off and V0=VCC =5V, which is logic 1.

Case II: when Vx = V y= logic 1=5VUnder this condition Dx and Dy are cutoff

and D1 and D2 are on, and QO driven into saturation region.

Hence V0=VCE(sat)=0.1V, which is logic 0Similarly, other possible inputs canbe tested to satisfied NAND gate

operation.

NAND gate : 0 0 11 0 10 1 11 1 0

VX VY Vo

VOL= VCE(sat

VIL=1.4V VIH= 1.5V

VOH

QO(off) Edge of conduction

Edge of saturation

VO

36

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Example 17.8 (cont.)

NAND gate : 0 0 1

1 0 10 1 11 1 0

Vx vy vo

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Problem 17.10:Using the results of example 17.8,calculate power dissipation for(a) Vx = Vy = 5V (b)Vx = Vy = 0.

Solution (a) Vx = Vy = 5 V

V1 = VBE(sat) + 2Vγ= 0.8V + 2(0.7) = 2.2V

i1 = (Vcc-V1)/R1=(5-2.2)/4=0.7 mA

iRC = (VCC - VCEsat)/R = (5

0.1)/4 = 1.23 mA

P=(i1 + iRC)VCC = (0.7V + 1.23)(5) = 9.65 mW

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Transistor-Transistor Logic (TTL)

• In 1965, TTL was introduced. Basically, the usage of diodes in DTL was replaced with a transistor.

• The main improvement in TTL design over DTL is improved switching speed due to reduction in the propagation delay time.

Pull down resister DTL TTL

Pull down resister RB is no longer necessary, since The excess minority carrier in the baser of Qo use Q1 as a path to ground

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TTL circuit with three emitter input transistor.

In Isoplanar integrated circuit technology, the number of inputs can be increaseby diffuse more emitters in the same base region as shown in the above figure. Thisapproach reduce the chip area required for the TTL IC.The above circuit perform same NAND gate operation as its DTL counterpart.

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Analysis of TTL circuit: When at least one or both inputs are low

• If either or both inputs to Q1 are low logic (0.1V), the base emitter junction will become forward biased.

Under this condition, the collector current of Q1 would be equal to the reveresaturation current out of the base of Qo,

and Q1 is biased in saturation and Qo incutoff. The base voltage of Q1 is

VB1 = VX + VBE(sat)

And the base current of Q1 is

IB1 = (VCC - VB1) / R1

And the collector voltage of Q1 is

VC1=Vx + VCE (sat)

VO=VCC=Logic 1

NAND gate : 0 0 11 0 10 1 11 1 0

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Analysis of TTL circuit: When all input are high

• If all inputs are high, VX=Vy=5V.• Under this bias condition, B-E junction

of Q1 are reverse biased and B-C junction are forward biased and Q1 is biased in the inverse active mode.

• The base voltage VB1 is give by,

VB1 = VBE (sat) Qo + VBC (on)Q1If we assume that B-C and B-E junctions

turn on voltages are same then, iEX = iEY = βRiB1 andiC1 = iB1 + iEX + iEY = iB1 + 2βRiB1 = (1 + 2βR)iB1

VO(sat)=Logic 0=0.1V

What would be relationship between iC1 and βR , if number of inputs are three?

NAND gate : 0 0 11 0 10 1 11 1 0

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Improved TTL NAND gate

The TTL NAND gate can be improved by adding a second current gain stage as shown in the figure.

The characteristics of TTL circuit will be discussed in the following example(17.9)

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TTL NAND gate: DC current –voltage analysis

NAND gate : 0 0 11 0 10 1 11 1 0

12

45

Problem 17.18 on page 1167Determine the currents i1, i2, i3, i4, iB2 and iB3 for the

following input conditions:(i) Vx=Vy=0.1V(ii) VX=Vy=5VSol:Given that Vx=Vy=0.1V ⇒Q1 in saturationVB1= Vx+VBE(sat)= 0.1+0.8=0.9Vi1= (VCC-VB1)/R1 = ( 5-0.9)/6 = 0.683 mASince Q2 and QO are in cutoff mode,⇒iB2 = i2 = i4 = iB 3= I 3= 0ii) Given that VX=Vy=5V, which implies that Q1 is inverse

active mode and Q2 and Q3 would switch into saturation mode.

VB1= VBE(sat)Qo+VBE(sat)Q2+VBC(on)Q1

VB1= 0.8+0.8+0.7=2.3Vi1+(VCC-VB1)/R1= (5-2.3)/6=0. 45mA=iB2I2=(VCC-VC2)/R2={5-(0.8+0.1)]/6=2.05mAI4=VBE(sat)/RB=0.8/1.5=0.533mAiB3=(iB2+i2)-i4=0.45+2.05-0.533=1.97mAi3=(VCC-Vo)/RC= (5.0.1)/2.2= 2.23mA(b) For Q3: i3/iB3=2.23/1.97=1.13<βFor Q2: i2/iB3=2.05/0.45=4.56<βThis implies that Q3 and Q2 are in saturation.

46

Improved TTL NAND gate

The TTL NAND gate can be improved by adding a second current gain stage as shown in the figure.

The characteristics of TTL circuit will be discussed in the following example(17.9)

47

TTL NAND gate: DC current –voltage analysis

NAND gate : 0 0 11 0 10 1 11 1 0

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Problem 17.18 on page 1167Determine the currents i1, i2, i3, i4, iB2 and iB3 for the

following input conditions:(i) Vx=Vy=0.1V(ii) VX=Vy=5VSol:Given that Vx=Vy=0.1V ⇒Q1 in saturationVB1= Vx+VBE(sat)= 0.1+0.8=0.9Vi1= (VCC-VB1)/R1 = ( 5-0.9)/6 = 0.683 mASince Q2 and QO are in cutoff mode,⇒iB2 = i2 = i4 = iB 3= I 3= 0ii) Given that VX=Vy=5V, which implies that Q1 is inverse

active mode and Q2 and Q3 would switch into saturation mode.

VB1= VBE(sat)Qo+VBE(sat)Q2+VBC(on)Q1

VB1= 0.8+0.8+0.7=2.3Vi1+(VCC-VB1)/R1= (5-2.3)/6=0. 45mA=iB2I2=(VCC-VC2)/R2={5-(0.8+0.1)]/6=2.05mAI4=VBE(sat)/RB=0.8/1.5=0.533mAiB3=(iB2+i2)-i4=0.45+2.05-0.533=1.97mAi3=(VCC-Vo)/RC= (5.0.1)/2.2= 2.23mA(b) For Q3: i3/iB3=2.23/1.97=1.13<βFor Q2: i2/iB3=2.05/0.45=4.56<βThis implies that Q3 and Q2 are in saturation.

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49

Draw back of the basic TTL NAND gate

In all digital circuits there is always existing a load capacitor, which is composed of the input capacitance of the load circuitsand the capacitance of the interconnect lines.

During circuit operation this load capacitor must be charged through collector pull-up resistor.

It has been estimated that the RC time constant of a basic TTL circuit is about 60ns, which is large enough compared to the propagation delay time (PDT) of a commercial TTL circuit. 50

Addition of totem pole output stage to overcome the problem

Case I: How the output transistor discharge the load capacitor quickly?

If Vx=Vy=1Input transister Q1 is biased in the inverseactive mode, and both Q2 and Qo are driven

into saturation. The voltage at the base of Q3is,

VB3=VC2=VBE(sat)QO+VCE(sat)Q2 = 0.8 + 0.1 = 0.9V

Clearly, VB3 is not enough to turn on Q3 andD1.⇒ Q3 remain in cut off mode when output islow.

Under this condition the low output transistordischarge the load capacitor and pull the

output low very quickly. That means PDTimproved.

Totem pole

VC2

51

Addition of totem pole output stage to overcome the problem (cont.)

• Case II: How the output transistor charge the load capacitor quickly?

If VX=VY=logic 0Under this biased mode Q1 is on, and Q2

and QO are in cut off, and VB3= VCC= 5V, which is sufficient to turn on

Q3 and D1⇒ current in the output capacitor can

flow through Q3 and D1 and capacitance can be fully charged quickly because the internal resistance of Q3 and D1 is very small in conduction mode, so RC time constant of the capacitor will be very short. In other words, PDT of the TTL circuit has been improved.

Totem pole

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FanoutIn digital circuits the main use of a logic circuit is drive other similar type logic gates to perform a complex logicfunction. The maximum number of

similar type of logic gates that can beconnected to the logic gate output

without effecting proper circuitoperation is known as fanout.

For a given value of β there is alwaysmaximum allowable load current and

load circuits.

An another condition is the load current iLL that Qo must sink from the load as

shown in the figure.The above concept will be explored byfollowing example.

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53

How can we estimate maximum fanout for the output low condition?: Example 17.10

54

How can we estimate maximum fanout for the output low condition?: Example 17.10 (cont.)

55

How can we estimate maximum fanout for the output low condition?: Example 17.10 (cont.)

56

Modified Totem-Pole Output stage

In modified TTL circuit a transistorQ4 has been used instead of

diode.Advantages of modified circuit:

i) the pair transistor Q3 and Q4increase the fanout capability of theTTL gate in its high state

ii) The output impedance is relativelyLower in its high state , whichdecrease switching time.

iii) The B-E junction of Q3 behave as diode D1 and diode is no more need to provide a voltage offset.

1

15

57

Analysis of Modified Totem-Pole Output stage (when output is low)

• In the circuit the role of the R4 at low output is to provide a path to ground for the minority carrier that must flow from base of Q3 to the ground to turn the transistor off.

When output is low Q2 and QO must be in saturation and base voltage of Q4 is,

VC2 = VCE(sat)Q2 + VBE(sat)QO = 0.9V

, which is sufficient to turn on the transistor Q4. However, VE is only 0.2V, which implies that current in Q4 is very small and consequently power dissipation is small.

VE

2

VC2

58

Problem 17.21aGiven that βF=50, βR=0.1, VBE(on)=0.7V,VBE(sat)=0.8V, and VCE(sat)=0.1V

Determine the power dissipation in the circuits for (a) Vin=0.1V and (b) Vin=5V

Solution: Vin=0.1VQ1 must be conduct and in saturation modeQS and QO remains in cutoff mode.Under this condition,

VB1= VIn+ VBE(sat)= 0.1 + 0.8=0.9V

i1= (VCC-VB1)/RB= (5 - 0.9)/4 = 1.025mAP=i1 X ( VCC-Vin) = (1.025)(4.9) = 5.02 mW

3

i1VB1

59

Problem 17.21b(b) When Vin=5V

Q1 is in inverse active modeQs and QO are in saturation mode

VB1=VBC(on)Q1+VBE(sat)QS+VBE(sat)Qo

VB1=0.7+0.8+0.8=2.3V

i1=(Vcc-VB1)/RB=(5-2.3)/4=0.7mA

iE1=βi1=(0.1)(0.7)=0.07mA

Vout=VCE (sat)Qs+ VBE(sat)Qo

Vout= 0.8+0.1=O.9V

io=(Vcc-Vout)/1=4.2mA

P=(i1+IEI+iO)(5) = 24.9mW

• The high power dissipation suggested that this TTL circuit is not attractive for practical applications

4

VB1

i1

iE1

io

i1

VB1

Reverse currentVout

60

Problem 17.24 (a)

5Given that βF=100, βR=0.2, Fout=5Vx=Vy=Vz=0.1VDetermine iB1, iB2, iB3, iC2 and iC3Sol:VB1=Vx+VBE(sat)Q1 = 0.1 + 0.8 = 0.9V

iB1=iB3+(2-VB1)/RB1

Where iB3 = [Vcc - VEB(on)Q3] - VB1/RB2

iB3=[{2 - 0.7} - 0.9]/1 = 0.4mA

iB1=1.1 + 0.4 = 1.4mA

iB2=0 because Q2 is off

Since Q3 is in saturation

iC3 = 5iL’ for Vo high

V َََB1=VCB(on)Q1 + VEB(sat)Qَ 1=0.7 + 0.8=1.5V Qَ3 is off

iَB1 = 2 - 1.5/1 = 0.5mA

iَL1 = βRiَB1=0.2 X 0.5 = 0.1mA

iC3 = 5x 0.1 = 0.5mA

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61

Problem 17.24 (a)

Given that βF=100, βR=0.2, Fout=5Vx=Vy=Vz=0.1VDetermine iB1, iB2, iB3, iC2 and iC3Sol:VB1=Vx+VBE(sat)Q1 = 0.1 + 0.8 = 0.9V

iB1=iB3+(2-VB1)/RB1

Where iB3 = [Vcc - VEB(on)Q3] - VB1/RB2

iB3=[{2 - 0.7} - 0.9]/1 = 0.4mA

iB1=1.1 + 0.4 = 1.4mA

iB2=0 because Q2 is off

Since Q3 is in saturation

iC3 = 5iL’ for Vo high

V َََB1=VBC(on)Q2َ + VEB(sat)Qَ 1=0.8 + 0.7=1.5V Qَ3 is off

iَB1 = 2 - 1.5/1 = 0.5mA

iَL1 = βRiَB1=0.2 X 0.5 = 0.1mA

iC3 = 5x 0.1 = 0.5mA

Q3 is cutoff!!

62

Schottky Transister-Transister Logic(short storage time)

• The speed of the TTL circuits thus far studied is limited by two mechanism:

i) All the transistors are in saturation mode while conducting, which limits the switching speed because the amount of time required to remove the storage charge from the base of the saturated transistor is longer. The obvious solution of this problem is to use a BJTs in such a way that do not deep saturate.

ii) The resistances in the circuit, together with the various transistors and wiring capacitances, results relatively longer time constant which slow the speed of TTL circuit. The solution of this prblem is to reduced all resistances.

63

How can we prevent deep saturation?: By Using a Schottky Clamped Transistor

• Schottky Clamped Transistor , transistors are prevented from saturation by connecting a Schottky diode between base and collector. In BJT, saturation mode, can be avoided by limiting forward bias base collector voltage, which is given by;

VBC (sat)=VBE (sat) - VCE (sat) = 0.8 - 0.2 = 0.6V

The Schottky diode limit the base current as well as clamp the base collector voltage to turn on voltage (0.3-0.4V), which is less that the value required to saturate the transistor. Hence, by using SchottkyClamped Transistor non saturation can be achieved, which exhibits a very short turn off time.

64

Characteristics of Schottky Clamped Transistor

• Case I: When the transistor is in its active region, the base collector junction is in reverse biased, which means that Schottky diode is reverse bias and out of the circuit.

• Case II: when the transistor is trying to switch into saturation region, the base collector junction become forward biased. Under this condition the base collector voltage become equal to diode turn on voltage (0.3V), which prevent the npn transistor deep into saturation by shunting base current through the diode.

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Characteristics of Schottky Clamped Transistor (cont.)

• From the figure we can write a relationship between different current in the circuit as,

• iC´ =iD + iC (i)• iB= iB´ + iD (ii)• And iC´=βiB´ (iii)• By combining (ii) and (iii) we can

write as,• iD=iB-iB´=iB-iC´/β• by substituting this value into (i)

we can write as• iC´=iB - iC´/β + iC or

β11+

+=′ CB

Ciii

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β11+

+=′ CB

Ciii

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When the Schottky transistor is biased in saturation mode

• Since the internal npn transistor is not in the deep saturation mode, so we can assume that VBE=VBE(on) If the Schottky transistor is biased in saturation then we can write,

• VCE = VCE(sat ) = VBE(on) - Vγ(SD)• VCE(sat) = 0.7 - 0.3 = 0.4V

• Although the output low logic is higher than VCE(sat) and results in slight reduced logic swing but disadvantage is quite minor in comparison with the speed improvement.

When the Schottky transistor is at the edge of saturation we can write,

iD = 0, iC = βiB, and VCE = VCE(sat) = 0.1V

•

+VCC

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Problem 17.16

Given that β=10, VBE(on)=0.7V, Vγ(SD)=0.3V(a) For no load iL=0, find iD, iB´, iC´(b) Determine maximum load current that the transistor can sink and still

remain at the edge of saturation.Sol: (a):From the figure iRC=(VCC-VCE)/RC=(5-0.4)/2.25=2.04mA

iC´= (2 + 2.04) / 1 + 1 / 10 = 3.67mA

iB´= iC´/β = 3.67 mAiD = iB- iB´= 2 - 0.367 = 1.63mA

(b): Since transistor should be in the edge of saturation. This implies that iD=0

iB´= iB=2 mA

iC´=βiB´ = (10)(2) = 20mA = iRC+iL

iL=iC´-iRC= 20 - 2.04 ≅ 18mA

•

β11+

+=′ CB

Ciii

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Schottky TTL NAND Circuit• As compared to standard TTL circuit a

Schottky TTL circuit reveals a number of variations.

• i) Schottky clamped has been added to all transistors excerpt Q3 , which will, never saturate because,

VCE3=VCE4+VBE3=0.4 + 0.7=1.1V

• ii) All the resisters have been reduced almost half the values used in the standard circuit.

• The above two new feature result in a much shorter gate delay., which is the order of 2 to 5ns, compared to 10 to 15ns for standard TTL circuits.

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Further Features of Schottky TTL Circuit

1) The input clamping diodes are used to limit the negative swing (ringing) of the inputs to one diode drop below ground because these diode conduct only when input voltage go below ground level.

2) The resistance between the base of the Qo and ground is replaced by a nonlinear resistance consist on Q5, R5and R6. This nonlinear resistance is known as Squaring network and active pulldown.

3) The function of resister R6 is used to avoid the clamping of B-E voltage of Qoclamped to VEC5.

The typical power dissipation in the Schottky TTL is about 32mW for low logic, which is very high!!! .

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Advance Low Power Schottky TTL Inverter Circuits (ALSTTL)

In ALSTTL the propagation delay time was reduced down to 1.5ns, while still maintaining the low power dissipation. The dimension of the standard IC was also reduced from 5µm to 3µm

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Role of different elements in ALSTTL

1) Speed improvements:The major modification was in the input part of the circuit.The diode D2 provide a low impedance Path to ground for removal of storedcharge from the base of Q3, when input makes a high to low transition.

This enhances the inverter switching time.

In addition, Q2 increases the internal current drive by providing basedriving current to Q3.

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Role of different elements in ALSTTL (cont.)

2) Input section:

The input diodes of the ALSTTL circuit are replaced with emitter follower pnptransistor.

The emitter follower configuration reduces load current by a factor ¼, and thus increases the fanout. In addition, the emitter base junction of the Q1 compensates for additional base emitter drop of Q2.

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Role of different elements in ALSTTL (cont.)

• The diode D3 allows the base of Q7 to discharge through Q3 when the output switches high to low and provides more rapid discharging of the load capacitance.

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Role of different elements in ALSTTL (cont.)

• Output clamping diodes:• The diode D4 has been

added to the output and provides the same function as the input clamping diode D1. That is, D4 prevents the output from overshooting ground (when logic 1 switch to logic 0)by more than a turn on voltage (0.3V).

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Operation of the ALSTTL circuit• Case I: when VX=0.4VUnder this biased condition the E-B

junction of Q1 is forward biased and in active mode, and consequently the VE1 of Q1 is given by,

VE1 = Vx + VBE = 0.4 + 0.7= 1.1 VAll the other transistor (Q2-Q5) are in cut

off mode (Why? ) VO=high

Case II: When VX=3.6VThe Q1 is cutoff and Q2, Q3, and Q5 turn

on, the VE1 is given by,VE1= VBE(Q2)+VBE(Q3)+VBE(Q5)VE1 = 0.7(3) = 2.1 VVO=low

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Problem 17.29aGiven that β=50, refer figure 17.35(a)Calculate power dissipation in the circuit

when the input is at logic zero.(b) When the input is at logic 1

Sol: For TTL circuit for low logic VX = 0.4V and for high logic Vx=3.6V

VE1 = Vx + VBE(Q1) = 0.4 + 0.7 = 1.1V

iE1 = (VCC - VE1)/R1 = (5-1.1)/40 = 0.0975mA. This is the total current flowing through the circuit because all other transistors are in cutoff mode.

P = iE1 . VCC= (0.0975)(5) = 0.487mW78

Problem 17.29bb) When the input is at logic 1b) : VE1= VBE(Q2)+VBE(Q3)+VBE(Q5)=(0.7)(3)=2.1V

iR1=(VCC-VB1)/R1 =(5-2.1)/40 =0.0725mA

VC2=VCE(Q2)+VBE(Q3)+VBE(Q5)=0.4+0.7+0.7=1.8V

IR2=(VCC-VC2)/R2=(5.1.8)/R2 =0.065mA

VC3= VCE(Q3)+VBE(Q5)=0.4+0.7=1.1V

IR3= (VCC-VC3)/R3=(5-1.1)/1.5=0.26mA

P=VCC(IR1+iR2+iR3)=1.98mW

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Introduction of BiCMOS Digital Circuits

• BiCMOS is a VLSI technology that combines bipolar and CMOS devices into single integrated circuit.

• By combining the two technologies BiCMOS offers the following advantage:

• i) Low power dissipation comparable to CMOS • ii) Improved speed comparable to TTL or ECL technology • iii) Large current driving capability comparable to TTL or ECL• iv) large noise margin similar to TTL technologyDisadvantage:i) Highest costii) Large fabrication cycle time up to thirty mask steps are

common compared with ten to twenty for bipolar or CMOS.

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BiCMOS Inverter (when input is low)

• Case I: When VI=logic 0

The MN and Q2 are off while Mp conducts, which forces Q1 on. The Q1 then provide a large output current to charge the load capacitance. The result is very short low-to-high propagation delay time. Q1 is essentially acts as a pull up transistor and

V0(max)=VDD-VBE1(on),

because Q1 turn off when Vo reaches to this value, a disadvantage.

2

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BiCMOS Inverter (when input is high)

• Case II: when VI = logic 1

Mp goes off, MN and Q2 turn on. The transistor Q2 provide large output current that quickly discharge the load capacitor, which result a short high to low propagation delay time. The output voltage continue to decrease until

VO(min)=VBE2(on)Q2,

because Q2 turn off at this value. Thus low voltage is greater than 0, a disadvantage.

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Improved version of BiCMOS inverter

• One serious disadvantage of the previous circuit we discussed is that the absence of circuit path through which base charge can be removed from the npn transistors (Q1 and Q2), when they are turn off.

• The solution of this problem is addition of pull down resistors (R1 and R2) as shown in the figure.

• Resistor R2 provides an additional benefit:When VI high and after Q2 cuts off, Vo continue to fall below VBE2 (on) because a small current through MN and R2 continue to flow , which pulled the output to ground potential.

• Similarly, when output goes high, a very small current through Mp and R1 pulled up the output to VDD.

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