1:- Design All logical Gates Using VHDL.

VHDL PROGARM FOR OR GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR AND GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR NOT GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR NAND GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR NOR GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR XOR GATE

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR XNOR GATE

Sample WaveForm Output:-

Akash Gera

2:- VHDL Programs For the following and check the Simulation

1) Half Adder2) Full Adder.

VHDL PROGARM FOR HALF ADDER

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR FULL ADDER

LIBRARY IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder is

port( a, b, cin : in STD_LOGIC;

sum, cout : out STD_LOGIC );

end fulladder;

architecture Behavioral of fulladder is

signal s1,s2,s3: STD_ULOGIC;

constant gate_delay: Time :=100 ps;

begin

s1<=(a xor b) after gate_delay;

s2<=(cin and s1) after gate_delay;

s3<=(a and b) after gate_delay;

sum<=(s1 xor cin) after gate_delay;

cout<=(s2 or s3) after gate_delay;

end Behavioral;

Sample WaveForm Output:-

Akash Gera

3:- VHDL Programs For the following and check the Simulation

1. Multiplexer2. Demultiplexer

VHDL PROGARM FOR MULTIPLEXER(4 X 1)

Sample WaveForm Output:-

Akash Gera

VHDL PROGARM FOR DEMULTIPLEXER(2 X4)

Sample WaveForm Output:-

Akash Gera

4:- VHDL Program For a Comparator and check the Simulation

Sample WaveForm Output:-

Akash Gera

5:- VHDL Program For a Code Converter and check the Simulation

Sample WaveForm Output:-

Akash Gera

6:- VHDL Program For a JK flip flop and check the Simulation

Sample WaveForm Output:-

Akash Gera

7:- VHDL Program For a Counter and check the Simulation

Sample WaveForm Output:-

Akash Gera