Digital Processing Unit 1/15

PACS IHDR 12/13 Nov 2003

DPU PRESENTATION

R.Orfei & S. PezzutoCNR- IFSI

Digital Processing Unit 2/15

PACS IHDR 12/13 Nov 2003

FUNDING AND DELIVERY CRITICALITY

• FACT: IFSI has got no funds from ASI after 2001, that has prevented attendance at meetings, reviews, support during integrations……

• FACT: the ASI-Carlo Gavazzi Space contract has been extended up to 31/01/2004

• PREDICTION: from now up to 31/01/2004 a new contract/addendum will be issued taking into account the PD#4 items (e.g. the SW reset of the IEEE-1355 chip); the new contract/addendum will expire at the end of 2004

• FACT: the lack of funds, the stop of CGS activities (waiting for the PD#4 ASI approval) and the present HW problems have driven a very critical DPU/ICU Herschel schedule

Digital Processing Unit 3/15

PACS IHDR 12/13 Nov 2003

Design status (1/2)- During the AVM tests a random loss of the 1355 links has been

detected and investigations are in progress to identify the source of the problem

- At present the IFSI unit is at CGS to carry out the investigation

- The analysis (thanks also to CSL, IAC and MPE for their help!) has shown that consecutive addressing of the STD-1553 Dual Port RAM and of the IEEE-1355 Dual Port RAM causes the loss of the 1355 links. The HW is now suspect.

- The design of the HW boards (contracted to Carlo Gavazzi Space) will be corrected in EQM and FM to include the necessary modifications resulting from the fixing of the above problem

Digital Processing Unit 4/15

PACS IHDR 12/13 Nov 2003

DESIGN STATUS (2/2)

AVM SW nearly completed; missing items:

• new OBCP and autonomy function (to be implemented when available)

• patching• uploading of OBCP implemented but not tested• other types of patching not addressed• Burst mode implemented but not thoroughly tested• upgrading of the VIRTUOSO O.S.: waiting for an offer from

WIND RIVER• New OBS image uploadable with the BOOT SW

Digital Processing Unit 5/15

PACS IHDR 12/13 Nov 2003

SW DOCUMENTATION

• SSD: is in progress, issue 1 should be available by the end of November (SW requirements inserted, logical model and architecture design revised)

• DDD: a new issue will be ready after the SW is stabilized

• SVVP: a new issue was circulated according to S. Thurey’s comments. Some comments require a new document layout and a new release will be issued asap in line with IFSI manpower

Digital Processing Unit 6/15

PACS IHDR 12/13 Nov 2003

BUDGETS FOR FM (1/2)(ACTUAL MASS INFERRED FROM AVM BOARDS)

• Box weight (mechanics): 3037 g CPU Boards (2 of): 960 g I/F Boards (2 of): 640 g DC/DC Boards (2 of) (E): 1000 g Motherboard: 520 g Screws etc.: 100 g Cabling (E): 300 g

Conformal coating (E): 420 g

TOTAL (E) 6977 g (+-200 g)

Digital Processing Unit 7/15

PACS IHDR 12/13 Nov 2003

BOX INTERFACE CONTROL DRAWING

Digital Processing Unit 8/15

PACS IHDR 12/13 Nov 2003

BUDGETS FOR FM (2/2)

TOTAL ESTIMATED POWER (DC/DC CONVERTER EFFICIENCY = 70%): 14.6 W

I W I W I W I W

CPU BOARD ONLY - DATA MEMORY (DM) TEST 1,050 5,250 0,015 0,038 0,000 0,000 0,000 0,000 5,288

MB + CPU + I/F - STAND BY 1,150 5,750 0,030 0,075 0,010 0,150 0,090 1,350 7,325

MB + CPU + I/F - DATA MEMORY TEST 1,400 7,000 0,030 0,075 0,010 0,150 0,090 1,350 8,575

MB + CPU + I/F - DM TEST + FSDL (EMPTY) FIFO READ 1,500 7,500 0,030 0,075 0,010 0,150 0,090 1,350 9,075

MB + CPU + I/F - DM TEST + 1553 TRANSMISSION 1,250 6,250 0,030 0,075 0,010 0,150 0,250 3,750 10,225

PRELIMINARY-DPU-AVM POWER CONSUMPTION

MEASUREMENT CONFIGURATION/DESCRIPTIONTOTAL

(W)

+5V SUPPLY +2,5V SUPPLY +15V SUPPLY -15V SUPPLY5 2,5 15 15

Digital Processing Unit 9/15

PACS IHDR 12/13 Nov 2003

CPU BOARD

DSP 21020

RAM

FPGA

EPROM

20 MHz

IEEE-1355

MEZZANINE

JTAG

Digital Processing Unit 10/15

PACS IHDR 12/13 Nov 2003

I/F BOARD

FIFOS

FIFOS

S/S I/Fs A/D Conv.

16 MHz

1553B (S/C I/F)

Long Stub Trafos“A” and “B”FPGA

NOT FOR PACS

Digital Processing Unit 11/15

PACS IHDR 12/13 Nov 2003

DPU

Digital Processing Unit 12/15

PACS IHDR 12/13 Nov 2003

Assembly withcabling andconnectors

Boards fromcontractor

S/C SimulatorS/S Simulators

(IFSI)

Preliminary inhouse testsHW & LowLevel SW

Transfer LayerProtocol

EGSE (PACS)S/S Simulators

(IFSI)

Assemblywith

mechanics

Environmentaltests

Delivery toPACS

Full Integrationtests: HW &

SW

EGSES/S (OR S/SSimulators)

(PACS)

Tests commonto the wholeinstrument

AIV FLOW

Digital Processing Unit 13/15

PACS IHDR 12/13 Nov 2003

EQM SCHEDULE (TENTATIVE)

ID Task Name Duration Start Finish

193 PACS EQM 134,7 wks Wed 06/02/02 Mon 06/09/04

194 ASI PD #4 approval (NEW CONTRACT) 1 day Fri 28/11/03 Fri 28/11/03

195 Boards Manufacturing & Testing 20 days Fri 23/04/04 Thu 20/05/04

196 PACS EQM Acceptance Tests at CGS 0,8 wks Fri 21/05/04 Wed 26/05/04

197 Electrical Tests 1 day Fri 21/05/04 Fri 21/05/04

198 S/C I/F Signals 0,2 wks Mon 24/05/04 Mon 24/05/04

199 S/S I/F Signals 1 day Tue 25/05/04 Tue 25/05/04

200 SW Tests 1 day Wed 26/05/04 Wed 26/05/04

201 CPU+I/F+DC/DC + MB Boards at IFSI 1 day Thu 27/05/04 Thu 27/05/04

202 Mechanical mfg 4 wks Wed 06/02/02 Tue 05/03/02

203 Cabling 18 days Fri 28/05/04 Tue 22/06/04

204 DPU-OBS Integration 4 wks Wed 23/06/04 Tue 20/07/04

205 S/W Review 2 days Wed 30/06/04 Thu 01/07/04

206 Box Assembly 1 day Wed 21/07/04 Wed 21/07/04

207 TRRB 1 day Thu 22/07/04 Thu 22/07/04

208 Envir. Tests 5 wks Fri 23/07/04 Thu 26/08/04

209 DRB 0,2 wks Wed 18/08/04 Wed 18/08/04

210 PACS EQM Delivery to MPE 1,3 wks Fri 27/08/04 Mon 06/09/04

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

27/05

A. Pavoni

S.Pezzuto

S. Pezzuto;R. Cerulli;S. Molinari

A. Morbidini;P. Baldetti

22/07

R. Orfei[80%];R. Cerulli[20%];S. P

18/08

27/08

Apr May Jun Jul Aug Sep Oct Nov Dec

Digital Processing Unit 14/15

PACS IHDR 12/13 Nov 2003

FM SCHEDULE (TENTATIVE)

ID Task Name Duration Start Finish

212 PACS FM 142,8 wks Wed 06/03/02 Mon 29/11/04

213 ATP (FOR MANUFACTURING CONTINUITY) 1 day Mon 02/02/04 Mon 02/02/04

214 Mechanical mfg 4 wks Wed 06/03/02 Tue 02/04/02

215 Boards Manufacturing & Testing 21 days Mon 19/07/04 Mon 16/08/04

216 Burn of Flight PROMs 2 wks Tue 03/08/04 Mon 16/08/04

217 Electrical Tests 1 day Tue 17/08/04 Tue 17/08/04

218 S/C I/F Signals 1 day Wed 18/08/04 Wed 18/08/04

219 S/S I/F Signals 1 day Thu 19/08/04 Thu 19/08/04

220 SW Tests 1 day Fri 20/08/04 Fri 20/08/04

221 CPU+I/F+DC/DC Conv. MB Boards at IFSI 1 day Mon 23/08/04 Mon 23/08/04

222 Cabling 18 days Tue 24/08/04 Thu 16/09/04

223 DPU-OBS Integration 4 wks Fri 17/09/04 Thu 14/10/04

224 Box Assembly 1 day Fri 15/10/04 Fri 15/10/04

225 TRRB 0,2 wks Mon 18/10/04 Mon 18/10/04

226 Envir. Tests 5 wks Tue 19/10/04 Mon 22/11/04

227 DRB 1 day Fri 12/11/04 Fri 12/11/04

228 PACS FM Delivery to MPE 1 wk Tue 23/11/04 Mon 29/11/04

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

R. Orfei;R. Cerulli

23/08

A. Pavoni

S.Pezzuto[80%];R. Cerulli[10%];S. Molinari[10%]

A. Morbidini;P. Baldetti

18/10

R. Orfei[80%];R. Cerulli[20%];S. Pezzuto[2

12/11

23/11

Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr2005

Digital Processing Unit 15/15

PACS IHDR 12/13 Nov 2003

PA/QA ACTIVITIES

• ALL COMPONENTS ARE BOUGHT THROUGH THE CO-ORDINATED PARTS

PROCUREMENT AGENCY

• FOR INDUCTORS AND TRANSFORMERS RELEVANT RFAs AND PADs ISSUED

• NO RE-FLOW SOLDERING IS FORESEEN: ALL HAND MADE SOLDERS (INCLUDING

SMD) BY ESA QUALIFIED PERSONNEL

• ENVIRONMENTAL QUALIFICATION TESTS ARE SCHEDULED FOR QM UNITS (A

REDUCTION SET OF TESTS, ON THE GROUNDS OF SIMILARITY, IS UNDER

EVALUATION)

• ENVIRONMENTAL ACCEPTANCE TESTS ARE SCHEDULED FOR FM UNITS (A

REDUCTION SET OF TESTS, ON THE GROUNDS OF SIMILARITY, IS UNDER

EVALUATION)