Discrete FET - PHEMT Devices

FiltronicSolid State

Applications NotesDiscrete FET / PHEMT Devices

Revision AAugust 1996


Discrete FET / PHEMT Applications Notes 2

INTRODUCTION

These applications notes describe Filtronic Solid State (FSS) discrete FET /PHEMT devices and typical applications, effective August 1, 1996. Although every efforthas been made to ensure the accuracy of this information (contained in theseApplications Notes and the associated Datasheets), FSS assumes no responsibility forerrors, omissions, or future specifications changes. Every reasonable effort will be madeto provide updated or corrected applications information or specification changes to allconcerned users.

Filtronic Solid State discrete FET / PHEMT devices are generally sold bydescription only. RF specifications, in particular, are based on samples of devices fromindividual semiconductor wafers or fabrication lots (groups of 6-10 wafers). Allsemiconductor die are 100% DC tested, based on specific test conditions and methodsas described herein. Test methods are based on MIL-STD-750, with modifications wherenecessary. Unless otherwise indicated, all specifications listed as minimum or asmaximum are guaranteed at the temperatures indicated (nominally at 22ΕC) and underthe conditions listed. “Typical” specifications are based on average values, intended toreflect the majority of actual devices manufactured, but are not guaranteed.

Filtronic Solid State assumes no responsibility for performance or reliability of itsdiscrete devices when operated outside the recommended electrical or environmentallimits, or if operated in such a way as to exceed the Absolute Maximum Ratings asindicated on specific Datasheets. Applications information is intended as generalguidance only, and FSS is not responsible for user-provided circuitry.



TABLE OF CONTENTS

Section Page

1.Introduction.........................................................................................................................22.Quick Reference Guide......................................................................................................43.Cross-Reference Guide .....................................................................................................54.General Device Description................................................................................................65.PHEMT Device Physics .....................................................................................................86.PHEMT Characteristics......................................................................................................117.Small-Signal S-Parameters and Lumped Element Models ................................................208.Biasing Circuits and Stabilization Techniques....................................................................239.Large-Signal Models and Optimum Power Match Data .....................................................2610.Example Circuits ..............................................................................................................2911.Recommended Assembly Techniques.............................................................................3912.Parametric Screening and Quality Assurance..................................................................4013.Discrete Device Uniformity...............................................................................................4614.Device Reliability ..............................................................................................................4815.Appendix A .......................................................................................................................49



2. Quick Reference Guide

Discrete GaAs MESFET and PHEMT Product Family

MODEL STATUSFREQ.RANGE(GHz)

GAIN(dB)

POWER(dBm)

NOISEFIGURE

(dB)VDS

(V)IDSS

(mA)PAE(%)

CHIPDIM.(µm)

GATEW/L(µm)

TYPE

LF 3807 (1) 1 - 12 7 24 --- 7 200 40 430x460 700/.5 MES

LF 3814 STD 1 - 12 6 27 --- 7 400 40 430x460 1400/.5 MES

LF 3830 STD 1 - 8 7 31.5 --- 9 700 36 340x930 3000/.5 MES

LF 3850 STD 1 - 8 7 33.5 --- 9 1100 38 380x900 5000/.5 MES

LF 6828 STD 1 - 18 7 19 --- 5.5 80 26 310x440 280/.5 MES

LF 6836 STD 1 - 18 6.5 21 --- 5.5 120 27 330x350 360/.5 MES

LF 6872 STD 1 - 18 6 24 --- 5.5 230 26 370x500 720/.5 MES

LP 7512 STD 1 - 40 8.52 --- 1.0 2 35 --- 330x460 200/.25 SHP

LP 7612 STD 1 - 40 9.53 21 1.14 5 55 50 330x460 200/.25 DHP

LP 6836 PRT 1 - 30 9.53 24 --- 8 100 45 330x350 360/.25 DHP

LP 6872 STD 1 - 26 9.53 27 --- 8 220 45 370x500 720/.25 DHP

LP 1500 ED5 1 - 20 9.03 30.5 --- 8 465 48 340x800 1500/.25 DHP

LP 1800 ED5 1 - 20 9.03 31.0 --- 8 560 48 340x820 1800/.25 DHP

LP 3000 ED5 1 - 20 8.53 33.5 --- 8 930 45 340x850 3000/.25 DHP

LP 5000 ED5 1 - 20 8.53 36.0 --- 8 1550 45 340x860 5000/.25 DHP

LEGEND:

STD STANDARD PRODUCTOBS OBSOLETE; MODEL DISCONTINUED.PRT PROTOTYPE; APPLICATION DEVELOPMENT SAMPLES AVAILABLEED ENGINEERING DEVELOPMENT; PROTOTYPE DEVICES AVAILABLE AS INDICATEDMES Standard GaAs MESFETSHP SINGLE HETEROJUNCTION PHEMTDHP DOUBLE HETEROJUNCTION PHEMT

NOTES:

1). LF 3807 to be discontinued 10/96. One-half of the LF 3814 can be used as a replacement.

2). Associated Gain at Optimum Noise Figure, measured at 18 GHz.

3). Power Gain at 1dB Gain Compression, device tuned for optimum power at 18 GHz.

4). Low-noise bias, measured at 18 GHz.

5). Prototype devices available 10/96.

FREQ. RANGE is the recommended range based on the device’s available gain.



3. Cross-Reference Guide

This guide is based on general performance parameters; optimum circuit performance may require re-design, since the FSS device S-parameters maydiffer significantly from other manufacturers’ devices as listed below. Contact the Foundry for additional information.

NEC

NE24200, 32400 LP 7512 NE24200, 67300 LP 7612, 7512HI-REL

NE710000NE720000NE760000NE761000

LP 7612 NE800100NE800200NE800400

LF 3814LF 3830LF 3850

NE900000NE900100NE900200NE900400

LP 7612LP 6836LP 6872LP 1800

MWT (Microwave Technology)

MWT-1, A1MWT-2MWT-3, A3MWT-4MWT-6MWT-7, A7, S7MWT-8, A8MWT-9, A9

LP 7612LP 6836LP 7612LP 7612LP 6872, LF 3814LP 7612LP 1500, LP 6872LP 6872

MWT-10MWT-11, A11MWT-12MWT-13MWT-14MWT-15MWT-16

LP 7512LP 1500LP 6872, LF 3814LP 6872, LF 3814LF 3850LP 6836, LP 6872LP 6872

FUJITSU

FHX04X - FHX06XFHR02X, FHR10XFSC10X, FSC11XFSX02X, FSX03XFSX51X, FSX52X

LP 7512 FSC11XFSC51X

LF 6828

FSX52X LP 6836 FLX252XV LP 3000

FLC081XPFLC151XPFLC301XP

LP 6872, LF 3830LP 1800, LF 3850LP 5000

FLK012XPFLK022XP/XVFLK052XP/XVFLK102XP/XVFLK202XV

LP 7612LP 6836LP 6872LP 1500LP 3000

FLR024XP/XVFLR054XVFLR104XV

LP 6836LP 6872LP 1500

FLR016XP/XVFLR026XP/XVFLR056XV

LP 7612LP 6836LP 6872



4. GENERAL DEVICE DESCRIPTION

Filtronic Solid State offers discrete devices thatcan be classified into three categories: GaAs MESFETs,Single Heterojunction Pseudomorphic High ElectronMobility Transistors (SH-PHEMTs), and DoubleHeterojunction Pseudomorphic High Electron Mobility

Transistors (DH-PHEMTs). The latter two device typesfeature AlGaAs/InGaAs heterojunctions, with GaAsbuffer and cap layers. Notional cross-sections areshown below:

AuGe / Ni / Au Alloyed Contacts

N+ GaAs Active Layer

N- Buffer Layer

DrainContact

SourceContact

Ti / Pt / Au Recessed Gate

N++ Contact Layer

AlGaAs / GaAs Superlattice

Undoped GaAs Buffer

InGaAs Channel Layer

N+ AlGaAs Layer (5 x 1017 cm-3)N++ GaAs Contact Layer

DrainContact

SourceContact

Ti / Pt / Au Mushroom Gate

GaAs MESFET STRUCTURE

PHEMT STRUCTURE

Undoped AlGaAs Spacer

Heterojunction

X

Y

Z

Both major device types, the MESFET and thePHEMT, share several common features, beginning withthe gate structure. This is a standard Pt / Ti / Au layeredstructure, which forms a Schottky contact to thesemiconductor; general properties of this type of contactcan be found in numerous references, such as in Sze1.The nominal gate length for FSS’s MESFET is 0.5 µm,and 0.25 µm for the PHEMT devices. Gate definition isaccomplished by Electron-Beam direct-write techniques,using a Cambridge E-Beam system; all other patterningis done with standard contact photolithographytechniques. In both device types, a gate recess channelis etched into the semiconductor prior to gatemetallization, to reduce parasitic gate-source resistance,as well as optimizing the device’s reverse breakdownvoltage. Note that the gate and gate recess channel arealso offset towards the source contact. The MESFETgate structure is trapezoidal in cross-section, beingsomewhat wider at the bottom than at the top. ThePHEMT gates are mushroom structures, therebyreducing gate metal resistance that would result from thenarrower 0.25 µm base.

Drain and source contacts are alloyedAuGe/Ni/Au contacts, with overplated Au for bond pads.The Ge in the contact metal is driven into semiconductorduring the alloy process, where it acts as an amphotericdopant, thereby reducing the contact barrier height andforming the ohmic contact itself. The AuGe/Ni/Au hasbeen established as a very stable and robust contact

structure. All discrete devices are passivated with siliconnitride (Si3N4), which doubles as scratch protection.

Nominal die thickness is 100 µm, or 75 µm forpower devices (≥ 1W). The larger power devicesgenerally include plated via-holes through the die tominimize parasitic source inductance. The vias aredefined by Reactive Ion Etching (RIE) techniques, amethod also employed on FSS’s MMIC products.

All semiconductor structures are grown byMolecular Beam Epitaxy (MBE), which providescompositional control to a precision of a few atomicmonolayers, and very stable and repeatable doping levelcontrol. FSS has utilized MBE technology for a widevariety of device structures for more than 15 years.Basic material parameters are routinely characterized,such as: doping level, carrier mobility (both at roomtemperature and at 77°K), sheet charge density (forPHEMT devices), and wafer uniformity.

1. S. M. Sze, Physics of Semiconductor Devices, Wiley,New York, 1981, pp. 245-297.



5. PHEMT DEVICE PHYSICS

The basic High Electron Mobility Transistor(HEMT) structure is described in many references, and areview of this device’s salient features is included herefor completeness. Sze1 provides a basic introduction toheterojunction energy band structures, and a verycomplete review of HEMT technology can be found inTransactions on Electron Devices.2

Consideration of the basic lumped elementintrinsic MESFET model (see Sec. 7 and Liechti3) and itsconnection to the underlying device structure shows thatthere are several factors that ultimately limit high-frequency response. The unilateral gain is given by:

GffU ≈ max

2

2

where GU = unilateral gain, f = frequency, and fmax = themaximum frequency of oscillation. The gain decreasesat 6 dB/octave until f = fmax, where the unilateral gainbecomes unity. This fmax is approximately given by:

ff

r fT

io T DG

max ≈′ +2 τ

where r’io = input-to-output resistance ratio, τDG =2πRGCDG, the drain-to-gate RC time constant, and fT =the unity current gain, defined as:

fgCT

m

GS

≡1

2πwhere gm = intrinsic device transconductance, and CGS =gate-source capacitance. The frequency fT is defined asthat frequency at which the current through CGS (iC =2πf CGSVC ) is equal to the that produced by the current

generator (iG= gmVC, where VC is the voltagedeveloped across the capacitor CGS). At frequenciesabove fT , the current through CGS is greater than thatprovided by the current generator, and thus fT representsa fundamental high-frequency limit. Combiningexpressions for the transconductance and the gate-source capacitance:

CZ Lh

gv Z

hGSS G

msat S≅ ≅ε ε

where εS = semiconductor dielectric constant, Z = gatewidth, LG = gate length, vsat = saturated carrier velocity,and h = depletion layer depth. The result becomes:

fv

LTsat

G

≈2π

Fundamentally the high-frequency performanceis optimized by reduction of the device’s gate length,along with maximizing the saturated carrier velocity. Inaddition, the extrinsic resistances RG and RS must beminimized, as well as feedback elements such as CDG.

While gate length is limited by thephotolithography technology, the carrier velocity can beenhanced by use of alternative materials, i.e., GaAsinstead of Si, or by use of a two-dimensional electron gas(2DEG) transistor. This latter device incorporates aheterojunction, which is a junction of two differentsemiconductors. One particular heterojunction ofinterest in this case is a Al0.3Ga0.7As/GaAs N+/P-combination, which results in a energy band diagram asshow:

Gate Metal N+ Doped AlGaAs Undoped P- GaAsUndopedAlGaAsSpacer

FermiLevel

Heterojunction 2-D Electron Gas

ConductionBand

X

Y

ZHEMT ENERGY BAND DIAGRAM



Since the Al0.3Ga0.7As and GaAs have differentbandgap energies, their conduction band levels will notline up, resulting in a discontinuity as shown. A thinelectron inversion layer is formed on the GaAs side ofthe heterojunction, populated by carriers that havecrossed over from the doped Al0.3Ga0.7As side; a verythin “spacer” layer further separates the electron layerfrom effect of ionized dopant impurities. This electroninversion layer has been termed a “two-dimensionalelectron gas” since there may be, under certainconditions, quantization of the allowed energy levels.Fairly accurate prediction of the inversion layer sheetcharge density results from the appropriate quantummechanical treatment. Also note that, by design, theAl0.3Ga0.7 As layer thickness and doping level are chosento ensure that, at zero applied gate bias, this layer is fullydepleted of mobile carriers. Therefore the only mobilecharge carriers reside in the 2D electron gas layer.

The structure is designed to achieve a 2Delectron gas sheet charge density that is as high aspossible, typically 1.0-2.5 x 1012 cm-2, since thisdetermines the IDSS per unit gate width for the device.Application of a bias voltage to the drain terminal, withthe source grounded, causes current flow in the X-axisdirection. Control of the 2D electron layer is byapplication of the gate voltage, since the sheet charge

density is directly related to the electric field appliedacross the heterojunction.

This heterostructure, used in place of standardMESFET structure, came to be known by various names,e.g., MODFET, TEGFET, and HEMT, for High ElectronMobility Transistor. An approximate expression for thetransconductance is given by:

gZ vd dm

S sat≅+

ε∆

where d + ∆d = total Al0.3Ga0.7As layer thickness(including spacer). While this has the same functionalform as with the MESFET, higher gm is achieved atmuch lower values of drain voltage, since the greatermobility in the undoped GaAs results in lower “knee”voltages (i.e., the onset of velocity saturation). Inaddition, the layer thickness is substantially less than aMESFET’s depletion layer thickness. The goal withHEMT design is to optimize the heterostructure in orderto maximize low-field carrier mobility, saturation velocity,extrinsic transconductance, and to minimize the inputcapacitance CGS.

The Pseudomorphic HEMT structure utilizes adifferent combination of semiconductors, as shown in thefigure below:

Gate Metal N+ Doped AlGaAs Undoped P- GaAs

UndopedAlGaAsSpacer

2-D Electron Gas

Undoped InGaAs

PSEUDOMORPHIC HEMTENERGY BAND DIAGRAM



This structure features a AlGaAs/InGaAsheterojunction, rather than the AlGaAs/GaAscombination used for the HEMT device. The relativecompositional ratio of gallium and indium is varied toestablish the desired conduction band discontinuity, butthere are material-related limits that must be considered.One important factor is that AlGaAs and InGaAs are notlattice-matched, i.e., the interatomic lattice spacing isdifferent. Thus a grown heterojunction using thiscombination will contain a certain amount of strain, whichultimately limits the thickness of the InGaAs layer.Because the two semiconductors are not lattice-matched, the structure is referred to as a“pseudomorphic” HEMT device.

The use of InGaAs provides for even highermobility and saturated carrier velocity, along withimproved 2-D electron gas confinement; in addition, bysuitable modification of the basic PHEMT structure, thesecond heterojunction can be utilized for an addition 2-Delectron gas layer parallel to the first. Typically this isdone by using another AlGaAs layer below the InGaAschannel layer. FSS’s PHEMT technology features bothtypes of PHEMT structures, as mentioned earlier; theDH-PHEMT structure gives much larger IDSS per unitgate width, and therefore much improved power density.The various device structures and their materials-related

performance parameters are summarized in theMaterials-Related Performance Parameters Table below.

Note first the improvement in low-field mobilityresulting from the use of a 2-D electron gas in the HEMTand PHEMT devices; there are also dramatic increasesin extrinsic transconductance and high-frequencyperformance as well. The last two entries representtypical FSS performance from the SH- and DH-PHEMTstructures. Also note the substantial improvement ineffective carrier velocity resulting from the use of InGaAsvs. GaAs, which directly translates into higher cut-offfrequency fT.

References:

1). S. M. Sze, op. cit., pp. 122-129.

2). Morkoc, H. and Abe, M., ed., “Special Issue onHeterojunction Field-Effect Transistors”, IEEE Trans.Elec. Devices, Vol. ED-33, No. 5, May 1986.

3). Liechti, C. A., “Microwave Field-Effect Transistors -1976”, IEEE Trans. Microwave Theory and Tech., Vol.MTT-24, No. 6, June 1976, pp. 279-300.

SUMMARY OF MATERIALS-RELATED PERFORMANCE PARAMETERS

DEVICE TYPELG

(µm)HALL MOBILITY

(cm2/V)vsat

(cm/s)IDSS

(mA/mm)gm

(mS/mm)fT

(GHz)fmax

(GHz)

GaAs MESFET 0.50 3000 6.9 x 106 170 250 22 45

HEMT 0.65 6000 N/A 120 280 N/A N/A

HEMT 0.25 6000 6.3 x 106 220 320 40 80

PHEMT 1.00 7000 11.0 x 106 290 310 15 N/A

SH-PHEMT 0.25 7000 7.8 x 106 220 450 55 105

DH-PHEMT 0.25 5000 7.8 x 106 325 450 50 100



6. PHEMT CHARACTERISTICS

Current-Voltage (I-V) Characteristics

Based on the material presented in Section 5, itis clear that the fundamental charge transport andcurrent control mechanisms in the PHEMT device differssignificantly from the classical GaAs MESFET, and whilethere are many similarities between the devicesextrinsically, there are also several important differences.The first of these lies in the basic I-V curves, and in thederived transconductance (GM) and Drain-Source current(IDS) vs. Gate voltage characteristics. Typical examplesof these are given below for the LP 7612 device, which isa 0.25 x 200 µm discrete DHPHEMT. Note the low“knee” voltage, at about VDS = 0.5V, representing thetransition from the linear to the saturated region. One ofthe most striking aspects is the large value of Drain-Source current attained with positive gate bias; for theDHPHEMT device, this maximum Drain-Source current,denoted IDSSM, can be as much as 75 to 100% aboveIDSS. In contrast, the MESFET might show 20-25% morecurrent under the same forward gate bias. With bothdevices, the amount of forward gate bias that can be

applied is limited to +0.7 to +0.8V, since larger values willdrive the Gate into forward conduction. This PHEMTphenomenon has a number of implications for circuitdesigners.

The transconductance vs. VGS curve shows apronounced peak at about 80% of VP, the pinchoffvoltage, where the current is effectively reduced to zero.The maximum extrinsic Gm value is approximately 385mS/mm, corresponding to an intrinsic transconductanceof about 500 mS/mm. For optimum small-signal gain, anoperating point of 70-80% of IDSS is recommended.

Because the device’s I-V curves show symmetryabout the VGS = 0V curve (i.e., IDSS), the standardguidelines for Class A, AB, and C operation are differentthan for the MESFET. It is generally accepted that fortrue Class A operation, i.e., no distortion of the amplifiedsignal, a quiescent operating point of IDS = 50% IDSS isthe correct choice. This is based on consideration of theMESFET’s I-V curves and the derived GM vs. gatevoltage characteristic. Notional examples of these areshown on the following page.

TYPICAL PHEMT I-V CHARACTERISTICS I DS AND GM VS. GATE VOLTAGE

LP7612 LP7612

DRAIN VOLTAGE (V) GATE VOLTAGE (V)

DR

AIN

CU

RR

EN

T (

mA

)

DR

AIN

CU

RR

EN

T (

mA

)

Gate VoltageStart .8VStop -1.2Step -.2 V

GM

(m

S)

150

120

90

60

30

0

150

120

90

60

30

0

150

120

90

60

30

00 1.2 2.4 3.6 4.8 6 .8 .4 0 -.4 -.8 -1.2



Class A operation requires, in the ideal case, adistortionless amplification of the input signal, and for asinusoidal waveform, this also requires that no harmonicsignals are generated. The standard for the measure ofmaximum “linear” power is the output power at 1 dB ofgain compression (i.e., 1 dB below the small-signal gain),denoted P1dB. In the case of the notional MESFET I-Vcurves given above, once the input signal drives thedynamic operating point into the gate-drain breakdownregion (located in the lower right-hand corner), signaldistortion can be expected. The load-line shown above isestablished by the output matching circuit, which mustalso resonate out the device’s output admittance. Formaximum output power, the load-line must be chosen tomaximize the peak-to-peak voltage and currentamplitudes, since:

P V IRF P P P P≅ − −1

8

In addition, biasing the device at less than 50% of IDSS

can cause clipping of the output current waveform as theFET is driven beyond pinchoff (i.e., VGS > VP, the pinch-off voltage). Examination of the transconductance vs.gate voltage characteristic also shows that the region ofconstant GM is limited. For optimum linearity, MESFETsare biased at 50% of IDSS, and for larger small-signalgain, bias values of 60-75% are used. Higher power-added efficiency can be achieved at operating points lessthan 50% of IDSS, but with degraded linearity.

Because the PHEMT I-V curves show that IDSSM

is 150-175% of IDSS, it can be anticipated that for Class Aoperation, a quiescent bias point (QP) of 55-75% of IDSS

is the correct choice. This bias point allows for a largecurrent swing while avoiding current cut-off and itsassociated generation of harmonics. The selection ofthe quiescent Drain voltage then becomes a compromisebetween allowing for the largest voltage swing, whileavoiding the Gate-Drain breakdown region.

IDSSM

IDSS

50% QP

VGS = +0.5V

VGS = 0V

VGS = -VP

VDS

IDS

INPUT SIGNALAPPLIED TO GATE

OUTPUT CURRENTDELIVERED TO LOAD

VGS0.0

GM

NOTIONAL MESFETI-V CURVES

MESFET TRANSCONDUCTANCECHARACTERISTIC

GATE-TO-DRAINBREAKDOWN

REGION

LOAD-LINE



Power Linearity andIntermodulation Distortion (IMD)

Because the PHEMT transconductance vs. gatevoltage characteristic shows a peak at 70-80% of IDSS, asopposed to a relatively broad “plateau” of nearly constantGM, it is reasonable to suspect that the inherent linearityof the PHEMT is less than that of the MESFET. As isshown below, however, with a proper choice of thequiescent operating point, the PHEMT linearity andIntermodulation Distortion (IMD) performance isexceptionally good. Regardless of what measure is usedto assess the fundamental linearity, the PHEMT meets orexceeds the “classical” power transfer model.

It is useful to review the classical theory ofnonlinearity in memoryless systems,1 before presentingactual device data. A truly distortion-free two-portsystem will accept any input signal and produce a outputsignal that is a scaled version of the input, with only alinear phase shift. This means that the system transferfunction H(jω) is given by:

( ) ( )H j K j toω ω= −exp

where K and to are constants. For practical two-portsystems with amplification, some non-linearity is ofcourse inherent, but if the deviation from ideal linearity ismild, the two-port can be represented by a power seriesexpansion of the input voltage, as follows:

e k e k e k e

with e A to i i i

i

= + +=

1 22

33

1cosω

where ei = input signal, eo = output signal, A = inputsignal amplitude, ω1 = signal frequency, and k1,2,3 =expansion series coefficients. Expanding the powerseries and combining like terms, the output signalconsists of a DC component, and components at thefundamental, 2nd, and 3rd harmonic frequency. Thefundamental component has an amplitude which is,expressed in log units:

G k k A dBm= +

20341 3

2log

where G = power gain. This is compared to the linearpower gain:

G k dBmo = 20 1log

where Go = linear or small-signal power gain. Note that ifk3 > 0, gain expansion occurs, while if k3 < 0, then thetwo-port exhibits gain compression.

If one now applies a second fundamentalfrequency or tone, the simultaneous two-tone inputproduces output signal components at: DC, ω1, ω2, 2ω1,

2ω2, and 3ω1, 3ω2; there will also now beintermodulation products, i.e., second-order products atω1 ∀ ω2, and third-order products at: 2ω1 ∀ ω2 and 2ω2

∀ ω1. The third-order products are of particular concern,since they fall within the passband of a typical single-octave system, whereas the other terms do not. In asystem with impedance R, the output power of thefundamental in the “linear” region of the power transfercharacteristic will be, in dBm units:

PR

dBmo =

10

2

101

2 3

logk A

Once the two-port begins deviating from linearity, the

term k1 A is replaced by: k A k A19

4 33+ . For all

practical purposes, the two-port can be consideredessentially linear if operated more than 10 dB below the1 dB compression point. The power of the 3rd-orderintermodulation products is given by:

Pk A

RdBm2

3

4 33

23

1 210

2

10ω ω− =

log

Note that the slope of the 3rd-order products increasesat a 3:1 ratio compared to the linear power expression.Thus if the linear output power is extrapolated, it willintersect the 3rd-order product extrapolation, as afunction of input power. This intersection point, the 3rd-order intermodulation “intercept point,” is useful forcharacterizing non-linear systems. This behavior isdepicted in the figure below, along with an idealized two-tone IMD spectrum.

1. Ha, Tri T., Solid-State Microwave Amplifier Design,Wiley, New York, 1981, pp. 203-209.



Using the relationships given above and solvinganalytically for the intercept point yields the expression:

Pkk R

dBmIP =

10

23

1013

3

3

log

Thus the intercept point in this example is independent ofinput power, and from this one also derives the well-known expression:

P P dBmIP dB= +1 10 63.

Another often-used expression relates the 3rd-order IMDproduct power levels to the fundamental power level, asfollows:

P P P dBmIP2 1 2 13 2ω ω ω− ≅ −

3

1

1

1

Input Power (dBm)

OutputPower(dBm)

PIP

3rd-order products

fundamental

FUNDAMENTAL AND 3RD-ORDER IMD PRODUCTPOWER TRANSFER CURVES

ωω1 ω22ω2 - ω12ω1 - ω2

ω1 ω2 ω

INPUT SPECTRUM OUTPUT SPECTRUM



Typical two-tone IMD performance data ispresented below for the LP 7612 and LP 6872 discreteDHPHEMT devices, illustrating the effect of thequiescent OP. This effect is especially pronounced forthe LP 7612, showing quite clearly that the operatingcurrent needs to be greater than 50% of IDSS in order toshow zero gain expansion and optimum IMDperformance. The power linearity was assessed by fourmethods:

1). Examination of the power transfer curve;qualitatively, the presence or absence of gain expansion.

2). Curve-fitting the PIN vs. POUT data to the“classical” theory.

3). Intercept Point determination by graphicalextrapolation.

4). Intercept Point determination by directcalculation, using:

P P P dBmIP2 1 2 13 2ω ω ω− ≅ −

The devices were characterized using the test equipmentconfiguration shown below.

Low-loss triple-sleeve coaxial tuners match theDUT to 50 ohms, which are manually tuned for optimumpower and/or gain. The discrete device is eutecticallydie-attached onto a gold-plated coppergroundbar/heatsink, which in turn is mounted between apair of 50 ohm microstrip lines (on alumina). Bond wiresconnect the DUT’s Gate and Drain to the microstrip lines.Coaxial-to-microstrip launchers complete themeasurement fixturing. The TWT amplifier is operatedmore than 25 dB below its 1dB compression point, anddoes not contribute intermodulation products. Input andoutput losses are corrected up to the coaxial-to-microstrip adapters.

SIGNALGENERATORS

TWTA

TUNER

BIASTEE

POWERMETER

SENSOR

-VG

DUT

TUNER

+VD

POWERMETER

SENSOR

SPECTRUMANALYZER

TEST CONFIGURATION FOR TWO-TONEINTERMODULATION MEASUREMENTS



LP 7612 5V 75% IDSS

-30

-20

-10

0

10

20

30

40

3.3 4.3 4.8 6 6.9 8.1 8.5 9.7 10.7 11.7 12.9 14 14.5 15.7 16.6 17.6 18.6 19.6 20.6 21.6 22.6 23.6

INPUT POWER (dBm )

POUT 1-TONE

POUT EXT

GP

P3rd EXT

P3rd ABS

PINT CALC

This data was taken on a LP 7612 DHPHEMTdiscrete device, as described above, biased at VDS = 5V,IDS = 75% IDSS. The actual data, corrected to a single-tone basis, is shown as the “POUT 1-TONE” and “P3rdABS”. The first is the fundamental tone POUT vs. PIN

data, while the second is the actual (absolute) powerlevel of the 3rd-order IMD products. Note that the actual3rd-order data follows the expected 3:1 slope line, whoseintersection with the linear extrapolation of the small-signal power gain shows a 3rd-order Intercept Point of+35 dBm. The single-tone output power at 1 dB gaincompression, P1dB = +21.5 dBm, with a Power-AddedEfficiency PAE = 47%. Thus the device exceeds the

expected: P1dB + 10.6 dB = +32.1 dBm, and the PAE isconsistent with Class A operation. The calculated PowerGain is shown as “GP” on the plot above, showing nogain expansion or other nonideal behavior prior tocompression. Also shown as “PINT CALC” are thevalues calculated from: P P PIP2 1 2 1

3 2ω ω ω− ≅ − ,

showing constant IP3 values in the linear region, andreasonably good agreement with the graphicaldetermination. Finally, the POUT vs. PIN data fits well tothe power transfer model, with k1 = 3.89, and k3 = -0.422.



LP 7612 5V 50% IDSS

-30

-20

-10

0

10

20

30

40

-0.3 0.8 1.8 2.9 3.6 4.5 5.4 6 7 8.1 9.1 9.7 10.7 11.8 12.9 13.7 14.6 15.2 16.2 17.2 18.2 19.2

INPUT POWER (dBm )

POUT 1-TONE

POUT EXT

GP

P3rd ABS

P3rd EXT

PINT CALC

In the plot shown above, the operating currenthas been reduced to 50% of IDSS; the single-tone P1dB =+22.2 dBm, with a PAE of 59%, which indicates ClassAB operation. Note that the extrapolation method fordetermining IP3 shows a value of +30.5 dBm, somewhatlower than the expected 22.2 + 10.6 = 32.8 dBm. Gainexpansion is seen at input power levels between +5 to

+9 dBm, and the power transfer model fits poorly to theactual data. The table below summarizes the biaseffects on device linearity. The “75D” data shows theeffect of de-tuning the output match to the device by 1dB, to simulate a non-ideal circuit matching environment.There is no discernible effect on linearity.

LP 7612 DHPHEMT IMD PERFORMANCE VS. OPERATING POINTVDS = 5.0V TEST FREQ. = 18 GHz

IDS

(%)P1dB

(dBm)PAE(%)

GainExpansion

Calculated IP3(dBm)

Graphical IP3(dBm)

30 21.7 59 0.3 dB 28-30 35.050 22.2 59 0.8 dB 28.5 30.575 21.5 47 None 35.0 35.0

75D 20.5 38 None 35.0 35.5100 20.7 30 None 28.0 30.0



Similiar data for the LP 6872 device is shown below:

LP 6872 8V 50%IDSS

-20

-10

0

10

20

30

40

50

13.4 14.5 15.5 16.4 17.5 18 19.1 20.3 21.3 21.9 22.9 24 25 26 27 28 29 30 31 32 33 34

INPUT POWER (dBm)

POUT 1-TONE

POUT EXT

GP

P3rd ABS

P3rd EXT

PINT CALC

LP 6872 DHPHEMT IMD PERFORMANCE VS. OPERATING POINTTEST FREQ. = 18 GHz

VDS

(V)IDS

(%)P1dB

(dBm)PAE(%)

GainExpansion

Calculated IP3(dBm)

Graphical IP3(dBm)

8 30 27.9 42 0.1 dB 38-39 388 50 28.3 44 0.2 dB 39-41 437 75 28.2 49 0.1 dB 36-39 428 75 28.2 43 0.3 dB 35-38 408 85 28.3 40 None 41-42 42

The LP 6872 DHPHEMT, nominally P1dB = 27dBm at 18 GHz, exhibits good IMD performance over awider range of bias conditions, but once again optimumlinearity is achieved with a quiescent operating point setat or above 50% IDSS. As a further degree of freedom,

the operating voltage can be adjusted over the 6-9Vrange without significant degradation of device linearity.This may be useful for optimizing the gain and powermatching conditions.



Operating Current “Pulling”:

0

10

20

30

40

50

60

-5 0 5 10 15 20 25

PIN (dBm )

Ids 5v100p

Ids 5v70p

Ids 5v30p

Ids 5v50p

IDS vs. Input Power at V DS = 5VIDSS = 56 mA

mA

The data presented above shows the typicalcurrent “pulling” effect for the LP 7612 DHPHEMTdiscrete device, biased at VDS = 5V, at a test frequencyof 15 GHz. The vertical axis shows the Drain supplyoperating current as a function of input power for 30, 50,70, and 100% of IDSS. For most bias conditions, theoperating current pulls up as the device is driven intosaturation; for the PHEMT this is due to instantaneouscurrent (i.e., RF current) excursions above IDSS, asdiscussed in Sec. 6. This data shows input power levelsequating to 12 dB of gain compression; note the rapiddecrease in current at extreme drive levels, PIN > 18dBm, that indicates the onset of Gate conduction current.

Continuous RF input power levels that result in largevalues of gain compression is not recommended forreliable operation.

Note that for a quiescent operating point (OP) at100% IDSS, the onset of Gate conduction current occursat a slightly lower input power level, and that theoperating current decreases significantly. Anyappreciable amount of Gate current results in a shift ofthe OP due to an ohmic drop of about 75-100 mV due tothe Gate metal resistance, which is about 7Ω for thisdevice, in addition to the circuit’s grounding resistor, ifany.



7. SMALL-SIGNAL S-PARAMETERS AND LUMPED-ELEMENT MODELS

A complete listing of small-signal scatteringparameters for all production-released FSS discreteMESFET and PHEMT devices is available from anauthorized Sales Representative or directly from thefoundry. This DOS-formatted 3.5” diskette contains S-parameters files in the “Touchstone” format, which isdenoted by the suffix “.s2p” on the file names. Thisdiskette also contains several “Readme” text files thatcontain additional measurement-specific information,such as bond wire lengths, etc. The S-parameter filescan be viewed using the MS-DOS Editor, or with MSWindows Notepad (the user will need to “Associate”the file with “Text File [Notepad.exe]”). The S-data filecontains one or two comment lines, followed by a headerline such as:

“# S GHZ MA 50”

This designates: S-parameters, frequency units in GHz,Magnitude-Angle format (or “RI” Real-Imaginary), and 50ohms normalization. The header line is followed by theactual frequency and S-parameter data. TheTouchstone format can be directly imported into standardCAD programs such as HPEEsof Libra or MDS.Note that some files contain a “n” in the filename, suchas “lp76_1n.s2p”, which indicates that bias-dependent

Noise Characterization data is appended to the file, alsoin Touchstone format.

For S-parameter characterization, the discretedevice was eutectically die-attached onto gold-platedmolybdenum carriers (for optimum heatsinking), alongwith two JMicrotechnology Probepoint substrates. Thedevices were then wire-bonded (using 0.0007” or 18 µmgold wire) from the appropriate bond pads to thesubstrates. These substrates accommodate the GGBPicoprobes, which are in a ground-signal-groundconfiguration on a 150 µm pitch. The input and outputreference planes of measurement are therefore up to thebond wires; all S-parameter files contain bond wireeffects, as detailed in the “Readme” files. Actualmeasurements were taken by a Hewlett-Packard 8510CNetwork Analyzer.

Lumped-element small-signal models werecreated by directly fitting to the measured S-parameterdata, by optimization for minimum error between actualand modeled data. The resulting model was thensubjected to verification testing by comparison withknown parameters such as gate resistance and bondwire effects. The basic lumped-element model is asfollows:

I = v Ge

DS C M

- j TDω

1 + jfF

LG RG

CGS

RI

GATE

CDG

CDC

RS

LS

SOURCE

IDS RDS

CDS

RD LD

DRAIN

+_

VC

LUMPED-ELEMENT MODEL



FSS FET AND PHEMT LUMPED ELEMENT MODELS

ELEMENT LF 6836 LF 6872 LF 3814 LF 3830 LF 3850 LP 7512(low/up)

LP 7612(low/up)

LP 6872

LG, nH 0.24 0.14 0.14 0.08 0.06 0.14 0.17/0.20 0.14RG, Ω 10.7 5.3 2.0 1.18 0.20 5.3/6.4 7.0/4.4 1.0CGS, pF 0.58 1.00 1.88 5.17 7.10 0.28/0.27 0.57/0.51 1.49RI, Ω 0.80 0.16 2.79 0.0 0.57 1.50 0.01 1.3CDC, pF 0.02 0.04 0.14 0.09 0.06 0.05/0.04 0.02 0.01GM, mS 90 130 200 470 580 90/100 90/100 230TD, pS 0.03 0.07 0.68 0.01 0.04 0.01 0.04/0.10 0.03F, GHz 41 45 25 25 30 55/55 50/44 41.2RDS, Ω 300 525 76.8 34.0 30.0 228/282 497/598 173CDS, pF 0.05 0.12 0.12 0.49 0.68 0.03 0.06 0.16CDG, pF 0.04 0.09 0.03 0.05 0.35 0.04 0.01 0.04RD, Ω 1.2 0.76 0.09 0.04 0.10 0.10 0.16/1.5 0.20LD, nH 0.19 0.11 0.12 0.09 0.07 0.10 0.16/0.06 0.13RS, Ω 4.2 1.1 1.82 1.60 0.12 2.94/3.26 2.74/3.26 0.96LS, nH 0.02 0.04 0.02 0.04 0.003 0.02/0.03 0.03 0.03VDS, V 5.5 5 7 9 9 2 5 8IDS, % 50 50 50 50 50 25 50 50IDSS, mA 123 240 246 589 712 40 68 240

NOTES:

1). Model elements optimized to the following accuracies:

S11: Magnitude: ≤ 2% Phase: ≤ 3°S22: Magnitude: ≤ 4% Phase: ≤ 5°S21: Magnitude: ≤ 10% Phase: ≤ 5°S12: Magnitude: ≤ 10% Phase: ≤ 5°

Accuracy defined with respect to measured S-data.

2). low/up : “low” optimized for 2-12 GHz band.“hi” optimized for 10-26 GHz band.



Typical modeled vs. measured S-parameter comparison is given below:

B1S11dataS[1.1]

B2S11modelS[1.1]

0.0 0.2 0.5 1.0 2.0 5.0 inf0.0

0.2

0.5

1.0

2.0

5.0

-5.0

-2.0

-1.0

-0.5

-0.2

Frequency 2.0 to 12.0 GhzLP 7612 Vds5V Ids=50% ldss=68mA

Optimized for 2 to 12 GHz

B1S22dataS[2.2]

B2S22modelS[2.2]

0.0 0.2 0.5 1.0 2.0 5.0 inf0.0

0.2

0.5

1.0

2.0

5.0

-5.0

-2.0

-1.0

-0.5

-0.2



B1S12dataS[1.2]

B2S12modelS[1.2]



0.05

0.04

0.03

0.02

0.01

0.0

B1S21dataS[2.1]

B2S21modelS[2.1]



6.0

5.0

4.0

3.0

2.0

1.0

0.0

150

120

90

60

30

0180

-150

-90

-60

-30

-120

180

-150

-120-90

-60

-30

0

30

6090

120

150



8. BIASING CIRCUITS AND STABILIZATION TECHNIQUES

Basic Self-Bias Configuration:

A typical hybrid amplifier circuit utilizing discretedevices and implemented in microstrip is shownschematically below, along with a sketch of the actualcircuit. In this particular example, the MESFET orPHEMT active device is “self-biased,” so that a singleDC voltage supply is used; this is done by floating the DCground of the device with discrete RF bypass capacitors.The device’s gate is DC grounded through the thin-film

resistor as shown, and therefore the required negativegate-source voltage is established by the voltage dropacross the source resistor. The drain bias is fed througha quarter-wavelength high-impedance line which is RFgrounded at one end. For this illustration, conjugate gainmatching is accomplished by use of “Series-L Shunt-C”matching networks on both the input and output circuits,implemented as microstrip lines and open-circuited stublines.

INPUT MATCHINGNETWORK

OUTPUT MATCHINGNETWORK

RFOUT

RFIN

SOURCE RESISTORNETWORK WITH RFBYPASS CAPACITOR

GATE GROUNDINGRESISTOR WITH

RF CHOKE

+VS

DC DE-COUPLINGCAPACITOR (x2)

8/4 HIGH-IMPEDANCEMICROSTRIP LINE FOR

RF CHOKE (SHORTED STUB)

THIN-FILM RESISTORLADDER FOR BIAS

LEVEL SETTING

“SERIES-L SHUNT-C” MATCHINGNETWORK IMPLEMENTED AS

MS LINE + OPEN-CIRCUITED LINE

RF CHOKE + THIN-FILMRESISTOR FOR DC GATE

GROUNDING



Gate Grounding Resistor:

In many instances, the gate DC groundingresistor and its associated RF choke can serve a dualrole; in addition to providing the necessary DC ground forthe gate of the active device, this network can providestabilization at frequencies below the circuit’s passband.Typically (and especially for low-noise designs) the RFchoke is implemented as a quarter-wavelength high-impedance microstrip line. Caution should be used forlengths other than 90° effective length in the passband,since the noise performance will be degraded. For low-noise devices (such as the LP 7512 and LP 7612) aresistor value of 5-15 ohms is satisfactory. For someapplications it is desirable to eliminate the groundingresistor, and in these cases care must be taken toensure that the circuit is stable below the passband,especially below 2 GHz, where the inherent gain of thePHEMT devices becomes very large.

Alternately, the grounding resistor may be placedat the “top” of the RF choke, and in this configurationsmaller or large resistor values may be used. This issometimes desired for power devices, to avoid re-biasingif the device begins to draw gate current.

Source Resistor Ladders:

For self-biased circuits, the DC operating currentis established by the voltage drop across the sourceresistor(s), so it is important to provide suitablecombinations of resistors. In this instance, the PHEMTdevices simplify the design process, since the Pinch-OffVoltage (VP) is nominally 0.8V, and is somewhatinvariant with IDSS and device size (gate width).Suggested resistor-ladder values are given in the tablebelow:

Nominal IDSS(mA)

RS Sequence(Ω)

30 30 / 15 / 7.5 / 3.25 / 1.6360 20 / 15 / 7.5 / 3.25 / 1.63120 5 / 2.5 / 1.25 / 0.63 / 0.31220 2 / 1 / 0.5 / 0.25 / 0.125450 1 / 0.5 / 0.25 / 0.125 / 0.06650 0.8 / 0.4 / 0.2 / 0.1 / 0.05

These values allow for adjustment about anominal 50% IDSS, which will occur at approximately 50%VP. For FSS’s MESFET devices, the Gate-Source

voltage required for a 50% IDSS operating point can beprovided for a specific wafer lot if needed.

Stabilization:

The general issue of stability is now considered,using a LP 7612 PHEMT device as an example. Thedata presented in the table following was taken at VDS =5V, IDS = 50% IDSS, with no source bypass capacitors;bond wire inductances are included, with gate bond wirestypically 0.004-0.006” long (2 per device), drain wires0.006-0.008”( 2 per device), and source wires 0.006-0.008” (4 per device). Note that the Stability Factor K isless than unity at all frequencies, indicating that deviceas is potentially unstable, depending upon the load andsource impedances presented to the device. The Gaincolumn presents either the Maximum Available Gain,GMAX, when k > 1.0, or Maximum Stable Gain, GMS, in thecase where K < 1.0. For k < 0, the device is unstable ina 50Ω system. Examination of the Stability Circles1

indicates that the largest regions of potential instabilityare in the load impedance plane, therefore carefulattention must be paid when designing output matchingnetworks. The Stability Factor k is defined as:

kS S D

S S

where D S S S S

≡− − +

≡ −

1

211

2

22

2 2

12 21

11 22 12 21:

where Sij = two-port power scattering parameters. Thepower gains GMAX and GMS are defined as:

( )GSS

k k

GS

S

MAX

MS

≡ ± −

≡

21

12

2

21

12

1

Stability circle definitions can be found in Vendelin1.

1. G. D. Vendelin, Design of Amplifiers and Oscillatorsby the S-Parameter Method, Wiley, New York, 1982.



LP 7612 S-Parameters, Stability and Power Gain

FREQ. S11 S21 S12 S22 GMAX

GMS

k S21(dB)

(GHz) MAG ANG MAG ANG MAG ANG MAG ANG (dB)2 0.95 -37° 5.95 152° 0.02 73° 0.83 -9° 25.8 0.18 15.5

6 0.78 -96 4.34 109 0.03 51 0.77 -23 21.1 0.52 12.710 0.68 -137 3.13 79 0.04 45 0.74 -35 19.0 0.80 9.914 0.65 -166 2.41 56 0.05 48 0.74 -47 17.2 0.89 7.618 0.64 171 1.93 36 0.06 54 0.74 -61 15.3 0.84 5.722 0.67 152 1.63 18 0.08 57 0.73 -74 13.4 0.61 4.326 0.70 131 1.37 0 0.10 56 0.75 -86 11.3 0.35 2.730 0.72 115 1.24 -16 0.15 53 0.81 -101 9.2 0.01 1.8

As can be seen from this data, the LP 7612provides excellent gain to 25 GHz and beyond, but doesrequire stabilization at lower frequencies. For example, ifthe device is to be used in a 6 - 18 GHz gain stage, thereis potential for instability below 5 GHz. One method toimprove this situation is to apply the RF choke /grounding resistor network to the input of the device;using a 5 mil wide by 65 mil long (0.13 by 1.65 mm.)microstrip line (on 10 mil [0.25 mm] alumina), with a 20Ωgrounding resistor gives the following:

FREQ. k GMAX

GMS

2 6.14 14.26 0.84 20.8

10 0.76 18.814 0.85 17.218 0.87 15.422 0.71 13.526 0.57 11.430 0.47 9.4

Now the stability is improved at frequencies below thepassband, with little degradation of GMS in the passbandof interest. For additional stabilization above thepassband, the network can be modified to include ashunt capacitor to ground (implemented as an open-circuited stub), as shown below:

Both distributed elements are quarter-wavelength (at the band center frequency fC) high-impedance lines. Above the passband, the open-circuited line acts as a shunt capacitance to ground,thereby improving the stability. This line’s width may bevaried to improve the roll-off characteristics above thepassband.

For low-frequency applications, classicalresistive shunt feedback may be used to simultaneouslystabilize and match the device. For example, a LP 7612,with two 50 pF source bypass capacitors, can bestabilized with a series R-L network (R=450Ω, L=1 nH)for operation in the 2-4 GHz band. This results in aninsertion gain S21 = 11.5 dB, and input/output return lossof better than -8 dB. Note that the phase of S21 for thisdevice is such that this technique is useful only forfrequencies below about 8 GHz.

λ/4 at fC

20Ω



9. LARGE-SIGNAL MODELS AND OPTIMUM POWER MATCH DATA

Introduction

Two large-signal models were utilized tocharacterize the non-linear properties of FSS’s discreteMESFET and PHEMT devices, the Root model(developed by Hewlett-Packard) and the classical Curticemodel. The Root model extraction consists of a file thatis directly read by Libra (Release 6.0) and MDS. TheCurtice model can also be used with these CADprograms, but was originally derived for use with SPICE.Curtice model elements are presented in tabular form inthis section, but the Root model extractions are availableonly on the FSS Devices Data Diskette. Forconvenience, Optimum Power Match data is presentedbelow for the devices that were Root-modeled.

The Root model represents a departure fromstandard non-linear models in that there are no closed-form analytical equations that model the I-V curves andnon-linear capacitance effects as in the Curtice model.Therefore the Root model does not assume anyparticular functional relationships for the I-V curves, andis inherently more accurate. One disadvantage of themodel is that it does not provide any additional insightinto the device physics, so it cannot be compared totheory directly; it is a “file based” model.

Root Model Background

The Root model replaces several of theelements in the linear model (Sec. 7) with “contourmaps” of charge vs. terminal voltage. Specifically, CGS,CGD and CDS are replaced with fitted contour functionsthat map the charge in the device as a 2-dimensionalfunction of terminal voltages; the device’s parasiticelements, such as RG, LG, etc., are modeled with lumpedelements. For example, the charge under the gate, QG,is fitted to such a contour by measuring the device’s S-parameters at many points along the I-V curves; fromthis data the voltage-dependent capacitances CG andCGD are mapped as shown in the figure below.Essentially the Root model derives an admittance matrixwhich, along with the parasitic elements, can predict thenon-linear behavior of a device without assuming aspecific functional behavior. The result is a fairlyaccurate high-frequency large-signal model. There aresome limitations, however, for example, the requirementto measure S-data over the device’s I-V curves isimpractical with large power PHEMT devices, since theyare inherently unstable in certain regions. Temperatureeffects and modeling of Class B and C operation are alsonot addressed by the model. Despite these limitations,the Root model represents one of the most accuratelarge-signal models available today that is supported incommercial CAD software.

( ) ( )C V ,V

Y V ,VG GS DS

11meas

GS DS=Im ,ω

ω

( ) ( )C V ,V

Y V ,VGD GS DS

12meas

GS DS=−Im ,ω

ω

VDS

VGS

QG

dQG = -CGDdVDS

dQG = CGdVGS

Root ModelQG Charge Contour



SUMMARY OF FSS DISCRETE DEVICE LARGE-SIGNAL MODEL EXTRACTIONS:

DEVICE MODEL

LP 7612 RootLP 6872(half-cell)

Root

LF 6836 RootLF 3814 RootLF 6872 RootLF 3830 CurticeLF 3850 Curtice

POWER PERFORMANCE AND OPTIMUM POWER MATCHAS PREDICTED BY THE ROOT MODEL:

DEVICE FREQUENCY(GHz)

OPTIMUMPOWERMATCH

P1dB

(dBm)POWER

GAIN(dB)

MAG PHASE

LP 76125V, 50%

IDSS = 63 mA

12182430

0.4920.4600.4400.502

75.4°102.0132.1161.1

18.418.618.618.3

14.811.08.97.9

LP 68728V, 50%

IDSS = 240 mA

6121824

0.4550.4330.5060.607

105.0141.0165.1-176.0

26.327.227.427.5

19.712.79.88.4

LF 68365.5V, 50%

IDSS = 142 mA

1218

0.4040.345

87.2121.4

19.720.3

9.77.1

LF 38147V, 50%

IDSS = 270 mA

4812

0.5260.4480.500

92.4122.2143.2

23.325.325.6

16.79.77.2

LF 68728V, 50%

IDSS = 257 mA

612

0.4860.432

76.7112.5

23.024.7

12.47.6



NOTES:

1). Root Model files are found on the FSS Devices Diskette; these files have the extension “.raw” The file should bedirectly read into the simulator; for example, in Libra the Root file should be place in the “Data” subdirectory in a specificProject Directory. These files are in ASCII text format. Do not scale the models. Predicted maximum power (at 1 dBcompression) is generally within 1-1.5 dBm of actual values; simulated power performance should be taken as a relativeperformance indication, not as an absolute.

2). The LP 6872 Root Model extraction was done for a half device, due to inherent instability in a 50Ω system. The usershould place two instances of the “HPFET” item, and connect the Gate, Drain, and Source connections together to formthe complete, composite 6872 device.

CURTICE MODEL EXTRACTIONS:

PARAMETER AND UNITS LF 3830 LF 3850

BETA, 1/V 0.0644 0.3668GAMMA, 1/V 0.5 0.5VOUTO, V 5.0 9.0VTO, V -3.73 -1.735A0, A 0.01 0.01A1, A/V 0.001 0.001A2, A/V2 -0.001 -0.001A3, A/V3 -0.0001 -0.0001TAU, sec. 0.0 0.0R1, Ω 0.0 0.0R2, Ω 0.0 0.0VBO, V 100 100VBI, V 0.6292 0.6119RF, Ω 0.0 0.0IS, A 1.019 x 10-11 1.019 x 10-11

N 1.228 1.186RDS, Ω 44.84 33.88CRF, Fd 1 x 10-6 1 x 10-6

RD, Ω 0.2 0.474RG, Ω 0.3 0.01RS, Ω 0.5 0.24RIN, Ω 4.401 -2.028CGSO, Fd 5.89 x 10-12 1.07 x 10-12

CGDO, Fd 0.0 0.0FC 0.5 0.5CDS, Fd 2.94 x 10-13 1.67 x 10-12

CGS, Fd 0.0 0.0CGD, Fd 1.83 x 10-13 3.91 x 10-13

LG, H (gate inductance) 1.07 x 10-10 6.30 x 10-11

LD, H (drain inductance) 6.60 x 10-11 6.20 x 10-11

LS, H (source inductance) 4.00 x 10-12 5.00 x 10-12

LBG, H (gate pad inductance) 3.50 x 10-11 3.50 x 10-11

LBD, H (drain pad inductance) 2.50 x 10-11 2.50 x 10-11

LBS, H (source pad inductance) 2.50 x 10-11 2.50 x 10-11



10. EXAMPLE CIRCUITS

Gain Stage for the LP 7612 DHPHEMT:

A gain stage was developed for the LP 7612discrete device, implemented in microstrip on a 10 milalumina substrate; the device is assumed to be die-attached onto a groundbar, with source bypasscapacitors (2 at 8 pF each). This will allow self-biasing,although the topology shown below does not include

biasing chokes. Optimization of the gain responseassumes that this stage will be utilized in a balancedconfiguration, with 90° quadrature hybrids (e.g., Langecouplers).

ELEMENT TYPE DIMENSIONS (mils)

INPUT CIRCUIT: (Element nomenclature after conventions used in Libra, Touchstone)1 MLIN W=10 L=40 (50Ω INPUT LINE)

2,3 MLEF 2 STUBS (OPEN-CIRCUITED MLIN) W=11.9 L=17.54 MCROS W1=10 W2=6 W3=W4=11.95 MLIN W=6 L=25.5

6,7 MLEF 2 STUBS W=13.8 L=11.68 MCROS W1=6 W2=21.1 W3=W4=13.89 MLIN W=21.1 L=15.9

10,11 MLEF 2 STUBS W=13.5 L=20.312 MCROS W1=21.1 W2=10.2 W3=W4=13.513 MLIN W=10.2 L=714 MTEE W1=10.2 W2=10.2 W3=215 MLIN W=2 L=67 (GATE GROUNDING CHOKE)16 TFR RS=50 W=2 L=1 (GATE GROUNDING RESISTOR)17 MLIN W=10.2 L=3

OUTPUT CIRCUIT:1 MLIN W-5.3 L=28.6

2,3 MLEF 2 STUBS W=9 L=9.44 MCROS W1=5.3 W2=11.6 W3=W4=95 MLIN W=11.6 L=276 MLEF 1 STUB W=6.4 L=22.67 MTEE W1=11.6 W2=10 W3=6.48 MLIN W=10 L=40 (50Ω OUTPUT LINE)

INPUT CIRCUIT OUTPUT CIRCUIT

LP 7612

NOT SHOWN: RF CHOKESFOR DRAIN BIASING, DCBLOCKING CAPACITORS

TUNING PADS MAY BE ADDED ASDESIRED. 50Ω INPUT/OUTPUTMLINS MAY BE SHORTENED ASNEEDED.



Simulated linear (small-signal) performance ofthis gain stage is shown below; the SSG was 9.75 dBover the 4 to 20 GHz band, with ±0.25 dB of gain ripple.Minimum stability (K-factor) was 0.7 at 8 GHz In abalanced configuration with Lange couplers (W=1.2 mils,S=0.85 mils, and L=97 mils), the SSG was 9.5 ±0.5 dB,with a minimum k-factor of 2.0. The improvement instability in a balanced configuration is typical, since the

potentially unstable regions in the source and loadplanes are transformed to areas outside the normalSmith chart (Γ ≥ 1.0). The Root model was utilized tosimulate the power performance, and the gain stage asdescribed above showed 5 dB of power slope across theband.

SINGLE-ENDED GAIN STAGE PERFORMANCE

12.0

11.0

10.0

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.52.0 24.0

Prototype LP 7612 Gain Stage Linear Analysis

7612gain_tbS217612gainS[2,1]db

7612gain_tbK17612gainK

Frequency 2.0 GHz/DIV



The output circuit can be re-optimized for betterpower performance, resulting in the modified outputsection shown below. The optimum power match datapresented in the preceding section was used for this re-optimization, and in a self-biased balanced configuration,

a pair of 7612 devices provided 19.0 to 20.8 dBm oflinear power (simulated) over the 6-18 GHz band asshown. Note that the devices were biased at about 70%of IDSS, and that the Root model correctly predicted nogain expansion prior to compression.


MODIFIED OUTPUT CIRCUIT:1 MLIN W=2.1 L=39.72 MLEF STUB W=11.5 L=25.54 MTEE W1=2.1 W2=10 W3=11.55 MLIN W=10 L=40 (50Ω OUTPUT LINE)

POWER PERFORMANCE WITH MODIFIED OUTPUT STAGE

MODIFIED OUTPUT CIRCUIT

MAY BE MEANDERED TO FIT SPACERESTRICTIONS AND ALLOW FORTUNING OF ELEMENT LENGTH

13.0

12.0

11.0

10.0

9.0

8.0

7.0

25.0

20.0

15.0

10.0

5.0

0.0

-5.0-10.0 20.0

7612balpow_tbPF17612balgainPFdBm

7612balpow_tbGAIN7612balgainOUT_EQNdB

Frequency, GHz6.0

12.018.0

Linear Power (P1dB):6 GHz12 GHz18 GHz

Power 5.0 dBm/DIV

Prototype LP 7612 Gain Stage w/Power MatchBalanced Configuration Vds=5.5V Ids=45mA (per device)Self-Bias RS=8 ohms



6-18 GHz Power Stage for the LP 6872 DHPHEMT:


INPUT CIRCUIT:1 MLIN W=10 L=40 (50Ω INPUT LINE)

2,3 MLEF 2 STUBS W=6.9 L=13.74 MCROS W1=10 W2=3.2 W3=W4=6.95 MLIN W=3.2 L=126 MLEF 1 STUB W=17.1 L=4.47 MTEE W1=3.2 W2=6.9 W3 =17.18 MLIN W=6.9 L=34.6

9,10 MLEF 2 STUBS W=24 L=20.611 MCROS W1=6.9 W2=37.5 W3=W4=2412 MLIN W=37.5 L=1613 MTEE W1=37.5 W2=37.5 W3=314 TFR RS=50 W=3 L=2.5 (GATE GROUNDING RESISTOR)15 MLIN W=3 L=48 (GATE GROUNDING CHOKE)17 MLIN W=37.5 L=3

OUTPUT CIRCUIT:1 MLIN W=4.3 L=20.4

2,3 MLEF 2 STUBS W=30.4 L=16.74 MCROS W1=4.3 W2=4.6 W3=W4=30.45 MLIN W=4.6 L=33.86 MLEF 1 STUB W=14.2 L=26.77 MTEE W1=4.6 W2=10 W3=14.28 MLIN W=10 L=40 (50Ω OUTPUT LINE)

INPUT CIRCUITOUTPUT CIRCUIT

LP 6872





The Root model was utilized to optimize thepower performance of this circuit, and with two LP 6872PHEMTs, in a self-biased balanced configuration,produced over 30 dBm of linear power, with about 9 dBof power gain. The model did exhibit some irregularitiesunder conditions of large input power levels which

created convergence problems during the simulation. Inthe plot below, the circuit is not fully compressed by 1 dBacross the band, but does exhibit acceptable outputpower over the 6-18 GHz band. Simulated SSG = 9.5dB, with ±0.4 dB of gain ripple.

POWER PERFORMANCE IN A BALANCED CONFIGURATION:

Output Power

Power Gain

15.0

14.0

13.0

12.0

11.0

10.0

9.0

8.0

7.0

6.0

5.0

31.0

30.0

29.0

28.0

27.0

26.0

25.0

24.0

23.0

22.0

21.00.0 20.0Frequency 5.0 GHz/DIV

Prototype LP6872 Power StageBalanced Self-Biased at 22.5dBm Input PowerVd=9.0V Ids=140mA Idss=210mA RS=2.5 ohms

6872balpower_tbPF16872balpowerPFdBm

6872balpower_tbGAIN6872balpowerOUT_EQNdB



The plot below shows predicted compressioncharacteristics in this stage, with a slight amount of gainexpansion (about 0.15 dB), consistent with the quiescent

bias point of 67% (see Sec. 6). Simulated P1dB = 30.7dBm at 16 GHz, with a saturated output power of about31.5 dBm.

COMPRESSION CHARACTERISTICS AT 16 GHz

Small-Signal Gain

32.0

27.0

22.0

17.0

12.0Power 2.0 dBm/DIV

Prototype LP6872 Power StageVd=9.0V Ids=140mA Idss=210mA RS=2.5 ohms

6872balpower_tbPF16872balpowerPFdBm

6872balpower_tbGAIN6872balpowerOUT_EQNdB

11.0

10.0

9.0

8.0

7.00.0 26.0

Frequency, GHz16.0

P1dB = 30.7Psat = 31.5



2 GHz 1 Watt Power Stage for the LP 6872:

A 2 GHz, 1W power stage utilizing two LP 6872DHPHEMT devices is shown below, implemented inmicrostrip on Duroid (εR = 2.2, h = 10 mils [0.25 mm]),and using a lossy input matching network to achieveadequate stability and flat SSG.1 The output circuit isdesigned for optimum power match, while the inputcircuit is derived from a second-order all-pass network,with the PHEMT’s input capacitance CGS (as modified bythe Miller effect) incorporated as one of the network’selements. The simulated SSG is 17.5-18.0 dB at 21GHz, with an input return loss of -12 dB, and a worst-

case stability factor of 1.3 (at 2.5 GHz). Theimplementation of this circuit utilizes a combination oflumped element (chip) components and microstripelements. The circuit is predicted to provide +30.2 dBmof linear power at 2 GHz, with a Power-Added Efficiencyof 38%.

1. Arell, T., and Hongsmatip, T., “2-6 GHz CommercialPower Amplifier,” Applied Microwave, Winter 1993, pp.51-56.

ELEMENT TYPE DIMENSIONS (mils) OR VALUE (units)

INPUT CIRCUIT:1 MLIN W=30 L=100 (50Ω INPUT LINE)L1 IND L=1.6 nHL2 IND L=1.1 nHC1 CAP C=1.3 pFR1 RES R=18 ohms

OUTPUT CIRCUIT:1 MLIN W=27 L=352 MTEE W1=27 W2=30 W3=343 MLEF 1 STUB W=34 L=574 MLIN W=30 L=100 (50Ω OUTPUT LINE)

L1

C1

L2

R1

-VG

100 pF (x4)

LP 6872 (x2)

LAYOUT MAY NEEDTO BE MODIFIED TOACCOMODATE ACTUALCHIP COMPONENT SIZES

NOT SHOWN: DRAINBIASING CIRCUIT



PREDICTED POWER PERFORMANCE

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

0.0 20.0

6872cbandpow_tbPF16872cbandpowPFdBm

6872cbandpow_tbGAIN6872cbandpowOUT_EQNdB

Frequency, GHz1.52.02.53.0

Linear Power (dBm):1.5 GHz 29.72.0 GHz 30.22.5 GHz 30.53.0 GHz 30.5

Power 5.0 dBm/DIV

Prototype 2 GHz Power AmplifierTwo LP 6872 PHEMTsVds=9V Ids=290mA Dual Bias Vgs=-0.3V

32.0

30.0

28.0

26.0

24.0

22.0

20.0

18.0

16.0

14.0

12.0

10.0

8.0

6.0



6-18 GHz Low Noise Stage for the LP 7512 SHPHEMT:


INPUT CIRCUIT:1 MLIN W=10 L=40 (50Ω INPUT LINE)

2,3 MLEF 2 STUBS W=10 L=134 MCROS W1=10 W2=9.4 W3=W4=105 MLIN W=9.4 L=33

6,7 MLEF 2 STUBS W=10.8 L=14.88 MCROS W1=9.4 W2=20.4 W3=W4=10.89 MLIN W=20.4 L=40.3

10,11 MLEF 2 STUBS W=18.4 L=16.112 MCROS W1=20.4 W2=7.5 W3=W4=18.413 MLIN W=7.5 L=9.814 MTEE W1=W2=7.5 W3=215 MLIN W=2 L=6716 TFR RS=50 W=2 L=117 MLIN W=7.5 L=3

OUTPUT CIRCUIT:1 MLIN W=12 L=31.3

2,3 MLEF 2 STUBS W=27.7 L=204 MCROS W1=12 W2=10.3 W3=W4=27.75 MLIN W=10.3 L=17.36 MLEF 1 STUB W=20 L=167 MTEE W1=10.3 W2=10 W3=208 MLIN W=10 L=40 (50Ω OUTPUT LINE)

INPUT CIRCUIT OUTPUT CIRCUIT

LP 7512





The simulated noise and gain performance ofthis stage is shown below; nominal performance was 1.9dB noise figure from 12-18 GHz, with SSG = 8.5 ± 0.6 dBover the 6-18 GHz band. Significantly lower noise figure

can be achieved with this device for narrowerbandwidths; the typical LP 7512 performance is 1.0 dBNF at 18 GHz.

SINGLE-ENDED NOISE PERFORMANCE

Gain

10.0

9.0

8.0

7.0

6.0

5.0

Power 2.0 GHz/DIV

Prototype Single-Ended LP 7512 Low Noise StageVds=2V Ids=15mA

7512noise_tbS217512noiseS[2.1]dB

7512noise_tbNF17512noiseNFdB

6.0

5.0

4.0

3.0

2.0

1.02.0 20.0

Noise Figure



11. RECOMMENDED ASSEMBLY TECHNIQUES

Handling of Discrete Devices:

Handling of FSS Discrete Devices must at alltimes be done with Electrostatic Discharge (ESD)precautions, as outlined below. The devices may bemanually handled with clean sharp tweezers by graspingthe device on its edges. Some devices include airbridgestructures that are easily damaged with carelesshandling.

Automatic handling equipment may be used, butsoft, conductive pick-up collets are preferred. Colletsmust be grounded to prevent static charge accumulation.The optimum collet size is such that the device iscontacted around its periphery and away from the activestructures in the center. Rectangular cross-sections arepreferred.

Die Attach:

The recommended die attach is the “eutectic”die attach, using a 80/20 Gold/Tin eutectic solder, whichhas a melt temperature of about 280°C. Eutectic dieattach should be done under forming gas (90% N2, 10%H2) for best results. If forming gas is not available, thenclean dry N2 gas should be used. Eutectic die attach inambient air is not recommended. Pre-sized eutecticpreforms are available in a variety of sizes; use apreform whose dimensions are close to the device beingattached. The device can be placed using clean sharptweezers, once the preform has melted on the heatedstage (which is typically 285-290°C); the assemblyshould be removed from the heated stage as soon asthe die is positioned. For large devices (greater than 0.5x 0.5 mm or 20 x 20 mils), the assembly should becooled at a rate of about 10°C per minute, to reducethermal stresses. Maximum time at the eutectictemperature is 1 min.

Other solder materials may be used; contact theFoundry for compatibility. Another acceptable die attachmethod is the use of conductive epoxy (gold or silverfilled), which is assembled at room temperature and thencured per the manufacturer’s directions. The epoxy dieattach should not be used for power devices, since thethermal resistivity of the device will be degraded.

Die Placement:

In general devices should be placed as close aspossible to the matching circuits, regardless of the typeof substrate material used. For example, with microstripcircuits implemented on alumina, the die should beplaced within 0.001” (0.025 mm) of the input matchingcircuit to minimize the gate bond wire lengths. If sourcebypass chip capacitors are used, they should be placedas close as possible to the device to minimize sourcebond wire length.

The optimum heatsink material is gold-platedcopper, molybdenum, or Cu composites, which allow forefficient heat dissipation. Less desirable is kovar, anddirect die-attach onto duroid or alumina should only beused for low noise applications. All heatsink materialshould be gold (100 µin min.) over nickel plated. Poorheatsinking will result in high operating channeltemperatures and degraded device reliability.

Lead Bond:

The recommended lead bond technique isthermocompression wedge bonding with 0.001” (25 µm)diameter gold wire. This should be done on a heatedstage at 230-240°C, with a heated bonding tool at 150-160°C. Dry N2 or forming gas is the preferred ambientduring bonding. The bond tool force should be 35-38gm. Ultrasonic bonding is not recommended. Contactthe Foundry for additional information.

Storage:

FSS discrete devices should be stored in cleandry Nitrogen gas at room temperature (20-25°C).Alternately, storage at room temperature in clean dryambient air is acceptable; in any case, the parts shouldbe stored with proper ESD precautions.

ESD Precautions:

Standard ESD precautions for Class 1A devices(0-500V) should be observed in storing, handling, andassembling FSS discrete devices. Users should followthe measures outlined in MIL-STD-1686, “ElectrostaticDischarge Control Program,” and MIL-HDBK-263,“Electrostatic Discharge Control Handbook.”



12. PARAMETRIC SCREENING AND QUALITY ASSURANCE

Filtronic ’s Quality Assurance procedures for itsdiscrete FET and PHEMT devices are patterned after theJANC level requirements of MIL-STD-19500J. FSSoffers its discrete devices in three basic grades, asfollows:

• Commercial/Military Grade (C/MG)(Bulk purchase)

• Sorted Military Grade (SMG)• High-Reliability Grade (HiRel)

These grades differ with respect to the level ofparametric screening and visual inspection. All gradesare warranted to meet or exceed the performancespecifications as indicated for each device type on theappropriate Datasheet. Test methods and visualinspection criteria are per MIL-STD-750, as detailedbelow. The discrete device fabrication, test, and QualityConformance Inspection (QCI) sequence is as follows:

GaAs SUBSTRATE INSPECTIONAND PREPARATION

MOLECULAR BEAMEPITAXIAL GROWTH

EPITAXIAL CHARACTERIZATIONDefect Density

Sheet Carrier DensityHall Mobility

LOT FORMATION6-10 wafers/lot

PROCESSING / FABRICATION

FINAL ELECTRICAL ANDVISUAL INSPECTION

100% DC TEST

GROUP A TESTSSubgroups 1 and 210 devices / wafer

ACCEPT/REJECT 10/1

GROUP B TESTSBond Pull / Die Shear

5 devices / waferACCEPT/REJECT 5/0

LOT ACCEPTANCE INSPECTIONPer Sequence Below

ACCEPT/REJECT 10/1

PREPARATION FOR SHIPMENT

COMMERCIAL/MILITARY GRADESample Visual Inspection

Film Frame Packing

SORTED MILITARY GRADE100% Visual Inspection

Packing (Waffle or Gel Pack)

HIGH-RELIABILITY GRADEWafer Lot submittal for

JANS screening

SCRIBE AND BREAK

SAMPLE VISUAL INSPECTION

FILTRONIC SOLID STATEDISCRETE DEVICEFABRICATION AND

QUALITY ASSURANCESEQUENCE

STABILIZATION BAKE



TABLE 1 GROUP A TESTS AND METHODS

SUBGROUP TEST OR INSPECTION SYMBOL MIL-STD-750METHOD

1 DC Characteristics:Saturated Drain-Source CurrentTransconductancePeak Transconductance (opt.)Pinch-Off VoltageGate-Source and Gate-Drain Leakage CurrentGate-Source and Gate-Drain Breakdown VoltageForward Gate Voltage (opt. for JANS level)

IDSS

GM

GM PEAK

VP

IGS, IGD

BVGS, BVGD

VGF

34133455 (60 Hz)3455 (50%VP)34033401, 34113401, 3411

2 RF Characteristics:Optimum Noise FigureAssociated Gain at NFMIN

Max. Output Power at 1 dB Gain CompressionPower Gain at P1dB

Power-Added Efficiency at P1dB

NFMIN

GA

P1dB

GP

PAE (η)

3246.1

3255

NOTE: Noise Figure is not measured on power devices, and power performance (P1dB, GP, PAE) is not characterized onlow noise devices.

LOT ACCEPTANCE INSPECTION

SMALL LOT ASSEMBLY10 devices / wafer

DIE ATTACH / LEAD BOND

INTERNAL VISUAL INSPECTION

HERMETIC LID SEAL

STABILIZATION BAKE

GROUP A TESTSSubgroup 1

DC POWER BURN-IN96 Hours, TCH = 175°C

GROUP A TESTSSubgroup 1

ENDPOINT AND DELTA CALCULATIONSPer Datasheet and Delta Limits Table

LOT ACCEPTANCE INSPECTIONSEQUENCE:



TABLE 2 GROUP B TESTS AND METHODS

TEST OR INSPECTION MIL-STD-750METHOD

CONDITION SMALL LOTACCEPT/REJECT

n/c

Bond Strength (Bond Pull)

Die Shear

2037

2017

All leads 5/0

5/0

TABLE 3 LOT ACCEPTANCE INSPECTION TESTS AND METHODS

TEST OR INSPECTION MIL-STD-750METHOD

CONDITION SMALL LOTACCEPT/REJECT

n/c

Internal Visual InspectionStabilization BakeDC Power Burn-InEndpoint CalculationsDelta Calculations

20721031.41039

FSS Worksmanship Standards24 hr. at 200°C in N2 ambient96 hr. at 175°C channel temperaturePer Datasheet min/max valuesPer Table 4 Limits

---------

10/110/1

TABLE 4 DELTA LIMITS

DELTA PARAMETER SYMBOL DELTA LIMITS FORDC POWER BURN-IN

Saturated Drain-Source CurrentTransconductancePeak Transconductance (opt.)Pinch-Off VoltageGate-Source and Gate-Drain Leakage CurrentGate-Source and Gate-Drain Breakdown Voltage

IDSS

GM

GM PEAK

VP

IGS, IGD

BVGS, BVGD

±20%±20%

---±20%

±150% or 2.0ΦA±25%



In summary, 25 devices are taken at randomfrom each wafer submitted for QCI screening, with 5devices used for Bond Pull/Die Shear testing, 10 forGroup A testing, and 10 for Lot Acceptance Inspection(LAI). The devices used in Group A testing are dieattached and lead bonded into 50 ohm microstripevaluation circuits, and triple-sleeve low-loss coaxialtuners are used to provide optimum impedance matchingfor power, gain, and noise figure measurements. TheLAI devices are assembled and sealed into 100 milceramic leaded packages for the power burn-in. Strictadherence to JANC requirements calls for a sample of22 per inspection lot, with an accept/reject limit of 22/0(no failures allowed). This corresponds to a LotTolerance Percent Defective (LTPD) of λ=10; the FSSscreening uses a sample size of 20 total, with 2 failuresallowed (20/2). The equivalent LTPD level isapproximately λ=25. The less stringent LTPD is justifiedby the omission of High-Temperature Reverse Bias(HTRB) screening prior to the power burn-in, which

would serve to remove “infant mortality” devices. Theuse of microstrip test circuits for 10 of the sampledevices is done to minimize RF performance degradationdue to package parasitics.

For the Sorted Military Grade, Group A and LAItesting is done on each wafer. For Commercial/MilitaryGrade, this screening is done on a “run” basis; afabrication run is defined as a group of 6-10 wafers thatare fabricated and processed simultaneously as a group.Therefore as a minimum, each wafer run of 6-10 waferswill have at least one wafer submitted for Group A andLAI testing; devices purchased under the C/MG are notnecessarily from a wafer that has been screened, but thepurchaser can request devices from the screened waferin a given lot for a nominal surcharge. Devicespurchased to the High-Reliability Grade are subjected toa more rigorous screening procedure per MIL-19500JANS level. The various grades and the associated testand inspection methods are summarized below:

DISCRETE DEVICE GRADES AND SCREENING PROCEDURES

GRADEGROUP ATESTING LAI T ESTING

SHIPMENT METHOD100% DC DATA

ON DISKETTEVISUAL

INSPECTIONMETHOD

FILM & RING WAFFLE OR GELPACKED

C/MGCOMMERCIAL

PER EACHRUN

PER EACHRUN

ONLY NOT AVAILABLE NOT AVAILABLE SAMPLE BASIS

C/MGMILITARY UPGRADE

EACHWAFER

EACH WAFER ONLY NOT AVAILABLE AVAILABLE SAMPLE BASISVISUAL YIELD

PROVIDED

SMG EACHWAFER

EACH WAFER N/A YES PROVIDED 100% BASIS

HI-REL JANS JANS N/A YES PROVIDED 100% BASIS

NOTES:

1). Minimum order quantity for C/MG option is 1/4 wafer; approximate quantities available from an authorized FSS SalesRepresentative or from the Foundry.2). Hi-Rel screening per customer Source Control Drawing.



WAFER FABRICATION

INITIAL VISUAL INSPECTIONMIL-750 METHOD 2070, 2072

SAMPLE BASIS: 35 DIEPER WAFER

PCM TESTING

STABILIZATION BAKEMIL-750 METHOD 1032

200C FOR 24 HRS100% DC TESTING

GROUP A, SUBGROUP 1SCRIBE & BREAK

SMALL LOT BUILD35 MIN. PACKAGED DEVICES

DIE ATTACH, LEAD BONDAND SEAL

INTERNAL VISUAL INSPECTIONMIL-750 METHOD 2071

GROUP BSUBGROUP 1

SEM INSPECTIONMIL-750 METHOD 2077

BOND PULL TESTMIL-750 METHOD 2037

3 DEVICES MIN., ALL LEADS

DIE SHEAR TESTMIL-750 METHOD 2017

3 DEVICES MIN.

LID SEAL

STABILIZATION BAKE175C FOR 24 HRS

DC PARAMETRIC SCREENGROUP A, SUBGROUP 1

SMALL LOT INSPECTIONQCI / LOT QUALIFICATION DC TESTED DIE

FOR VISUAL INSPECTIONAND SHIPMENT PREP

FILTRONIC SOLID STATEMIL-19500J JANS SCREENING SEQUENCE



PRE-BURN-INDC PARAMETRIC TESTING

PRE-CONDITIONINGDC POWER BURN-IN

MIL-750 METHOD 1039TCH = 150C FOR 160 HRS

POST-BURN-INDC PARAMETRIC TESTING

PDA DETERMINATION

GROUP BSUBGROUP 5

ACCELERATED LIFE TESTMIL-750 METHOD 1027

5 DEV. / 0 REJECTS

PRE-BURN-INPARAMETRIC TESTING

DC POWER BURN-INTCH = 225C FOR 240 HRS

POST-BURN-INPARAMETRIC TESTINGDELTA CALCULATIONS

GROUP BSUBGROUP 2

ACCELERATED LIFE TESTMIL-750 METHOD 1027

5 DEV. / 0 REJECTS




GROUP BSUBGROUP 3

OPERATING LIFE TESTMIL-750 METHOD 1026

8 DEV. / 0 REJECTS




GROUP ASUBGROUP 2

RF TESTS10 DEV. / 0 REJECTS(OPTIONALLY DONE

ON CARRIER-MOUNTEDDEVICES)

100% VISUALINSPECTION

QA CERTIFICATIONPREPARATIONFOR SHIPMENT

SHIPMENT CSI



13. DISCRETE DEVICE UNIFORMITY

The uniformity of FSS’s discrete PHEMT andMESFET devices depends fundamentally on thematerials and processing technology utilized in themanufacturing process. In addition to the ParametricScreening and QCI testing as outlined in Sec. 12, typicaldevice uniformity data is presented below, using the LP7612 DHPHEMT as the example. Uniformity ispresented at three levels: wafer uniformity, same-lotwafer-to-wafer uniformity, and lot-to-lot uniformity. The

DC parametrics given are as measured during the 100%screening, while the RF data presented was taken from aRF-probeable version of the LP 7612. This modified7612 device was directly measured on-wafer usingCascade Microtech GSG coplanar probes. While theS-data of this modified 7612 is not identical to theproduction version, the data does represent the processand material variation across a wafer.

TYPICAL 100% DC PARAMETRIC TEST DATALP 7612 LOT: 3059 WAFER: #4 TEST DATE: 4/30/96

TOTAL DIE TESTED: 21566 TOTAL PASSED DEVICES: 14032

PARAMETER UNITS MEAN STD.DEV.σ

LIMITSUP/LOW

CPK

Drain-Source Current, IDSS mA 70.7 6.6 40/85 0.72Pinch-Off Voltage, VP V -0.84 0.19 -0.25/-1.50 1.06Transconductance at IDSS, GM mS 67.6 21.5 50/--- 0.27Transconductance at 50% VP mS 89.9 8.5 60/--- 1.17Gate-Drain Breakdown, BVGD V -11.5 1.02 -8/--- 1.15Gate-Source Breakdown, BVGS V -10.9 1.70 -6/--- 0.98Leakage Current, IGSO µA 0.53 0.56 ---/10 0.30

TYPICAL RF UNIFORMITY: WAFER BASISLP 7612 LOT: 3051 WAFER: #3

10 SITES ACROSS WAFER VDS = 5V IDS = 50%IDSS

PARAMETER FREQ(GHz)

MAGNITUDE PHASE

MEAN σ MEAN σS11 5

1525

0.9220.6450.616

0.0050.0020.010

-60°-126-149

3°33

S21 51525

4.732.271.49

0.150.040.07

1358057

233

S12 51525

0.0480.0680.036

0.0050.0090.007

5963

222

S22 51525

0.7550.5640.572

0.0180.0300.068

-26-55-68

244

MaximumAvailableGain (dB)

51525

19.911.77.4

0.40.40.1

--- ---



TYPICAL RF UNIFORMITY: LOT BASISLP 7612 LOT: 3051 WAFERS #3, 4, 5, 6

ONE SITE AT RANDOM PER WAFERVDS = 5V IDS = 50%IDSS

PARAMETER FREQ(GHz).

3 4 5 6

MAG. ANG. MAG. ANG. MAG. ANG. MAG. ANG.S11 5

1525

0.9290.6410.599

-55°-120-144

0.9130.6460.633

-65°-133-157

0.9130.6390.617

-62°-129-152

0.9140.6390.626

-65°-133-157

S21 51525

4.882.491.63

1388462

4.822.251.45

1327752

4.972.381.55

1348159

4.902.281.48

1317651

S12 51525

0.0540.0800.054

6091

0.0440.0570.024

58310

0.0640.0880.062

5670

0.0460.0610.027

5725

S22 51525

0.7190.5120.503

-29-62-74

0.7670.5890.610

-24-51-64

0.7310.5080.509

-31-61-73

0.7700.5760.594

-26-53-67

MaximumAvailableGain (dB)

51525

19.6*12.57.6

---20.4*11.57.6

---18.9*12.37.5

---20.3*11.47.5

---

NOTE: Maximum Available Gain with * indicates Maximum Stable Gain, since Stability Factor k < 1.0.

Lot-to-Lot Uniformity:

All lots are screened as outlined in Sec. 12, andmust meet all parametric test specifications. In this way,minimum device performance is assured as detailed inthe appropriate Datasheet. Due to varying userrequirements, lots (groups of 6-10 wafers) areoccasionally targeted to specific IDSS ranges. This

targeting accounts for much of the lot-to-lot variation, butcomparison of different lots with similiar IDSS values willexhibit good uniformity, on the order of same-lot wafer-to-wafer uniformity. Users are encouraged to obtainsamples from a specific lot in order to verify performancein a specific circuit or application; the quantity ofavailable die from a particular wafer or wafer lot isavailable from the Foundry.



14. DEVICE RELIABILITY

A summary of reliability investigations that havebeen conducted on FSS’s MESFETs, PHEMTs, andMMICs is included in Appendix A. For MESFETs, themeasured MTTF is 1.0 x 108 hrs. at a channeltemperature of 120°C, with an Activation Energy of 1.52eV, and An Instantaneous Failure Rate of less than 10FITs. For PHEMT devices, in addition to the work

summarized in the Appendix, recent work has shownthat the MTTF for DHPEMTs exceeds 1.2 x 107 hrs. atTCH = 120°C, based on an accelerated burn-in ofsamples at 225°C. These samples have accumulated1,045 hrs. with no failures.



APPENDIX A


Device and Process Reliability 50

Device and Process ReliabilityInGaAs / AlGaAs PHEMT Devices

Revision BJanuary 1998



Scope

This report presents a current assessment of the reliability of InGaAs/AlGaAs Pseudomorphic High ElectronMobility Transistor (PHEMT) discrete and MMICs devices, as presently manufactured at Filtronic Solid State (FSS). GaAsMESFET reliability results from earlier research conducted at FSS is included for completeness. The report concludeswith a summary of work in progress.

Background

The reliability of semiconductor devices can be modeled by the "log-normal" distribution, which is a probabilitydistribution function described by a shape parameter and a median lifetime, as follows:

p t

t

n t tm( ) exp( / )

≡−

1

2 2

2

2σ π σ

where σ = shape parameter, t = time, and tm = median lifetime. The interpretation of this function in the context of devicereliability is that integrating p(t) from zero to some time tf gives the probability that a given device has failed. Another wayto interpret this function is that the area under the curve p(t) from zero to the median lifetime tm is equal to 0.5, indicatingthat there is a 50% chance that a device will have failed. The function is normalized such that the total area under thecurve is equal to one. This failure probability distribution assumes one dominant failure mechanism, with no early or“freak” failures.

The median lifetime of a population of devices is closely related to the Mean-Time-to-Failure (MTTF), andgenerally the two quantities are interchangeable. The MTTF is one of the primary parameters that must be determined fora given device or process, and this is generally done by exposing a sample of devices to accelerated life testing atelevated temperatures. The MTTF is determined by the definition of a device "failure," which in turn may be affected by anumber of degradation or failure mechanisms. One generally attempts to identify a single dominant failure mechanism,and MTTF at some elevated temperature is assumed to follow the Arrhenius relationship:

AFE

k T TA

o A≡ −

exp1 1

where AF = Arrhenius Acceleration Factor, EA = Activation Energy, k = 8.62 x 10-5 eV/ K (Boltzmann constant), TO =standard operating temperature, and TA = acceleration temperature. The Activation Energy (usually expressed in electronvolts, eV) characterizes the degradation process, and clearly should be as large as possible for reliable device operation atelevated temperatures. For example, assuming EA = 1 eV, the acceleration factor resulting from device operation at250°C, compared to operation at 120°C is AF = 1,537, meaning that a MTTF of 106 hours will be reduced to 651 hours atthe elevated temperature.

Another commonly used assessment in reliability analysis is the Instantaneous Failure Rate (IFR), which for a log-normal distribution is given by:1

( )

( )IFR

n t t

t efrc n t t

m

m

≡−

21

21

2

22

exp /

/

σ

σ πσ

where efrc denotes the complementary error function. The IFR is usually multiplied by 109, and the units of "FITs" arecommonly used, 1 FIT meaning one failure in 109 hours of operation. In expanded form:

1H. Fukui, et. al., “Reliability of Power GaAs Field-Effect Transistors,” IEEE Trans. on Elec. Devices, Vol. ED-29, No. 3, March 1982.



( ) ( )IFR

n t t

t e dt

where z n t tm

tz m=

−

≡−∫

21

2

12

12

2

0

2

exp /

: /σ

σ ππ

σ π

To completely characterize the distribution, one must determine the shape factor and the median lifetime (orMTTF) at a given temperature, and the Acceleration Factor is used to predict the MTTF at some other temperature. Theshape factor is taken to be invariant with temperature; it expresses the variation in time of device failures as the sampleages past the median lifetime. Ideally there are no device failures until the median lifetime is reached, at which time mostof the devices fail at essentially the same time. For component and system lifetimes ts such that: ts << tm, the average IFR≈ 1/MTTF.

In the case of MESFET and PHEMT devices, the integrity of the Schottky contact formed by the Gate electrode isof critical importance to reliable device operation. Changes in the metal-semiconductor barrier height will affect all otherchannel parameters; therefore, the temperature that is substituted into the Arrhenius formula is the average channeltemperature, determined by the following:

T P P PCH IN DC J OUT= + −Θ

where: TCH = Channel temperature, PIN = RF input power, PDC = DC power dissipated in device, ΘJ = channel-to-heatsinkthermal resistivity, and POUT = RF power delivered to a load. The channel region for these devices is defined as the regionextending from the Drain contact to the Source contact, along the total periphery of the Gate, if the device is a multi-fingeror interdigitated topology. In the case of FSS devices, the thermal resistivity is measured by direct-contact nematic liquid-crystal thermography. This method allows near-optical resolution, and features less than one micron can be imaged.

MESFET Device Structure and Reliability Assessment

The MESFET structure used at FSS is a classical recessed, offset gate structure, as shown below:

The semiconductor structure shown is grown by Molecular Beam Epitaxy, with the gate structure defined eitherphotolithographically or by direct-write electron-beam techniques. The device is passivated with a 2000A layer of siliconnitride (Si3N4). The Gate metallization system in a refractory Ti/Pt/Au structure, with additional overplated gold, and theohmic contacts are alloyed AuGe/Ni/Au with overplated gold; both the Gate and ohmic contacts are industry-standardtechnologies.

AuGe / Ni / Au Alloyed Contacts

N+ GaAs Active Layer

N- Buffer Layer

DrainContact

SourceContact

Ti / Pt / Au Recessed Gate

N++ Contact Layer

GaAs MESFET STRUCTURE



Samples of 0.5 x 285 (Gate length x width) µm discrete MESFETs have been evaluated using both hightemperature storage (non-operating), and elevated temperature DC operating lifetest over the last several years. Theprimary failure mode was a decrease in Saturated Drain-Source current (IDSS) and Pinch-off voltage (VP); a device failurewas defined to be a change of more than 20% from the initial value. No significant change in transconductance (gM) wasobserved, at least when measured at zero Gate-Source bias (VGS). Gate-Source breakdown voltage (BVGS) decreasedinitially, but then stabilized throughout the study. For the operating lifetest, a failure was defined as a change of more than±20% in DC bias current IDS.

The results from both types of tests were similar, indicating that the dominant failure mechanism was independentof electric field strength or current density. The failure data from both types of tests was combined to determine anactivation energy of 1.52 eV, with a projected median lifetime (or MTTF) of 1.0 x 108 hours at a channel temperature of120°C. The data showed a dispersion (shape factor) of σ = 0.49, with a projected Instantaneous Failure Rate (IFR) ofless than 10 FITs at the 120°C channel temperature.

The probable degradation mechanism was diffusion of Gate metal into the active layer, commonly known as "gatesinking." Elemental Au, in particular, acts as an acceptor impurity in GaAs, with a ionization energy of 0.09 eV (measuredabove the valence band). The diffusion of metal into the channel can reduce the effective channel thickness, consistentwith a reduction of IDSS and VP. The stability of the transconductance at VGS = 0V indicated that neither the Gate-Sourceparasitic resistance nor the contact resistance had degraded. This finding demonstrated excellent stability of the ohmiccontacts at high temperatures. Transconductance stability at bias conditions other than VGS = 0V was not characterized,nor were any RF parameters measured. Initial changes in breakdown voltage were related to changes in surface defectdensity (trapping sites); this is an example of an “annealing” effect, and does not affect long-term reliability.

MESFET MMIC Reliability

A 10-piece sample of 0.5 µm gate length MESFET-based MMICs was exposed to a step-stress test at baseplatetemperatures of 125, 175, and 225°C for 3600 hours at each temperature. No failures were noted during the 125 or 175°Ctrials, and 2 out of 10 devices failed after 2500 hours during the 225°C trial, which corresponds to a channel temperatureof approximately 245°C. Thus the MTTF at 245°C is at least 2500 hours, and given an acceleration factor of AF = 43,692,the projected MTTF at a channel temperature of 120°C would be at least 1.1 x 108 hours, which is comparable to the resultfor discrete MESFETs, assuming a comparable EA.

FSS MMICs also incorporate TaN thin-film deposited resistors and Si3N4 metal-insulator-metal (MIM) capacitors,which have been exposed to high temperature storage at 250°C for 1000 hours. Observed changes in sheet resistanceand capacitance per unit area were both less than 3%. For a reliability estimate, taking 10% change as the definition of afailure, the MTTF at 250°C should then be at least 3000 hours, and the projected MTTF at 120°C would then be 1.8 x 108

hours, although the activation energy for these two components was not verified.



PHEMT Device Structure

The PHEMT structure used at FSS differs somewhat from the MESFET structure, as shown below:

The PHEMT device features a slimier Gate structure as the MESFET (i.e., the refractory Ti/Pt/Au system), but inthis device the Schottky contact is formed with AlGaAs (the Al mole fraction is <0.3), rather than doped GaAs. Forreduced Gate resistance, the a “mushroom” structure is formed by a direct-write electron-beam lithography process; eachGate section measures 0.25µm at its base. The use of a wider bandgap, less heavily doped contact material provides formore Gate stability at high temperatures over long periods of time. By design, the AlGaAs layer is fully depleted of carriersat zero applied Gate bias, and Drain-Source current flows in the “2-dimensional electron gas” formed at theAlGaAs/InGaAs heterojunction. The Source and Drain ohmic contacts are formed with the identical AuGe/Ni/Au ohmicmetallization system as used in the MESFET. All metallization systems are formed by an evaporation process, withoverplated Au; the devices are passivated as with the MESFETs.

The structure shown above is a Single Heterojunction PHEMT (SHPHEMT), which is a low-noise, low- powerdissipation design. FSS power PHEMT devices utilize a Double Heterojunction PHEMT structure (DHPHEMT), whichfeatures two AlGaAs/InGaAs heterojunctions, one on each side of the InGaAs channel layer. The doping levels, molefractions, and layer thicknesses are based on proprietary designs developed by FSS to provide superior current and powerdensity performance.

AlGaAs / GaAs Superlattice

Undoped GaAs Buffer

InGaAs Channel Layer

N+ AlGaAs Layer (5 x 1017 cm-3)N++ GaAs Contact Layer

DrainContact

SourceContact

Ti / Pt / Au Mushroom Gate

PHEMT STRUCTURE

Undoped AlGaAs Spacer

Heterojunction



Discrete PHEMT Device Reliability

Reliability Study Test Device:

The device selected for the baseline PHEMT reliability study was a discrete DHPHEMT device, the LP7612, whichis a 0.25 x 200 µm, “π-gate” (non-interdigitated) design. This device features the following nominal performance:

RF Output Power at 1dB compression:VDS = 5V, IDS = 50% IDSS, f = 18 GHz +21 dBm

RF Gain at 1 dB compression:VDS = 5V, IDS = 50% IDSS, f = 18 GHz 8.5 dB

Minimum Noise FigureVDS = 2V, IDS = 33% IDSS, f = 18 GHz 1.25 dB

Saturated Drain-Source current, IDSS: 65 mAPinch-Off Voltage at IDS = 1 mA, VP: -0.75 V

Gate-Drain Breakdown Voltageat IGD = 1 mA, BVGD: -9 V

Gate-Source Leakage currentat VGS = -5V, IGSO: 1 µA

The test devices were assembled into hermetically-sealed, ceramic packages, the P-70 stripline package, thereby allowinginsertion into test fixtures for characterization and high-temperature burn-in.

Experimental Protocol:

To establish the basic reliability parameters, a discrete DH-PHEMT wafer was randomly selected from FSS’sstandard production material, and subjected to the usual lot screening procedures. The Lot Acceptance Inspection andQuality Conformance Inspection screening procedures are detailed in FSS’s Applications Notes, Discrete FET/PHEMTDevices, Rev. A, Nov. 1996. A random group of 100 LP7612 devices was taken from this wafer, and subjected to thefollowing screening:

100% DC Parametric Testing (Go / No Go)Visual InspectionDie Attach into P-70 ceramic packagesWire BondLid SealStabilization Bake (200°C for 24 hrs, non-operating)Pre Burn-In DC TestDC Power Burn-In (TCH = 175°C for 168 hrs)Post Burn-In DC TestPost Burn-In RF Test (S21 at 12 GHz)

The primary goal of this effort was to determine the extrapolated MTTF at a 150°C (channel temperature), basedon the assumption that the Arrhenius equation models the dominant failure mechanism. Randomly selected groups of thepackaged LP7612 devices were subjected to high-temperature DC power burn-in, at channel temperatures of 290, 275,268, and 260°C. Channel temperature was achieved by a combination of baseplate temperature and self-heating in thedevices. The LP7612 thermal resistivity had been previously characterized by use of direct-contact liquid crystalthermography. The typical value is 300-310 °C/W (at VDS = 3.0V) at room temperature, and is assumed to rise toapproximately 330°C/W at the temperatures used for this experiment. (The thermal conductivity of GaAs decreases as afunction of temperature due to increased phonon scattering.)



Each temperature group was continuously monitored during the burn-in, and periodically tested at roomtemperature to determine if a failure had occurred. A failure was declared if a device exhibited any change in SaturatedDrain-Source current (IDSS), DC transconductance (gM), or pinch-off voltage (VP) greater than 15%, compared to the initialvalues. Also monitored were: Gate-Drain and Gate-Source breakdown voltages (BVGD, BVGS), leakage current (IGSO) andRF insertion gain at 12 GHz (S21). Bias conditions used for the high temperature burn-in were: VDS = 3.0V, IDS = 30 ± 5mA.

High-Temperature Burn-In Test System:

This test station uses three independent, proportionally-controlled hotplates, each with 10 test positions. All 30test positions are independently controlled by a DC bias system under the overall control of a computer. Custom softwareallows the setting of each test position to a desired drain-source voltage and operating current. This software allows forautomatic polling of all test positions at user-selected intervals during the burn-in. Thus a complete record of eachdevice’s DC characteristics (IDSS, gM, VP, and IGSO) at temperature was kept, although only room temperature DC test datawas used for failure determination. The test devices were mounted with biasing circuits that served to suppress low-frequency oscillations that can occur with high transconductance PHEMTs.

Results:

At the onset of the study, the failure criteria that were established to be as follows:IDSS: > ± 15%gM: > ± 15%

These criteria were selected based on a typical application of this device, as a small-signal gain element. Failures weredeclared when either of these parameters had degraded or changed by more than the stated amount, compared to theinitial (zero time), room temperature values. As discussed previously, all other DC parameters were monitored andmeasured during the course of the burn-in, although they were not used for failure declaration. During the course of theexperiment, it was discovered that the transconductance showed essentially little or no degradation, so this parameter wasnot a factor. The following tables present the cumulative failures as a function of time for each experimental group:

Group #1: T CH = 290°C VDS = 3.0V IDS = 40mABaseplate Temp. = 240 °C Number of Devices: 8

TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)63 2 25126 1 38165 1 50174 1 63262 3 100


TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)195 6 33261 1 39307 1 44349 1 50424 1 56465 2 67727 3 83




TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)769 2 251286 1 381562 2 63


TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)359 1 9656 1 18664 1 271005 2 451013 1 551531 1 641800 1 73

Analysis:

Initial estimates of MTTF and shape factor for each group were made by plotting cumulative failures on log-probability paper, and by graphically determining the best linear fit. This method gave the following results:

GROUP MTTF (hrs) SHAPE FACTOR (σ)TCH = 290°C 150 0.4TCH = 275°C 330 1.0TCH = 268°C 1350 0.7TCH = 260°C 1150 0.8

For a refinement of the MTTF estimates from this graphical method, each group’s results were fitted to the IFR relationshipas given above, and this analysis is presented in the following series of graphs. The comparison between the theoreticalInstantaneous Failure Rate behavior and the actual experimental results serves several purposes: first, the IFRrelationship as presented assumes a single failure mechanism (i.e., no “early” failures), second, the graphically fittedMTTF can be compared to the exact log-normal expression, and lastly the shape factor can be validated.



GROUP #1 TCH = 290°C FITTED IFR

IFR, MTTF=130 HR, SIGMA=0.76

0

0.001

0.002

0.003

0.004

0.005

0.006

0.007

0.008

0.009

25 50 75 100 125 150 175 200 225

TIME (HR)

IFR

(H

R)

GROUP #1 TCH = 290°C AVERAGE FAILURE RATE

AFR

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

63 126 165 174 262

TIME (HR)

AF

R (

HR

)

The peak failure rates are in rough agreement, 0.008 vs. 0.014, but the average rate peaks at 174 hrs. vs. the IFR peak at115 hrs. No significant early failures are apparent.




IFR, MTTF=350 HR, SIGMA=0.99

0

0.0005

0.001

0.0015

0.002

0.0025

0.003

25 125 225 325 425 525 625 725 825

TIME (HR)

IFR

, (H

R)


AFR

0

0.0002

0.0004

0.0006

0.0008

0.001

0.0012

0.0014

0.0016

0.0018

195 261 307 349 443 727

TIME (HR)

AF

R

The IFR peak failure rate is significantly higher than the average rate, 0.0025 vs. 0.0014, but this group may have includedsome early failures. The first monitoring interval at 195 hrs. revealed 6 failed devices, and it is likely that an earliermonitoring time would have resolved the high average rate. The peak rates are at 225 vs. 349 hrs.




IFR, MTTF=1350 HRS, SIGMA=0.72

0

0.0001

0.0002

0.0003

0.0004

0.0005

0.0006

0.0007

0.0008

0.0009

10 250 500 750 1000 1250 1500 1750 2000

TIME (HR)

IFR

(H

R)


AFR

0

0.0001

0.0002

0.0003

0.0004

0.0005

0.0006

0.0007

0.0008

0.0009

769 1286 1562

TIME (HR)

AF

R (

HR

)

The peak average failure rate compares well with the peak IFR, 0.0008 vs. 0.0009, with peak rates at 1250 vs. 1500 hrs.;no average failure rate data was available after 1562 hrs.




IFR, MTTF=1250, SIGMA=0.80

0

0.0001

0.0002

0.0003

0.0004

0.0005

0.0006

0.0007

0.0008

0.0009

5 250 500 750 1000 1250 1500 1750 1800

TIME (HR)

IFR

(H

R)


AFR, TCH=260C

0

0.0001

0.0002

0.0003

0.0004

0.0005

0.0006

0.0007

0.0008

359 660 1009 1531 1800

TIME (HR)

AF

R

The IFR and average failure rate plots are in good agreement, both in terms of peak rates, and peak rate time in hours.No early failures were apparent.



FILTRONIC SOLID STATE RELIABILITYSTUDYLP7612 DISCRETE DHPHEMT ARRHENIUS PLOT

332

3.0E+08

150

1350 1150

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+08

1.0E+09

1.0E+10

1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6

1/T ( x 10 -3 K-1 )

MTTF(hrs)

2.14 eV

290C

275C

268C

260C

150C

DC POWER BURN-INBIAS: V DS=3V IDS=35mADEVICE HOURS: >45,000

EA = 2.14 eV (BEST FIT)

EXTRAPOLATED MTTFAT T CH = 150CFIT RATE = 3.3



MTTF Extrapolation and EA Estimate:

A least-squares linear fit to the results of the four experimental results yields the Arrhenius plot shown on thepreceding page, giving an extrapolated MTTF at TCH = 150°C of 3.0 x 108 hrs, with and Activation Energy estimate of 2.14eV. This MTTF corresponds to a 3.3 FITs average failure or hazard rate.

The Characteristics of PHEMT Aging:

The PHEMT device shows exceptional stability at high temperatures, especially with regard to transconductanceand RF power gain (S21). The majority of the experimental devices showed little or no degradation in gM, and typically lessthan 0.5 dB change in Insertion Gain (S21), which was measured at 12 GHz. It may be inferred from the S21

measurements that the gM vs. VGS characteristic (transfer curve) is stable during aging. If used in a self-biased amplifiercircuit (DC-grounded Gate, DC-floated Source), the additional stabilization of the operating current from the bias resistorswill result in excellent bias point stability. Typical aging effects are shown below on one of the devices from the 275°Cgroup:

TCH = 275C, S/N 9

0

10

20

30

40

50

60

70

80

90

100

0 131 195 261 349 465

TIME (hrs)

GM (mS)

IDSS (mA)

VP (mV)

BVGD (V)

BVGS (V)

IGSO (uA)

This particular device exhibited +0.3 dB of change in S21 over the course of the burn-in, implying stability of the gM at thenominal RF bias point of IDS = 50%IDSS. Most of the experimental devices in the four groups showed an increase in S21

over the duration of the burn-in, typically 0.2 to 0.5 dB (despite significant degradation of the package leads). This gM

stability can be related to the PHEMT’s transconductance expression:

gv Z

d dMsat s

i≅

+ε

where vsat = saturated carrier velocity, Z = Gate width, εS = semiconductor dielectric constant, d+di = AlGaAs layerthickness. The AlGaAs layer thickness is fixed at the time of the epitaxial growth, and to first order, does not change withdevice aging. By contrast, the MESFET expression contains the depletion layer depth as follows:

( )g

v Z

hwhere h

V x V V

q NMsat s s G bi

D≅ ≅

+ +ε ε:

( )2



where h = depletion depth, V(x) = potential along channel, VG = applied Gate voltage, Vbi = Schottky contact built-involtage, q = electron charge, and ND = active layer doping. The gate sinking mechanism can cause localizedcompensation of the MESFET’s active layer doping, thereby altering the ND term. The MESFET is sensitive to anychanges in the depletion layer depth, whatever the cause, whereas the PHEMT fundamentally is less sensitive.

Both devices, however, can exhibit changes in IDSS as channel parameters change, as seen in the followingexpressions:

( )PHEMT Iv Z V

d dMESFET I q v Z a h NDSS

sat s P

iDSS sat bi D: :≅

+≅ −

ε

where: VP = Pinch-Off voltage, a = active layer (channel) depth, and hbi = built-in (zero bias) depletion depth. For thePHEMT, if the pinch-off voltage is dependent on the Schottky contact built-in voltage (and therefore to the barrier height),while the MESFET expression contains dependencies on both the contact properties as well as the active layer doping.(Note that the IDSS of the 275°C sample PHEMT tracks VP closely.)

Hydrogen Sensitivity

FSS LP7612 discretes have been studied as to their sensitivity to molecular hydrogen (H2), a potential concern forhermetically sealed long-duration space flight applications. Amplifiers and linearizers built with LP7612s were exposed tovarious hydrogen concentrations (up to 4%), at elevated temperatures for times exceeding 2,000 hrs. These experimentsdemonstrated that, with suitable circuit topologies (e.g., self-biased), components built with FSS devices could performacceptably over a mission duration of 15 years or more.

S-Level Qualification of PHEMTs

FSS LP7612 PHEMT devices have been repeatedly qualified to MIL-STD-19500 JANS grade, for use in spaceflight hardware. LP7612 discretes are presently “in-flight” on a number of telecommunications satellites. Key elements ofthis qualification procedure included a 240 hour DC operating high-temperature burn-in, and a 1000 hour operating lifetest. Failures were defined as devices exhibiting changes greater ±15% (1000 hour life test) or ±20% (240 hour burn-in) inIDSS, gM, or VP, and ±0.5 dB change in the power gain (S21) at 12 GHz. A separate limit of ±100% or 1 µA (whichever wasgreater) was imposed for the reverse leakage current (IGSS). Samples of the wafer lot under evaluation must complete boththe 240 hour burn-in, at a channel temperature of 225°C, and a 1000 hour life test at a channel temperature of 150°C; thesampling method is based on LTPD (Lot Tolerance Percent Defective) levels of 30% and 50%.

PHEMT MMIC Reliability

MMICs based on the DHPHEMT active device technology are currently undergoing reliability testing at FSS,following the discrete PHEMT results. The LMA411, a two-stage, self-biased, low noise MMIC, has demonstratedexceptional stability at a 275°C channel temperature, with a MTTF exceeding 800 hrs. This channel temperature wasachieved with a 240°C baseplate temperature in addition to self-heating. Operating current changes were less than 5%,and the small-signal gain degraded less than 0.3dB for all test devices. The self-biased circuit topology is resistant tochanges in IDSS and VP, so these results are consistent with the discrete results. All of the test MMICs suffered severephysical deterioration due to the extremely high baseplate temperature; the testing was discontinued after it becameapparent that the package and off-chip components could not withstand the test conditions.



Fabrication Process Stability

All FSS discrete and MMIC devices are fabricated by essentially identical processes. The epitaxial specificationsand evaluation criteria, fabrication processes and test methods, and DC/RF test specifications and test methods are fullydocumented. Statistical Process Control (SPC) methods are utilized to monitor the fabrication processes, with keyparameters continuously tracked on trend charts. The Division is quality certified to ISO 9001 standards. All discrete andMMIC wafers and wafer lots are evaluated and screened by a tailored MIL-19500 JANC screening procedure, as detailedin FSS’s Applications Notes, Discrete FET/PHEMT Devices, Rev. A, November 1986.

Current Reliability Characterization Effort:

FSS is continuing its assessment of the reliability of its devices, and the following experiments are planned:

• Accumulation of additional LP7612 high-temperature Arrhenius data• Reliability of large gate periphery discrete devices• Effects of RF drive (to 1dB compression levels) on reliability• Verification of degradation mechanisms by microscopic analysis (e.g., Auger and SIMS)• Effects of high RF power level exposure, pulsed and CW, to 5W levels

Prepared By:

Michael Jon BaileyProduct Engineering Manager

Reviewed By:

Bill IretonManager of Semiconductor Operations

Discrete FET - PHEMT Devices

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