Design and Implementation of VLSI Systems(EN1600)lecture04

Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Sedra/Prentice Hall, Saint/McGrawHill, Weste/Addison Wesley]

Lecture 03: CMOS fabrication

http://www.appliedmaterials.com/HTMAC/animated.html

Fabricating one transistor

Oxidation(Field oxide)

Silicon substrate

Silicon dioxideSilicon dioxide

oxygen

PhotoresistDevelop

oxideoxide

PhotoresistCoating

photoresistphotoresist

Mask-WaferAlignment and Exposure

Mask

UV light

Exposed Photoresist

exposedphotoresistexposed

photoresist

GGS D

Active Regions

top nitridetop nitride

S DGG

silicon nitridesilicon nitride

NitrideDeposition

Contact holes

S DGG

ContactEtch

Ion Implantation

resis

t

resis

t

resis

t

resis

t

oxox D

G

Scanning ion beam

S

Metal Deposition and

Etch

drainS DGG

Metal contacts

PolysiliconDeposition

polysiliconpolysilicon

Silane gas

Dopant gas

Oxidation(Gate oxide)

gate oxidegate oxide

oxygen

PhotoresistRemove

oxideoxide

RF P

ower

RF P

ower

Ionized oxygen gas

OxideEtch

photoresistphotoresistoxideoxide

RF P

ower

RF P

ower

Ionized CF4 gas

PolysiliconMask and Etch

RF P

ower

RF P

ower

oxideoxideoxideoxide

Ionized CCl4 gas

poly

gat

e

poly

gat

e

RF P

ower

RF P

ower

Top view

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

Wafer preparation

Start with P substrate

1. Spin Resist Coating

2. Expose N Well Mask

3. Develop resist

4. Implant N Well

5. Remove Resist

Anneal wafer to diffuses N well (heal lattice) and grow new oxide layer

Remove oxide from anneal

1. Spin Resist

2. Expose resist with active diffusion mask

3. Develop resist

4. Grow oxide on exposed surface

5. Strip resist

Grown thin oxide over silicon surfaces

1. Deposit poly using Chemical Vapor Deposition (CVD)

2. Spin resist 3. expose resist using the GATE mask 4. develop resist 5. etch poly

Remove thin oxide layer where exposed

1. Spin resist 2. expose with P implant mask 3. develop resist 4. implant P 5. strip resist

1. Spin resist 2. expose with N implant mask 3. develop resist 4. implant N 5. strip resist

Remove resist – anneal wafer – oxide etch

Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4. etch contacts 5. strip resist

1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4. develop resist 5. etch metal 6. strip resist

Rest of metal layers follow similarly

Printing masks

The printerIlluminator optics

Beam line

Excimer laser (193 nm ArF )

Operator console

4:1 Reduction lens NA = 0.45 to 0.6

Wafer transport system

Reticle stage

Auto-alignment system

Wafer stage

Reticle library (SMIF pod interface)

Photolithography is used to print desired patterns on the wafer

UV light

Reticle field size20 mm 15mm,4 die per field

5:1 reduction lens

Wafer

Image exposure on wafer 1/5 of reticle field4 mm 3 mm,4 die per exposure

Serpentine stepping

pattern

The feature size directly depends on the wavelength of your lithographic system

masks

Cross section of a 7-metal layer IC

Next time:How to print different gates?