Design and Implementation of VLSI Systems(EN1600)Lecture08

Prof. Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey/Pearson]

Summary of Shockley model

2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

for nMOS for pMOS

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, ox = 3.9)

polysilicongate

Ideal vs. non-ideal

ideal Non-ideal

Saturation current does not increase quadratically with Vgs

Saturation current lightly increases with increase in Vds

Ideal vs. non-ideal

There is leakage current when the transistor is in cut off

Ids depends on the temperature

Velocity saturation

(V/µm)c = 1.5

n

(m

/s)

sat = 105

Constant mobility (slope = µ)

Constant velocity

At high electric field, drift velocity rolls of due to carrier scattering

Empirically:

Alpha model

0 cutoff

linear

saturation

gs t

dsds dsat ds dsat

dsat

dsat ds dsat

V V

VI I V V

V

I V V

I dsat = Pc¯(Vgs ¡ Vt)®=2

/ 2

2dsat c gs t

dsat v gs t

I P V V

V P V V

Pc, Pv and alpha are found by fitting the model to the empirical modeling results

Channel length modulation

• The reverse-bias p-n junction between drain and body forms a depletion region with a width Ld that increases with Vdb

• Increasing Vds increases depletion width decreases effective channel length increases current

Channel length modulation factor (empirical factor)

n+

p

GateSource Drain

bulk Si

n+

VDDGND VDD

GND

LLeff

Depletion RegionWidth: Ld

Leakage current: subthreshold

n+ n+

p-type body

W

L

tox

polysilicon

gate

Subthreshold conduction

Tunnel current

Junction leakage

Subthreshold leakage is the biggest source in modern transistors 180nm process

0e 1 egs t ds

T T

V V V

nv vds dsI I

2 1.80 eds TI v n = 1.4-15

Leakage current: junction leakage and tunneling

n well

n+n+ n+p+p+p+

p substrate

e 1D

T

V

vD SI I

Junction leakage: reverse-biased p-n junctions have some leakage.Is depends on doping levels and area and perimeter of diffusion regions

Tunneling leakage: Carriers may tunnel thorough very thin gate oxides Negligible for older processes

(and future processes with high-k dielectrics!)

VDD

0 0.3 0.6 0.9 1.2 1.5 1.8

J G (

A/c

m2)

10-9

10-6

10-3

100

103

106

109

tox

0.6 nm0.8 nm

1.0 nm1.2 nm

1.5 nm

1.9 nm

VDD trend

Impact of temperature

• Increases in temperature increases leakage current

• Increases in temperature decreases leakage current

Body effect

Vt is sensitive to Vsb -> body effect

0t t s sb sV V V

2 ln As T

i

Nv

n

sioxsi

ox ox

2q2q A

A

NtN

C

• What is the impact on Vt if we increase/decrease the body bias?

Process variationsBoth MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region

threshold voltage 0.97V threshold voltage 0.57V

Process variations impact gate length, threshold voltage, and oxide thickness

Summary

Ideal transistor characteristics Non-ideal transistor characteristics Inverter DC transfer characteristics Simulation with SPICE and integration with L-Edit