Testing Semiconductor MemoriesLab for Reliable ComputingDept. Electrical EngineeringNational Tsing Hua UniversityCheng-Wen Wu

Cheng-Wen Wu, NTHU

OutlineIntroductionRAM functional fault models and test algorithmsRAM fault-coverage analysisCocktail-March for testing word-oriented memoriesTesting multi-port RAMsTesting CAMsTesting flash memories

Cheng-Wen Wu, NTHU

IntroductionMemory testing is a more and more important issueRAMs are key components for electronic systemsMemories represent about 30% of the semiconductor marketEmbedded memories are dominating the chip yieldMemory testing is more and more difficultGrowing density, capacity, and speedEmerging new architectures and technologiesEmbedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc.Cost drives the need for more efficient test methodologiesIFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.Test automation is requiredFailure analysis, fault simulation, ATG, and diagnosticsBIST/BIRA/BISR generation

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Typical RAM Production FlowWafer

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Scope of RAM TestingParametric Test: DC & ACReliability ScreeningLong-cycle testingBurn-in: static & dynamic BIFunctional TestDevice characterizationFailure analysisFault modelingSimple but effective (accurate & realistic?)Test algorithm generationSmall number of test patterns (data backgrounds)High fault coverageShort test time

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RAM ModelsBehavior LevelVerilog/VHDLFunction LevelVerilog/VHDL/Block diagramNormally not synthesizableCircuit LevelSpice/SchematicLayout LevelGDS-II/GeometryWho should provide the model?

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Memory Function Model Example

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RAM Fault Models (Static)Address-Decoder Fault (AF)No cell accessed by certain addressMultiple cells accessed by certain addressCertain cell not accessed by any addressCertain cell accessed by multiple addressesStuck-At Fault (SAF)Cell (line) SA0 or SA1Transition Fault (TF)Cell fails to transit from 0 to 1 or 1 to 0

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RAM Fault Models (Static)Bridging Fault (BF)Short between cellsAND type or OR type Stuck-Open Fault (SOF)Cell not accessible due to broken lineNeighborhood Pattern Sensitive Fault (NPSF)Active (Dynamic) NPSFPassive NPSFStatic NPSF

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N

W

BC

E

S

RAM Fault Models (Static)Coupling Fault (CF)State Coupling Fault (CFst)Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given stateInversion Coupling Fault (CFin)Transition in coupling cell complements (inverts) coupled cellIdempotent Coupling Fault (CFid)Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0

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RAM Fault Models (Dynamic)Recovery Fault (RF)Sense Amplifier Recovery Fault (SARF)Sense amp saturation after reading/writing long run of 0 or 1Write Recovery Fault (WRF)Write followed by reading/writing at different location resulting in reading/writing at same locationWrite-after-write recovery faultRead-after-write recovery faultResults in functional faults---detected at high speed (e.g., GALROW/GALCOL)Disturb Fault (DF)Victim cell forced to 0 or 1 if we read or write aggressor cell (may be the same cell)

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RAM Fault Models (Dynamic)Data Retention Fault (DRF)DRAMRefresh FaultRefresh-Line Stuck-At FaultLeakage FaultSleeping Sickness---loose data in less than specified hold time (typically tens of ms)SRAMLeakage FaultStatic Data Losses---defective pull-upCheckerboard pattern triggers max leakageBIST good for sync with refresh mechanism

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Test Time Complexity (100MHz)

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Size

N

10N

NlogN

N1.5

N2

1M

0.01s

0.1s

0.2s

11s

3h

16M

0.16s

1.6s

3.9s

11m

33d

64M

0.66s

6.6s

17s

1.5h

1.43y

256M

2.62s

26s

1.23m

12h

23y

1G

10.5s

1.8m

5.3m

4d

366y

4G

42s

7m

22.4m

32d

57c

16G

2.8m

28m

1.6h

255d

915c

RAM Test AlgorithmA test algorithm (or simply test) is a finite sequence of test elementsA test element contains a number of memory operations (access commands)Data pattern (background) specified for the Read operationAddress (sequence) specified for the Read and Write operationsA march test algorithm is a finite sequence of march elementsA march element is specified by an address order and a number of Read/Write operations

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Classical Test AlgorithmsZero-One Algorithm [Breuer & Friedman 1976]Also known as MSCANFor SAFSolid background (pattern)Complexity is 4N

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Classical Test AlgorithmsCheckerboard AlgorithmZero-one algorithm with checkerboard patternComplexity is 4NFor SAF and DRF

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1

0

1

0

1

0

1

0

1

Classical Test AlgorithmsGalloping Pattern (GALPAT)Complexity is 4N**2---only for characterizationAll AFs,TFs, CFs, and SAFs are located1. Write background 0;2. For BC = 0 to N-1 { Complement BC; For OC = 0 to N-1, OC != BC; { Read BC; Read OC; } Complement BC; }3. Write background 1;4. Repeat Step 2;

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BC

Classical Test AlgorithmsSliding (Galloping) Row/Column/DiagonalBased on GALPAT, but instead of a bit, a complete row, column, or diagonal is shiftedComplexity is 4N**1.5

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1

1

1

1

1

Classical Test AlgorithmsButterfly AlgorithmComplexity is 5NlogN1. Write background 0;2. For BC = 0 to N-1 { Complement BC; dist = 1; While dist

Classical Test AlgorithmsMoving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976]For functional and AC parametric testFunctional (13N): for AF, SAF, TF, and most CFParametric (12NlogN): for Read access time2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bitRepeat T2~T5 for each address bitGALPAT---all 2-address sequences

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Classical Test AlgorithmsSurround Disturb AlgorithmExamine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows1. For each cell[p,q] /* row p and column q */ { Write 0 in cell[p,q-1]; Write 0 in cell[p,q]; Write 0 in cell[p,q+1]; Write 1 in cell[p-1,q]; Read 0 from cell[p,q+1]; Write 1 in cell[p+1,q]; Read 0 from cell[p,q-1]; Read 0 from cell[p,q]; }2. Repeat Step 1 with complementary data;

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Classical Test AlgorithmsZero-one and checkerboard algorithms do not have sufficient coverageOther algorithms are too time-consuming for large RAMTest time is the key factor of test costComplexity ranges from N2 to NlogNNeed linear-time test algorithms with small constantsMarch test algorithms

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March TestsZero-One (MSCAN)Modified Algorithmic Test Sequence (MATS) [Nair, Thatte & Abraham 1979]OR-type address decoder faultAND-type address decoder faultMATS+ [Abadir & Reghbati 1983]For both OR- & AND-type AFs and SAF

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March TestsMarching 1/0 [Breuer & Friedman 1976]For AF, SAF, and TFMATS++ [Goor 1991]Also for AF, SAF, and TFComplete and irredundant

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March TestsMarch XFor AF, SAF, TF, & CFinMarch C [Marinescu 1982]For AF, SAF, TF, & all CFs---redundantMarch C- [Goor 1991]Also for AF, SAF, TF, & all CFs---irredundant

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March TestsLimitationsSequential faults in address decodersRFNPSF(9N-2) for 2-CF [Marinescu 1982](2NlogN+11N) for 3-CF [Cockburn 1994]SolutionsAddress sequence variationHoppingPseudorandom

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Coverage of March Tests Extended March C- (11N) has a 100% coverage of SOF

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MATS++

March X

March Y

March C-

SAF

1

1

1

1

TF

1

1

1

1

AF

1

1

1

1

SOF

1

.002

1

.002

CFin

.75

1

1

1

CFid

.375

.5

.5

1

CFst

.5

.625

.625

1

Testing Word-Oriented RAMBackground bit is replaced by background wordMATS++:Conventional method is to use logm+1 different backgrounds for m-bit wordsm=8: 00000000, 01010101, 00110011, and 00001111Apply the test algorithm logm+1=4 times, so complexity is 4*6N/8=3N

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Cocktail-March AlgorithmsMotivation:Repeating the same algorithm for all logm+1 backgrounds has redundancyDifferent algorithm targets different faultsApproach:Use multiple backgrounds in a single algorithm runMerge and forge different algorithms and backgrounds into a single algorithmGood for word-oriented memories

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March-CWAlgorithm:March C- for solid background (0000)Then a 5N March for each of other standard backgrounds (0101, 0011):Result:Complexity is (10+5logW)N, where W is word length and N is word countTest time is reduced by 39% if W=4, as compared with extended March C-Improvement increases as W increases

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Comparison (Full Coverage)

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Testing NPSFNPSF test approachesTilingMulti-background marchEasy BIST implementation5-cell neighborhood

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NPSF ModelsStatic NPSF (SNPSF)BC forced to a certain state due to a certain deleted neighborhood (DN) patternPassive NPSF (PNPSF)BC frozen due to a certain DN patternActive NPSF (ANPSF)BC content changes due to a change in DN patternChange: a transition in one DN cell, with other DN cells & BC containing a certain patternAssumptions:Single NPSFAddress scramble table is availableMemory is bit-orientedWord-oriented memory is tested as multiple bit-oriented ones

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Test StrategyMulti-Background MarchTo generate all neighborhood patternsSolid BG(FC < 30%)Another BG

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Testing PNPSFMarch 17N:

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Data Background Generation Data backgroundsBG1: all zeroBG2: Ar[0], LSB of row addressBG3: Ar[1], second bit of row addressBG4: Ar[0]Ar[1]

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Testing ANPSFMarch 12N:

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Time Complexity12 N/BG X 8 BG = 96NDetects all NPSFs

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Multi-Port MemoriesPopular architecturesk-port (k > 1)n-read-1-writeFIFO

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2-Port Topology

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Inter-Port Word-Line Short* Functional test complexity: O(N3)

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Inter-Port Bit-Line Short* Functional test complexity: O(N2)

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Address Scrambling

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Reading Neighboring CellsRead neighboring cells to detect inter-port faults: rN, rS, rE, and rW

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TAGS-PS

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Dual-Port RAM Test

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Compacted Dual-Port RAM Test* Time complexity: 10N

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Four-Port RAM Test* Time complexity: 17N

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Testing 6-Read-1-Write RAM* Time complexity: 13N

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Flash Memory TestingTesting nonvolatile memories:Masked ROM---exhaustive; pseudorandomPROM (OTP) & EPROM---dummy rowEEPROM & flash memory---dummy row?Testing flash memory core is hardCustomized core and I/OIsolation (accessibility)Reliability issues: disturbances, over program/erase, under program/erase, data retention, cell endurance, etc.Long program/erase time

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Flash Memory OverviewFlash memory can be programmed and erased electrically Has the advantages of EPROM and EEPROMA stacked gate transistor with both the control gate (CG) and floating gate (FG):GDSP-Sin+n+SourceDrainControl gateFloating gate

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Flash Memory Program & EraseProgramErase Program(1 to 0): channel hot-electron (CHE) injection or Fowler-Nordheim (FN) electron tunneling Erase (0 to 1): FN electron tunneling By the entire chip or large blocks (flash erasure) Different products have different program/erase mechanisms

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Flash Memory Cell TypesStacked-gate Split-gate Select-gate

Operations: Read, Program, Erase (Flash Erase)As opposed to Read and Write in RAM

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Programming Scheme Comparison

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CHE Injection

Channel FN Tunneling

High power (dual external supplies)

Low power (single external supply)

Low oxide field stress

High oxide field stress

Faster program operation (byte program limited by power)

Slower program operation (improved by page program)

NOR-Array Structure

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NAND-Array StructureSelect (drain)Select (source)WL 1WL 2WL 3WL 4WL 16BL i

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Disturbance Example (I)NOR-Type Common Ground Standard (Stacked Gate)

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Disturbance Example (II)

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Disturbance Example (III)

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Disturbance Example (IV)

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Gate Program Disturb Fault (GPDF)Conditions:1.Victim cell initial value is a logic 12.Aggressor 10 (program) Victim 10 (program)

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Gate Erase Disturb Fault (GEDF)V(H)V(H)V(L)V(L)V(Gd)Conditions:1.Victim cell initial value is a logic 02.Aggressor 10 (program) Victim 01 (erase)

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Drain Program Disturb Fault (DPDF)V(H)V(H)V(L)V(Gd) During programming, erased cells on unselected rows on a bit-line that is being programmed may have a fairly deep depletion region formed under them Electrons entering this depletion region can be accelerated by the electric field and injected over the oxide potential barrier to adjacent floating gatesConditions:1.Victim cell initial value is a logic 12.Aggressor 10 (program) Victim 10 (program)

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Drain Erase Disturb Fault (DEDF)V(H)V(H)V(L)V(L)V(Gd)Conditions:1.Victim cell initial value is a logic 02.Aggressor 10 (program) Victim 01 (erase)

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Read Disturb Fault (RDF)Conditions:1. Occurs on the selected cell2. Cell initial value is logic 1Soft-Program During the read operation,hot carriers can be injectedfrom the channel into the FGeven if at low gate voltages

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Over Erase Fault (OEF)Flash memory erase mechanism is not self-limitingThreshold voltage can be low enough to turn the cell into a depletion-mode transistorFault behavior:An unselected cell in the same bit-line has excessive source-drain leakage currentReading that cell leads to incorrect value (like DEDF)Cannot be programmed correctly (like TF)

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Basic RAM Faults for Flash MemoryAddress-Decoder Fault (AF) Stuck-At Fault (SAF) Transition Fault (TF) Stuck-Open Fault (SOF) Bridging Fault (BF)Coupling faults need not be considered!Replaced by disturb faults

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Reliability ConsiderationReliability characteristics of floating-gate ICs depend onCircuit density, circuit design, and process integrityMemory array type and cell structureReliability stressing and testing must then be oriented toward determining the relevant failure rates for the particular array under consideration

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Data Retention FaultRetention time: the time from data storage to the time at which a verifiable error is detected from any causeIntrinsic retention times exceed millions of years in the operating temperature rangeMonths at 300C1 million years at 150 C120 million years at 55 CData Retention Fault (DRF)Static leakageBuilt-in data retention test circuit

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Cell Endurance FaultEndurance: a measure of the ability to meet data-sheet specifications as a function of accumulated program/erase cyclesEndurance limit is a result of damage to the dielectric around the floating gate caused by electric stressesIn many flash devices, the end of endurance is generally caused by hot electron trapping in the charge transport oxideCell Endurance Fault (CEF)Threshold window shift due to increased program/erase cyclesBuilt-in stress test circuit

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Composite Failure Rate Determination125C dynamic life stressThe 125C dynamic life stress is the standard MOS memory continuous dynamic read in a burn-in chamberEndurance testThe endurance test is the repeated data complementing of floating-gate devices, possibly at temperature extremesExtended data retention stressThis test is constituted by a high-temperature bake with a charge polarity that is opposite to the equilibrium state on the floating gate

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Typical Test Modes (Characterization)Stress (row/column)Reverse tunneling stressPunch through stressTox stressDC stressMass programWeak eraseLeak (thin-oxide, bit-line, etc.)Cell current; cell VtMarginEtc.

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Test PatternsA RAM test pattern definition includes both the data pattern and the address patternThe time to read a pattern is the same as the time to write a patternFor flash memories, however, the address and data pattern definitions must be segregatedIt has long write times relative to the read timesTypical data patterns:Solid, checkerboard, random, etc.Typical address patterns:Address increment/decrement, address complement, column/diagonal galloping, etc.

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Testing GPDFFlashProgram the first columnRead all cells except the first columnFlashProgram any column except the firstRead the first column*Assume reading and programming are done column-wiseSource: Saluja, et al., Int. Conf. VLSI Design, 2000

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Testing GEDFFlashProgram all cellsRead all cells except the last columnProgram any column except the lastRead the last column*Assume reading and programming are done column-wiseSource: Saluja, et al., Int. Conf. VLSI Design, 2000

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Test Coverage: Previous ResultsSource: Saluja, et al., Int. Conf. VLSI Design, 2000

FaultDCPDCEDDEFGFSAF50%50%50%100%100%TF12.5%50%50%87.5%62.5%AF40%0%0%44.5%40%SOF0%0%0%12.5%6.2%CFst25%25%25%50%50%GPDF33.3%0%0%100%33.3%GEDF0%100%75%100%100%DEDF0%75%100%100%100%DPDF0%0%0%0%0%

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March-Based Flash Test: March-FT{(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)}

This Flash memory is NOR type (Stacked gate).Memory size (N) : 65536Test length : 2(chip erase time) + 131072(word program time) + 393216(word read time)Test time : 7.207173 secSAF : 100%(131072 / 131072)P.S.TF : 100%(131072 / 131072) Flash Type = NORSOF : 100%(65536 / 65536) Gate Type = StackAF : 100%(4294901760 / 4294901760) Row Number = 256CFst : 100%(17179607040 / 17179607040) Col Number = 256GPD : 100%(16711680 / 16711680) Word Length = 1GED : 100%(16711680 / 16711680) Chip erase time = 3 secDPD : 100%(16711680 / 16711680) Word program time = 9u secDED : 100%(16711680 / 16711680) Word read time = 70n secRD : 100%(65536 / 65536)OE : 100%(65536 / 65536)

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Test Length (Bit-Oriented)Notation:F : Flash timeP : Program timeR : Read timer : row numberc : column number

DCP2(F) + 2r(P) + rc(R)DCE(F) + (c+1)r(P) + rc(R)DD(F) + (r+1)c(P) + rc(R)EF2(F) + (rc+2r+c-2)(P) + (2rc+r+c-3)(R)GF2(F) + (rc+2r+c-1)(P) + (2rc+c+r-2)(R)FT2(F) + 2rc(P) + 6rc(R)

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Test Length (Word-Oriented)Word length = w:2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)]

Solid: 0000 (1111)Standard: 0101 (1010), 0011 (1100)Ex: word length w = 46(F) + 4rc(P) + 8rc(R)solid backgroundtesting timestandard backgroundtesting time

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Test Algorithm Generation by Simulation (TAGS)

T(N)Test algorithms2N3N4N5N6N7N8N9N10N(f); (r1)(f); (w0); (r0)(f); (r1,w0); (r0)(f); (r1,w0,r0); (r0)(f); (r1,w0,r0); (r0,w0)(f); (r0); (r1,w0,r0); (r0,w0)(f); (r1,w0); (f); (r1,w0,r0); (r0)(f); (r1,w0); (r0); (f); (r1,w0,r0); (r0) (f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)

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Embedded Memory TestingMemories are one of the most universal coresIn Alpha 21264, cache RAMs represent 2/3 transistors and 1/3 area; in StrongArm SA110, the embedded RAMs occupy 90% area [Bhavsar, ITC-99]In average SOC, memory cores will represent more than 90% of the chip area by 2010 [ITRS 2000]Embedded memory testing is increasingly difficultHigh bandwidth (speed and I/O data width)Heterogeneity and pluralityIsolation (accessibility)AC test, diagnostics, and repairBIST is considered the best solution

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Embedded RAM Test Support

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Test run

Isolation only

Isolation & BIST

Probe test

Tester

Tester/BIST

Pre-BI test

Tester

BIST

BI

BI board

BIST

Post-BI test

Tester

BIST

Final test

Tester

Tester/BIST

RAM BIST ApproachesMethodologyProcessor-based BISTProgrammableHardwired BISTFastCompactInterfaceSerial (scan, 1149.1)Parallel (embedded controller; hierarchical)Patterns (address sequence)MarchPseudorandom

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Typical RAM BIST Architecture

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Serial March (SMarch)From March C-Serial interfaceOne BIST for all (cascaded)One-bit read/write at a time, but one pattern per cycleSlowNo diagnosticsSource: Nadeau-Dostie et al., IEEE D&T, Apr. 1990

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Syntest MBISTAlgorithms:March C-MOVIMarch C++CheckerboardShared controller for multiple RAMsSynthesizable RTL codeFSMData GeneratorAnalyzerADR ControlCEOEWEBADQPassBistFailFinishSource: Syntest

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NTHU/GUC EDO DRAM BIST

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DRAM Page-Mode Read-Write Cycle

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Programmable Memory BIST (PMBIST)

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PMBIST Architecture

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Controller and SequencerControllerMicroprogramHardwiredShared CPU coreIEEE 1149.1 TAPSequencer (Pattern Generator)CounterLFSRLUT

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Controller

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Sequencer

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PMBIST Test ModesScan-Test ModeRAM-BIST ModeFunctional faultsTiming faults (setup/hold times, rise/fall times, etc.)Data retention faultsRAM-Diagnosis ModeRAM-BI Mode

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PMBIST Controller Commands

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Bit 4

Addressing order

Bit 3

Data type

Bit 2, Bit 1, Bit 0

Operations

1: ( (increasing)

1: d = DB

000: EOT

(End of test)

0: ( (decreasing)

0: d = ~DB

001: Rd

(READ Cycle)

010: Wd

(Early WRITE Cycle)

011: RdW~d

(READ-WRITE) Cycle

EDO-PAGE-MODE

100: Wd

(Early WRITE Cycle

101: RdW~d

(READ-WRITE) Cycle

110: RdW~dR~d

(READ Early WRITE Cycle)

111: Refresh

PMBIST Control Sequence

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BIST Area Overhead3%0.3%OverheadMem size

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Processor-Based RAM BISTProcessor

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On-Chip Processor-Based RAM BISTBIST program is stored in boot ROM during design phase, and memory BIST is done by executing BIST program

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Testing RAM Core by On-Chip CPU6502 assembly program that performs March C- test algorithm.org0HFF00LDX#$$00LDA#$$55

M0:STA0000,XINXCPX#$$FFBNEM0LDX#$$00

M1:LDA0000,XCMP#$$55BNEERRORLDA#$$AASTA0000,XINXCPX#$$FFBNEM1LDX#$$00 . . . . .data backgroundwrite data background to memoryread from memorywrite data background to memory

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Test Speed ConsiderationProcessor-BIST speed is lower than dedicated BIST circuitTotal clock cycles to implement MARCH C- is O(114N)Table 1. 6502 instruction cycles

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IMM

ABX

IMP

REL

LDA

2

4

-

-

LDX

2

-

-

-

STA

-

4

-

-

INX

-

-

2

-

CPX

2

-

-

-

BNE

-

-

-

2~4

CMP

2

-

-

-

NTHU Processor-Programmable BIST

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Advantages and DisadvantagesAdvantagesReuse of on-chip CPU coreMight need modificationCore March elements can be implemented in hardware, allowing different March algorithms to be executed via assembly programmingDisadvantagesSome address space will be occupied by PPBISTArea overhead

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PPBIST Implementation

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PPBIST Data Registers

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Register

Function

RBG

Store background data

RAL

Store lowest address

RAH

Store highest address

RME

Store current March element

RIR

Instruction register

RFLAG

Status register

RED

Erroneous response of defective memory cell

REA

Address of defective memory cell

PPBIST Test ProcedureCPU write data back groundCPU write start/stop addressCPU write MARCH element instructionCPU write START instruction to wrapperBIST core(R0W1)BIST core(R1W0)BIST core(R0W1)BIST core(R1W0)BIST core(W0)BIST core(R0)compare error?complete?write error flagwrite faulty addresswrite faulty datawrite complete flagyesyesnonoCPU take over

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PPBIST Example Using 65026502 assembly program that performs March C- test algorithm under the proposed BIST scheme

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PPBIST ExampleAddresses of the registers in the BIST experimentMarch elements and the corresponding RME

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Register

Address

RBG

FFE0

RAL

FFE1 ~ FFE2

RAH

FFE3 ~ FFE4

RME

FFE5

Register

Address

RIR

FFE6

RFLAG

FFE7

RED

FFE8

REA

FFE9 ~ FFEA

M0

M1

M2

M3

M4

M5

0H

1H

2H

3H

4H

5H

Experimental ResultsTotal test time in terms of clock cyclesThe sum of all the March elements' test time plus 30 clock cycles10N clock cycles to perform March C-Test time of each March element :

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M0

M1

M2

M3

M4

M5

1N

2N

2N

2N

2N

1N

Comparison of BIST Methodologies

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BIST scheme

Test time

H/W overhead

Routing overhead

Integrated BIST core

Short

Low

High

On-chip processor

Very long

Zero

Zero

Ours

Short

Very low

zero

RAM BIST CompilerUse of RAM cores is increasing.SRAM, DRAM, flash RAMMultiple coresRAM BIST compiler is the trend.BRAINS (BIST for RAM in Seconds)Proposed BIST ArchitectureMemory ModelingCommand Sequence GenerationConfiguration of the Proposed BIST

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BRAINS OutputsSynthesizable BIST designAt-speed testingProgrammable March algorithmsOptional diagnosis supportBISDActivation sequenceTest benchSynthesis script

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BIST Synthesis Flow

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NTHU/GUC PMBIST Architecture

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PMBIST with ScanSource: Cheng, et al., DFT00

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Controller

Sequencer

TestPatternGenerator

Test Command/Information Storage Module

Serial data in

Serial data out

Error

Error

ToMemory

Address

BISTcontrol signals

MemoryCommand

Command

Hand-shaking

SequencerControlModuleAddress GeneratorSequence GeneratorCommand GeneratorError Handling Moduleaddresscommanderrorinfo.goerrorsignature

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State Diagram of Control ModuleBISTapplyBISTdoneBISTidleBISTapplyBISTdoneBISTidleBISTactiveFor DRAMFor SRAM

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DRAM Page-Mode Operation

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Memory Specification TechniquesMemory SpecificationsI/O SpecificationCommand SpecificationTask SpecificationDelay Constraint SpecificationAC Parameter SpecificationSupport customized memories.

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I/O SpecificationFour parameters IO_type IO_width IO_latency IO_packet_lengthIO_type: input, output, or inoutIO_width: port width (#bits), can be a constant or specified by user

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I/O SpecificationIO_latency: port latency

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I/O ModelingIO_packet_length: #bits packed within a clock cycle for the port

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Command SpecificationSpecifies the memorys instructions

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Task SpecificationSpecifies a complete memory operationA task can be a single command or a sequence of commands.

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Delay Constraint SpecificationSpecifies the minimal time interval between any two tasks

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AC Parameter SpecificationSpecifies input and output delaysSpecified parameters will be inserted into the synthesis script.

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Memory Specification ExampleFor ZBT SRAM:Method A:@latency D = 1;@task write = {write};Method B:@latency D = 0;@task write = {pre_write, post_write};The BIST circuit from method A is faster than the one from method B, but it has higher area overhead

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Sequence GenerationFor each March element, the compiler generates the command sequence according to the read task, write task, and minimum delay between the two tasksFor example: task read = {A}task write = {B, C}minimum delay between read and write = 10nsclock period = 10 nsThen the (rw) element becomes {A, nop, B, C}One can also optimize the command sequence

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Fast Access Mode

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Diagnosis SupportThe BIST circuit scans out the error information (element, address, signature, and polarity) during the diagnosis mode.Assume address 20h stuck-at 64h:

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Multiple RAM CoresController and sequencer can be shared. controllerTest pattern generatorTest pattern generatorsequencerRam Core ARam Core BRam Core CTest pattern generatorsequencer

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Experimental ResultsThe Built-In Memory ListDRAMEDO DRAMSDRAMDDR SDRAMSRAMSingle-Port Synchronous SRAMSingle-Port Asynchronous SRAMTwo-Port Synchronous Register FileDual-Port Synchronous SRAMMicron ZBT SRAMBRAINS can support new memory architecture easily

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Experimental Results

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Experimental ResultsFour single-port SRAM BIST circuits share the same controller and sequencer.Size of the SRAM core: 8K x 16OriginalBIST area for single-port SRAM: 1438 (gates)Total area = 1438 * 4 = 5752 (gates)

Sharedgate count: 3350

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Experimental Results8K x 16 single-port synchronous SRAM (0.25um)Area:Die size: 1780.74 x 755.07 um2BIST area: 80.1 x 583.48 um2 Area overhead : 3.4%

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Experimental Results2K x 32 two-port register file (0.25um)Die size: 1130.74 x 936.34 um2BIST area: 77.88 x 620 um2Area overhead: 4.5%

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Why RAM Diagnostics?Memory testing is more and more importantMemories are key componentsRepresent about 30% of the semiconductor marketDominate the chip area/yieldMemory testing is more and more difficult Growing density, capacity, and speed Emerging new architectures & technologies Growing need for embedded memoriesWhy diagnostics?Yield improvementRepair and/or design/process debugging

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Fault Model Subtypes

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NTHU-FTC BIST Architecture

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Test ModeIn Test Mode it runs a fixed algorithm for production test and repairOnly a few pins need to be controlled, and BGO reports the result (Go/No-Go)

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Fault Analysis ModeIn Fault Analysis Mode, we can apply a longer March algorithm for diagnosisFSI captures the error information of the faulty cellsEOP format:

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Error Catch and AnalysisLocate the faulty cellsIdentify the fault types

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How to Identify Fault Type?RAM Circuit/LayoutTester/BIST Output

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March DictionaryMarch 11N E0E1 E2E3E4 E5E6 E7E8 E9E10

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March Signature and Error MapMarch Signature (Syndrome)Error Map

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MECA System

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Error Analyzer

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Fault AnalysisDerive analysis equations from the fault dictionaryConvert error maps to fault maps by the equations

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Test Algorithm GenerationStart from a base test: generated by TAGS or user-specifiedGeneration options reduced to read-insertions

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Diagnostic ResolutionDiagnostic resolution

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Experimental ResultsProposed diagnosis framework has been applied to commercial embedded SRAMsResults for a 16Kx8 embedded SRAM (FS80A020) are shownTester log from Credence SC212 is examinedAddress remapping (logical to physical) is applied

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The Total Error Bitmap

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Fault BitmapsIdempotent Coupling FaultStuck-at 0

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Redundancy and RepairProblem: We keep shrinking the feature size and increasing the chip density and size. How do we maintain the yield?Solutions:FabricationMaterial, process, equipment, etc.DesignDevice, circuit, etc.Redundancy and repairOn-line EDAC (extended Hamming code; product code)Off-lineSpare rows and/or columns

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From BIST to BISRBISTBISDBIRABISRBIST: built-in self-testBIECA: built-in error catch & analysisBISD: built-in self diagnosisBIRA: built-in redundancy analysisBISR: built-in self-repair

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RAM Built-In Self-Repair (BISR)

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RAM Redundancy1-D: spare rows (or columns) onlySRAMAlgorithm: Must-Repair2-D: spare rows and columnsLocal and/or global sparesNP-complete problem Conventional algorithm:Must-Repair phaseFinal-Repair phaseRepair-Most (greedy) [Tarr et al., 1984]Fault-Driven (exhaustive, slow) [Day, 1985]Fault-Line Covering (b&b) [Huang et al., 1990]

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Redundancy Architectures

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An SRAM with BISR[Kim et al., ITC 98]

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A DRAM Redundancy Example

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DefinitionsFaulty line: row or column with at least one faulty cell.A faulty line is covered if all faulty cells in the line are repaired by spare rows and/or columns.A faulty cell not sharing any row or column with any other faulty cell is an orthogonal faulty cell.r: number of (available) spare rowsc: number of (available) spare columnsF: number of faulty cells in a blockF:number of orthogonal faulty cells in a block

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Example Block with Faulty Cells

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Repair-Most (RM) Run BIST and construct bitmap. Construct row and column error counters. Run Must-Repair algorithm. Run greedy Final-Repair algorithm.

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Worst-Case Bitmap (After Must-Repair)Max F=2rc.Max F=r+c.Bitmap size: (rc+c)(cr+r).

Cheng-Wen Wu, NTHU

Local Repair-Most (LRM)RM is not good enough for embedded RAM.Large storage requirement: bitmap and countersSlowLRM improves the performance.Repair-Most basedImproved heuristicsEarly termination rules Concurrent BIST and BIRANo separate Must-Repair phaseLRM reduces the storage required.Smaller local bitmapFrom (rc+c)x(cr+r) to mxn

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LRM AlgorithmActivated by BIST whenever a faulty cell is detected.Fault Collection (FC)Collects faulty-cell addresses.Constructs local bitmap.Counts row and column errors.Spare Allocation (SA)Allocate spare rows or columns when bitmap is full.Allocate spare rows or columns at end.

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LRM: FC and SA

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LRM Example(5,2)(5,4),(5,6),(5,7)(7,3)

Cheng-Wen Wu, NTHU

Local Optimization (LO)LMR has drawbacks:Selecting line with largest fault count may be slow.Multiple lines may need to be selected for repair.Area overhead is still high.Repair rate depends on bitmap size.LO has a better repair rate based on same hardware overhead, i.e., a higher repair efficiency.Fault Collection (FC)Records faulty cells in bitmap until it is full.Spare Allocation (SA)Exhaustive search performed for repairing all faults.Bitmap cleared; process repeated until done.

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LO: Column*/Row Selection for SAA 1 means that the correspondingcol is selected for repair, unless empty.* Assume column selection has a lower cost than row selection.

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LO Example

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Essential Spare Pivoting (ESP)Maintain high repair rate without using a bitmap.Small area overhead.Fault Collection (FC)Collect and store faulty-cell address using row-pivot and column-pivot registers.If there is a match for row (col) pivot, the pivot is an essential pivot.If there is no match, store the row/col addresses in the pivot registers.If F > r+c, the RAM is unrepairable.Spare Allocation (SA)Use row and column pivots for spare allocation.Spare rows (cols) for essential row (col) pivots.SA for orthogonal faults.

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ESP Example

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Cell Fault Size DistributionMixed Poisson-exponential distribution.

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Repair Rate Comparison1,552 RAM blocks.1,024x64 bits per block.r from 6 to 10.c from 2 to 6.LRM bitmap: rxc.LO bitmap: 8x4.

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Normalized Repair Rate

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Repair Rate (r=10)

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Normalized Repair Rate (r=6)

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Area OverheadOverhead is about 5-12% for 16Mb DRAM, r=8, and c=4.

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Computation Time (Simulated)

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Cheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUThis is an outline for the major areas of your presentation -- what youre going to talk about. You should not include the title, introduction or conclusion in your outline. Just highlight the major areas of your talk.Cheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHUCheng-Wen Wu, LARC, NTHU