Collaborate to Innovate FinFET Design Ecosystem Challenges...

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Collaborate to Innovate –

FinFET Design Ecosystem

Challenges and Solutions

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Agenda

Lifestyle Trends Drive Product Requirements

Concurrent Technology and Design Development

FinFET Design Challenges

FinFET Ecosystem Solutions

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Agenda





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Augmented Reality

Image: zh.wikipedia.org Image: public-domain-images.com

Mobile Convergence

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Ubiquitous Connectivity Internet of Things

Image: FreeDigitalPhotos.net

Cloud Computing

Future Lifestyle Trends

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Augmented Reality

Mobile Convergence


Cloud Computing

Service availability

Bandwidth

Battery life

Connectivity

Reliability

Battery life

Cost

Latency

Throughput

Performance/ W/ $

Service availability

Latency

Bandwidth

Battery life

Connectivity

Integration

Battery life

Form factor

Enabling Product Requirements

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Augmented Reality

Mobile Convergence


Cloud Computing

Wireless Transceiver

Power Management

Micro-controller


Power Management

Power Management

CMOS Image Sensor


Pico Projector

Gyroscope

Accelerometer

Power Management

CMOS Image Sensor


Power Management

Accelerometer

Gyroscope

E-Compass

Enabling Product Functionality

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Design Collaboration to Reduce New

Technology Challenges D

esig

n C

hall

en

ges

Low Power

High K

Metal Gate

Double

Patterning

FinFET

Transistor

65nm 40nm 28nm 20nm 16nm 10nm

Multi-Patterning & Spacer

Design

Enablement

To Lower

Design

Barriers

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Increasing EDA Tools and Feature Sets

to Enable Customer Designs

65 nm 40nm 28nm 20nm 16nm

DRC LVS RCX APR STA

Simulator Custom

DRC

DFM

DRC DRC DRC

IR/EM

LVS

RCX

APR

STA

IR/EM

Simulator Custom

LVS

RCX

DFM

APR

IR/EM

Simulator Custom

STA

LVS

RCX

DFM

APR

IR/EM

Simulator

Custom

STA

LVS

RCX

APR

STA

IR/EM

Simulator

Custom

DFM

Number of Supported EDA Tools and Features by Process Node

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Agenda





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Customer

Product

Launch

Backend Service

Wafer Fabrication

Mask Making / OPC Design

Service

Process Definition

EDA Enablement

IP Enablement

Test Chip Validation

Design

Enablement

Design

Productization

Customer

Product

Roadmap

Customer

Tape-out

Design

Enablement

Design

Productization

An Ecosystem for Innovation

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EDA

Ready

Process

Ready

Concurrent Technology and Design

-- EDA Partner Collaboration

TSMC Technology Development

EDA Partner Development

PDK

Enablement

Design Solution

Certification

Design Solution

Development

Design Solution

Definition

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IP

Ready

Process

Ready


-- IP Partner Collaboration


IP Partner Development

Process / IP

Roadmap

Alignment

Enablement

Kit / Training

TSMC 9000

Certification MPW

Silicon

Validation

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Design

Ready

Process

Ready

TV Validation


-- Design Partner Collaboration


Design Partner Development

Technology

Optimization

TV Plan

Product

Tapeout

Design Kits

Foundation IP

Design Guideline

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Concurrent Design & Technology

Readiness

TSMC-Online

• Design rules

• SPICE model

• Tech files/PDK

• Design kits

• Utilities

• Ref Flow

Certified EDA Tools

• DRC/LVS/RC

• DFM

• P&R

• STA/IR/EM

• Simulation

• Layout editor

Certified IP Portfolio

• Foundation IP

• Interface IP

• Embedded CPU

• Embedded GPU

• Analog IP

• OTP/MTP

Design

Tapeout

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Agenda





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A look back at 50 years of Silicon

Victor Grinich

Jean Hoerni

Eugene Kleiner

Jay Last

Gordon Moore

Robert Noyce

Sheldon Roberts

Julius Blank

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Transistor to IC

First IC

TI

1958

First Planar IC

Fairchild

1960

First Transistor

Bell Labs

1947

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FinFET vs. Planar Characteristics

FinFET Benefits

Lower leakage

Higher driving current

Low-voltage operability

Better mismatch

Higher intrinsic gain

FinFET Challenges

Higher parasitic capacitance

due to 3D profile

Higher parasitic resistance

due to local interconnect

Quantized device widths

Planar Device FinFET

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FinFET Value Proposition

~2X gate density improvement compared to 28nm

16nmFinFET offers extra 20% speed gain @ same total

power or 35% power saving @ same speed with similar

gate density compared to 20nm

16FF/28HPM 16FF/20SoC

Speed @ same total power 38% 20%

Total power saving @ same speed 54% 35%

Gate density 2X 1.1X

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FinFET Design Enablement Requires

Collaboration Among Foundry, EDA and

Lead Partners

Parasitic RC extraction: 3D profile

support, accuracy

Design methodology for low voltage

operation

Design methodology for

interconnect resistance

minimization

EM reliability and power integrity:

High drive current

3D

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FinFET Design Flow Requirements

3D FinFET device structure

Advanced SPICE modeling for 3D structure

Modeling layout dependent effects in 3D structure

Accurate RC extraction

Higher parasitic capacitance due to 3D profile

Higher parasitic resistance due to local interconnects

Quantized device width due to fin pitch/grid requirements

PODE device handling in designs, EDA tools and IPs

High-drive current leads to EM reliability and power integrity

issues

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FinFET EDA Tool Certification

Two levels of tool certification

Tool certifications as the foundation of FinFET design

infrastructure

Individual Tool Certification Tool

Certifications

Integrated Tool Certification

Using Cortex-A15

RC EM IR Custom

Design

STA P&R DRC LVS

Lib Char

FastSpice

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Summary

Technology advancements are driving earlier, wider

and deeper ecosystem collaboration to deliver

enabling design solutions

TSMC’s collaborative ecosystem unleashes

innovations to address FinFET design challenges

TSMC Open Innovation Platform® has a proven record

of success and is more critical than ever for 16nm and

beyond

Collaborate to Innovate FinFET Design Ecosystem Challenges...

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