Chuan Giao Tiep_SPI

7/31/2019 Chuan Giao Tiep_SPI

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I. Gii thiu.

Bi ny gip cc bn bit cch s dng cch truyn thng ni tip ng b SPI.Cng c chnh cng l 2 b phn mm AVRStudio (+gcc-avr) v Proteus. Thc cht

ngn ng lp trnh vn l gcc-avr nhng ti khng dng Programmer Notepad bitcode nh thng thng, thay vo ti dng AVRStudio lm trnh bin tp, bntham kho thm phn Lp trnh C bng AVRStudio trong bi hng dn s dngAVRStudio bit thm cch thc hin. Ti s dng chip ATmega32 lm minh

ha.Sau bi ny, ti hy vng bn c th hiu v thc hin c:

Nguyn l truyn thng ni tip SPI. S dng module SPI trong AVR cc ch Master v Slave.

II. Chun truyn thng SPI,SPI (Serial Peripheral Bus) l mt chun truyn thng ni tip tc cao do hang

Motorola xut. y l kiu truyn thng Master-Slave, trong c 1 chip Masteriu phi qu trnh tuyn thng v cc chip Slaves c iu khin bi Master v thtruyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn song cng (fullduplex) ngha l ti cng mt thi im qu trnh truyn v nhn c th xy ra ngthi. SPI i khi c gi l chun truyn thng 4 dy v c 4 ng giao tiptrong chun ny l SCK (Serial Clock), MISO (Master Input Slave Output), MOSI(Master Ouput Slave Input) v SS (Slave Select). Hnh 1 th hin mt kt SPI giamt chip Master v 3 chip Slave thng qua 4 ng.

SCK: Xung gi nhp cho giao tip SPI, v SPI l chun truyn ng b nn cn 1ng gi nhp, mi nhp trn chn SCK bo 1 bit d liu n hoc i. y l imkhc bit vi truyn thng khng ng b m chng ta bit trong chun UART. Stn ti ca chn SCK gip qu trnh tuyn t b li v v th tc truyn ca SPI cth t rt cao. Xung nhp ch c to ra bi chip Master.

MISO Master Input / Slave Output: nu l chip Master th y l ngInput cn nu l chip Slave th MISO li l Output. MISO ca Master v cc Slavesc ni trc tip vi nhau..

MOSI Master Output / Slave Input: nu l chip Master th y l ngOutput cn nu l chip Slave th MOSI l Input. MOSI ca Master v cc Slavesc ni trc tip vi nhau.

SS Slave Select: SS l ng chn Slave cn giap tip, trn cc chip Slaveng SS s mc cao khi khng lm vic. Nu chip Master ko ng SS ca mtSlave no xung mc thp th vic giao tip s xy ra gia Master v Slave .Ch c 1 ng SS trn mi Slave nhng c th c nhiu ng iu khin SS trnMaster, ty thuc vo thit k ca ngi dng.


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.

Hnh 1. Giao din SPI.

Hot ng: mi chip Master hay Slave c mt thanh ghi d liu 8 bits. C mixung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh ghi d liuca Master c truyn qua Slave trn ng MOSI, ng thi mt bit trong thanh

ghi d liu ca chip Slave cng c truyn qua Master trn ng MISO. Do 2 gid liu trn 2 chip c gi qua li ng thi nn qu trnh truyn d liu ny cgi l song cng. Hnh 2 m t qu trnh truyn 1 gi d liu thc hin bi moduleSPI trong AVR, bn tri l chip Master v bn phi l Slave.

Hnh 2. Truyn d liu SPI.

Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp(Clock Polarity) c gi tt l CPOL l khi nim dng ch trng thi ca chn SCK

trng thi ngh. trng thi ngh (Idle), chn SCK c th c gi mc cao(CPOL=1) hoc thp (CPOL=0). Phase (CPHA) dng ch cch m d liu c


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ly mu (sample) theo xung gi nhp. D liu c th c ly mu cnh ln caSCK (CPHA=0) hoc cnh xung (CPHA=1). S kt hp ca SPOL v CPHA lmnn 4 ch hot ng ca SPI. Nhn chung vic chn 1 trong 4 ch ny khngnh hng n cht lng truyn thng m ch ct sao cho c s tng thch giaMaster v Slave.

III. Truyn thng SPI trn AVR.

Module SPI trong cc chip AVR hu nh hon ton ging vi chun SPI m ttrong phn trn. V th, nu hiu cch truyn thng SPI th s khng qu kh thc hin vic truyn thng ny vi AVR. Phn bn di ti trnh by mt s imquan trng khi iu khin SPI trn AVR.

Cc chn SPI: Cc chn giao tip SPI cng chnh l cc chn PORT thng thng, vth nu mun s dng SPI chng ta cn xc lp hng cho cc chn ny. Trn chipATmega32, cc chn SPI nh sau:

SCK PB7 (chn 8)MISO PB6 (chn 7)MOSI PB5 (chn 6)SS PB4 (chn 5)

Khi chip AVR c s dng lm Slave, bn cn set cc chn SCK input, MOSIinput, MISO output v SS input. Nu l Master th SCK output, MISO output, MOSIinput v khi ny chn SS khng quan trng, chng ta c th dng chn ny iukhin SS ca Slaves hoc bt k chn PORT thng thng no.

Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghiiu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR.

SPCR(SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ng caSPI.

* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c set

bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy ra saukhi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l i vichip Slave) khi truyn nhn d liu vi SPI.

* Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. NuSPIE=0 th module SPI dng hot ng.

* Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit c truynv nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln nht ca dliu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn trc.Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phim bo cc bit DORD ging nhau trn c Master v Slaves.

* Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din lMaster, ngc li MSTR=0 th chip l Slave..


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* Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhp vcnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit ny tothnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khng quan trngnhng phi m bo Master v Slave cng ch hot ng. V th c th 2 bitny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liu trong 4 ch ca SPI trn AVR.

ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan trng nhng phi mbo cc bit DORD ging nhau trn c Master vSlaves.

CPHA=0

CPHA=1

Hnh 3. Cc ch hot ng ca SPI.

* Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR cho

php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun xung


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clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVR c tht. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp cho chip.

SPSR(SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trong

thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi dliu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6 WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1 nuchng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi qutrnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc truyn,

bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp tc choSPI.

SPDR(SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghigi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave, d liunhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn trong SPDRs c truyn cho Master.

S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chungca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi vc 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chng tacn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tip chocc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL, SPHA)

v chn tc giao tip. Truyn thng SPI lun c khi xng bi chip Master,khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca Slave xungmc thp (gi l chn a ch) v sau vit d liu cn truyn vo thanh ghi d liuSPDR, khi d liu va c vit vo SPDR xung gi nhp s c t ng to ra trnSCK v qu trnh truyn nhn bt u. i vi cc chip Slave, khi chn SS b koxung n s sn sng cho qu trnh truyn nhn. Khi pht hin xung gi nhp trnSCK, Slave s bt u sample d liu n trn ng MOSI v gi d liu di trnMISO.

minh ha cho cch truyn v nhn d liu SPI trn AVR, ti s thc hin mt

v d truyn nhn 1 chiu vi 1 chip Master v 3 chip Slaves. Tt c cc chip cdng l ATmega32, chip Master s iu khin cc chip Slaves thng qua 3 ng


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chn chip PB0, PD1 v PD2. Cng vic thc hin trong v d ny nh sau: Master sln lt chn 1 trong 3 chip Slaves v gi cc gi d liu tng ng n chng, chipSlave0 s nhn c cc con s t 0 n 80, Slave1 nhn 80 n 160 v Slave2 nhnd liu t 160 n 240. Cc Slave s hin th gi tr m mnh nhn c trn cc TextLCD kt ni vi PORTD mi Slave. S mch in v bng Proteus cho v dny c trnh by trong hnh 4.

Hnh 4. M phng v d giao tip SPI trn AVR.


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Ti s gii thch s lt mt s im chnh trong on code cho chip Master. Ccphn nh ngha t dng th 10 n dng 17 ch c tc dng lm cho chng trnh dc hiu hn v c tnh tng thch cao hn, v d nu bn mun s dng v d ny

cho cc chip khc bn ch cn thay i cc nh ngha ny m khng phi thay itrong ni dung cc chng trnh con. Chng ta nh ngha chn PORTB iukhin cc ng chn chip SS ca Slave (gi l cc ng a ch), dng 18 nhngha Slave(i) l th t chn trn PORT dng cho chip Slave th i. D hiu hn,ng SS trn Slave0 s c kt ni v iu khin bi chn 0 ca PORTB (chnPB0 v tng t cho cc Slaves cn li. Bin wData nh ngha trn dng 20 l mtmng 3 phn t cha cc con s 8 bits s truyn n cc Slaves.

Chng trnh con void SPI_MasterInit(void): Chng trnh ny khi ngcho chip Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi

Master, cc chn to xung gi nhp SCK v chn truyn d liu MOSI cn c setOutput nh trong dng 24, cc chn SPI cn li l input. Dng 25 gip ko in trko ln chn nhn d liu MISO ca Master. Dng lnh 26 SPCR=(1


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on code trong list 2 l on code cho chip Slaves, ch dng 3 chng tainclude file header interrupt.h v vic nhn d liu SPI ca SLave c thc hin

bng ngt SPI. Cc nh ngha bin trong cc dng code t 8 n 15 tng t nhtrong chng trnh cho chip Master. Ti s tp trung gii thch cc im khc bit choSlaves.

Chng trnh con void SPI_SlaveInit(void): Chng trnh ny khi ngcho chip Slave, cng ging nh trng hp ca Master, vic khi ng trc ht lset hng cho cc chn SPI. i vi Slave, ch c chn truyn d liu MISO l cnc set Output nh trong dng 19, cc chn SPI cn li l input. Dng 20 gip koin tr ko ln cc chn nhn d liu MOSI ca Slave, v chn chn Slave SS.Vic tip theo l ci t cc thanh ghi SPI nh trong dng lnh 21,SPCR=(1

Chuan Giao Tiep_SPI

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