Chinese Real Time VLBI Correlator Xiang Ying, Xu Zhijun, Zhu Renjie, Zhang Xiuzhong, Shu Fengchun,...
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Transcript of Chinese Real Time VLBI Correlator Xiang Ying, Xu Zhijun, Zhu Renjie, Zhang Xiuzhong, Shu Fengchun,...
Chinese Real Time VLBI Correlator
Xiang Ying, Xu Zhijun, Zhu Renjie, Zhang Xiuzhong, Shu Fengchun, Zheng Weimin
Shanghai Astronomical Observatory China
5th International e-VLBI Workshop 17-20 September 2006
OUTLINE Main Characteristics Architecture of the Correlator Clock Module PBI(Playback Interface) Module FFT & MAC(Multiply and Accumulate Card) Mo
dule MCC(Master Control Card) Module Some results Future Plan
1. 5 Stations FX Correlator ( 5 stations, 8 IFs )
2. Maximum data rate : 256Mbps (8 channels)
3. Integration Time : 32.768 millisecond – 1 hour (typical 1s)
4. Input data format: MKIV, MKV or others( VSI in plan)
5. data source : Disk Array, Network
6. Output: via net and disk files ( FITS format in plan)
7. Fringe searcher, Phase Cal
Main Characteristics
Architecture of Correlator
PBD
PBD
PBD
PBI
PBI
PBIFFT &
MAC
LTA(PC)
MCC Fringe search
PCAL
RS232
RS2327300A
7300A
7300A
7300A/RS232
5 Station8Ch
7300A
BENEFITS:
Fringe Finder
Phase Calibration
16Mbps data streamfrom network
256Mbps data stream from Disk Array
Hard Disk Array Storage
2Bit,8Ch
RS232
Station 1MKV
net
Station 2MKV
net
Station 5MKV
net
CCC (PC) 32 users RS232
Delay Model
FPGA
Delay Model
1G DDR ram
…
Clock Board
In the FFT & MAC & MCC Chassis: Provide 32MHz clock to pbi module
(5 stations) Provide 32MHz clock to FFT+MAC m
odule (8 channels) Provide 32MHz clock to MCC Provide 32MHz clock to LTA
PBI
1. Input buffer2. NRZM(Non Return to Zero Mark) deco
ding ( MK IV )3. Frame Synchronization detection and
frame header information extraction4. CRC checks and Parity check(MK IV )5. Fanout ( 1 : 1 、 1 : 2 、 1 : 4 )6. Output buffer
PBI Data Stream
8KX
32bit
15X
32bit
CRCchecks
Check &Strip
off parity
15X
8bit
1:1
1:2
1:4
SYSTEM_CLK
……111111110111111110111111110111111110……
sync patternInput buffer
NRZM decoding Data
checks
fanout
Frame sync 、Frame header
Output buffer
MK V数据通道MK V Data
MK IV数据通道MK IVdata
8KX
32bit
15X
32bit
15X
8bitDCLK
DATA +
WR_CLK
ACK
FFT_CLK
Ready
DataOutput
MAC
FFT16bitsScaled
Fixed Point
FRINGE
DELAY
16bits
LTA
7300A
Model Input
FSTC
MCC
PBI_1 DATA
CLKPBI_1
32M 32M 160M
8M
32M
PBI_2 DATA
CLKPBI_2
PBI_5 DATA
CLKPBI_5
FFT & MAC Board Diagram
…
1(b) 2(b) 3(b)
1(a)
RAM16x2
x1024
2(a)
RAM16x2x1024
3(a)
RAM16x2
x1024
PING-PANG RAM
FFT
16 bits1024 Fixed Point
Xilinx IP Core
DATA_R DATA_I (16 bits)
1
2
3
Address
10 bits
Index
9 bits
FFT_R
16 bits
Done
FFT_I
FFT (Fast Fourier Transform)
Model Parameter Integer Bit Delay Fringe Stopping
FSTC (Fractional Sample Time Correction)
1CCC
ibai
fedf 1,,1,0 Mf
N: Bit number in one model cycle
1,,1,0 Ni
M: FFT cycle in one model cycle
a,b,c,d,e are calculated by MCC
X_R
16 bits
X_I
Y_R Y_I
16 bits
Dout_R Dout_I
R
RAM42x512
I
RAM42x512
R
RAM42x512
I
RAM42x512
1~1023 次
1024 次
Output RAM
Acc RAM
42x2 bits
42x2 bits
42x2 bits
DOUT_R = X_R * Y_R + X_I * Y_I
DOUT_ I = X_I * Y_R - X_R * Y_I
MAC (multiple and accumulate)
MCC
Model Paramete
rs calculatio
n
(8 channels)Powerpc
(virtex4)
Output Parameter
s
From PPC
GPIO
FIFO
FFT points size, Nyquist Frequency, Sky Frequency, Dela
y polynomial
Rs232
Parameters: a, b, c,
d,e
Result – TC-1 Satellite
The Fringe of the
SH-UR Baseline
TC-1 observation
with Integration
time of 62.5 ms