Chapter 5 Metal Oxide Semiconductor Field Effect ...staff.utar.edu.my/limsk/Basic...

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Chapter 5

Metal Oxide Semiconductor Field Effect Transistor Theory and Applications

_____________________________________________

5.0 Introduction The metal oxide semiconductor field effect transistor MOSFET a voltage control current device. It differs from junction field effect transistor JFET that it has no pn junction structure. It has a metal gate, which insulates the conducting channel with silicon oxide SiO2. In the modern design, metal gate has been replaced by either p+ or n+ polysilicon.

There are two types of MOSFET namely depletion-enhancement DE and enhancement E types. Figure 5.1 and 5.2 show the difference between the types.

The DE type has a narrow channel adjacent to the gate connecting the drain and source of the transistor. It can operate in either depletion mode or enhancement mode. The mode of operation is like the JFET.

The E type does not have a narrow connecting channel. It operates by forming a conducting channel of the same type like the source and drain. The channel is formed either by attracting electron or depleting away electron to form an n-channel or p-channel connecting the source and the drain.

MOSFET not only can be used to design amplification circuit. It can also be used as a capacitor and a resistor. This capability makes the VLSI design simpler because there is no need to use other element for capacitor and resistor in the design.

Figure 5.1: The structure of depletion-enhancement n-channel and p-channel MOSFET

5 MOS Transistor Theory and Applications

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Figure 5.2: The structure of enhancement n-channel and p-channel MOSFET

The symbol of both depletion-enhancement and enhancement MOSFET types are shown in Fig. 5.3 and 5.4 respectively. Note that for most cases, by design the substrate is connected to the source.

Symbols other then those symbols shown in Fig. 5.3 and 5.4 are used too. The reader needs to identify them careful during any circuit analysis. Circuit examples shown in this chapter will use any symbol listed in Fig. 5.3 and Fig. 5.4 as illustration.

(a) n-channel (b) p-channel Figure 5.3: Symbol of depletion-enhancement MOSFET

(a) n-channel (b) p-channel

Figure 5.4: Symbol of enhancement MOSFET


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5.1 Depletion-Enhancement MOSFET and Enhancement MOSFET

The transfer characteristic of depletion-enhancement DE and enhancement E MOSFETs are shown in Fig. 5.5 and 5.6 respectively.

The characteristic curve of DE type is same as the JFET except there is an additional enhancement part, where the curve extends to positive VGS i.e. attract either hole or electron. In depletion mode, electron in n-channel or hole in p-channel is depleted away. In enhancement mode, electron is attracted in n-channel and hole in p-channel.

(a) n-channel (b) p-channel Figure 5.5: Transfer characteristic of DE MOSFET

The equation for the transfer characteristics of depletion-enhancement DE MOSFET is same the JFET which is

2

)off(GS

GSDSSD V

V1II

−= (5.1)

where IDSS is normally given by data sheet. If the design parameters are given then IDSS is defined as

2)off(GSOXnDSS V

L

WC

2

1I µ= (5.2)


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where L is channel length, W is width of the gate, Cox is capacitance of oxide per unit area, and µn is the effective mobility of electron, which has a nominal value 650cm2/V-s at 25oC.

Enhancement MOSFET uses only channel enhancement. If the drain and source are n-type, the gate is biased with positive voltage to attract electron from the substrate near the oxide to form an n-type conducting channel. Likewise, E MOSFET type has p-type drain and source, the gate is biased with negative voltage to form a p-type conducting channel.

(a) n-channel (b) p-channel Figure 5.6: Transfer characteristic of E MSOFET

There is a minimum gate-to-source voltage to be applied before conducting channel can be formed. This gate-to-source voltage is called threshold voltage and is denoted as VGS(th).

The threshold voltage VGS(th) is used to overcome the flat band potential, surface potential, fixed charge, and oxide capacitance Cox of the gate before inversion can be occurred.

A typical ID-VDS characteristic curve of an n-channel MOSFET for the selected VGS is shown in Fig. 5.7. There are three regions - the cut-off region, the triode region (or almost linear region) and saturation region (operation region). The saturation region is the useful region for an amplifier operation, whereas the other regions are good for switch operation. The curve also shows


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that the output impedance is infinite, which is not true in reality. We shall discuss how to determine the finite output resistance later in the chapter.

Figure 5.7: ID - VDS characteristic curve of an n-channel MOSFET There are two equations of the transfer characteristics for enhancement MOSFET.

At linear region, the equation is

( )

−−= 2DSDS)th(GSGSD V

2

1VVVK2I (5.3)

This equation is useful for MOSFET operating as a switch or digital device. We would not use it at the time being since we are interested with operation region.

At saturation region (operation region), the equation is


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[ ]2)th(GSGSD VVKI −= (5.4)

where [ ]2)th(GSGS

D

VV

IK

−= which can be calculated based on the known value of

ID for given VGS and VGS(th).

If the design parameters of the E MOSFET such as its channel length L, width of the gate W, and the capacitance of oxide Cox are known then

L

WC

2

1K oxnµ= = β

2

1 (5.5)

where µn is the effective mobility of electron which has value 650cm2/V-s and µp is the mobility of hole which has 200cm2/V-s. W/L is called the aspect ratio for a given MOSFET. β is the intrinsic transconductance parameter usually specified in SPICE MOSFET’s model.

Differentiating equation (5.4) for drain current ID with respect to gate-to-source voltage VGS for a fixed drain-to source voltage VDS yields the transconductance gm of the MOSFET.

Therefore,

[ ])th(GSGSGS

Dm VVK2

dV

dIg −==

or

[ ])th(GSGS

D

GS

Dm VV

I2

dV

dIg

−== (5.6)

Example 5.1 The data sheet for a certain enhancement MOSFET states that drain current is ID

= 3mA at VGS = 10V and VGS(th) = 5V. Determine the drain current ID for VGS = 8V. Solution

From equation (5.4), [ ]2

2V/mA12.0

V5V10

mA3K =

−=


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Thus, the drain current ID at VGS = 8 V is [ ] mA08.1V5V8V/mA12.0I 22D =−= .

Example 5.2 The n-channel MOSFET shown in the figure operates with drain current ID = 0.4mA and VD = 1.0V. The transistor has VGS(th) = 2.0V, µnCox = 20µA/V2, L = 10µm and W = 400µm. Determine its drain resistance RD and source resistance RS.

Solution Equation (5.4) is used to determine the VGS for ID current equal to 0.4mA. Thus,

an equation 2GS

63 )2V(10

40010x20

2

110x4.0 −= −− is obtained. Solving this equation

yields two values for gate-to-source voltage, which are VGS = 1.0V or 3.0V. Since VGS(th) = 2.0V, gate-to-source voltage VGS should be 3.0V. VGS = VG - VS = 3.0V and VG = 0, therefore VS = -3.0V.

The source resistance is RS = Ω=−−−=−− k5

10x4.0

)5(3

I

VV3

D

SSS

and

the drain resistance is RD = Ω=−=−− k10

10x4.0

15

I

VV3

D

DDD


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5.2 Biasing of MOSFET Figure 5.8 shows the biasing configuration of an n-channel and a p-channel MOSFET. For n-channel type MOSTFET NMOS, the gate is biased with positive voltage and the drain is biasing with positive voltage. For p-channel MOSFET PMOS, the gate is biased with negative voltage and the drain is biased with negative voltage. Note that the source is always common to both the gate-to-source and collector-to-source terminals.

(a) n-channel biasing configuration (b) p-channel biasing configuration Figure 5.8: Biasing configuration of an n-channel and a p-channel MOSFET

Notation The current flow between drain and source is termed drain or source current ID or IS. The voltage at source is denoted as VS, at drain is denoted as VD, and at gate is denoted as VG. The output resistance of MOSFET is denoted as ro and the drain-source resistance is denoted as rDS.

5.2.1 Depletion-Enhancement MOSFET Biasing A simple normal biasing method for depletion-enhancement MOSFET is by setting gate-to-source voltage equal to zero volt i.e. VGS = 0V. This method of biasing enables ac signal to vary the gate-to-source voltage above and below this bias point as shown in Fig. 5.9.


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Figure 5.9: DE MOSFET transfer characteristic curve

A depletion and enhancement MOSFET biased with VGS = 0 is shown in Fig. 5.10.

Figure 5.10: A zero-biased DE MOSFET


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Example 5.3 Using the circuit shown in Fig. 5.10, determine the drain current ID and drain-to-source voltage VDS given that VGS(off) = -8V, IDSS = 12mA, VDD = 15V, RG = 10MΩ and RD = 600Ω. Solution

From equation (5.1) the drain current is 2

)off(GS

GSDSSD V

V1II

−=

Since VGS = 0V then ID = IDSS = 12.0mA VDS = VDD - IDRD = 15.0V – 12mA(600Ω) = 7.8V 5.2.2 Enhancement MOSFET Biasing There are two standard methods that E MOSFET can be biased, which are shown in Fig. 5.11.

(a) Drain-feedback bias (b) Voltage divider bias Figure 5.11: Drain feedback bias and voltage-divider bias for E MOSFET

For drain feedback bias, the gate has very high impedance and negligible gate current. Therefore, the voltage drops across RG is negligible. i.e. VDG ≅ 0. Since VDS = VGS +VDG, thus, VGS is equal to VDS.


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For voltage-divider bias, VGS = DD21

2 VRR

R

+. The voltage value is also

equal to voltage at gate VG since voltage at source VS = 0. Example 5.4 If a VD voltage of 0.1V needs to be established for the design, what will be the value of RD and effective resistance rDS between drain and source of this NMOS? Given that VGS(th) = 1V and K = 1.0mA/V2.

Solution Since VD = 0.1V, this shall mean that VDS = 0.1V. This is also mean that the NMOS is operating at linear region because VDS ≤ (VGS - VGS(th)) - Refer to Fig. 5.7 Thus, from equation (5.3),

( )

−−= 2DSDS)th(GSGSD V

2

1VVVK2I

mA79.001.0x2

11.0)15(V/A10x12 23 =

−⋅−×= −

The required drain resistance RD value is RD = Ω=−=−

k2.6mA79.0

V1.0V5

I

VV

D

DSDD


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The effective resistance across the drain and source rDS is

Ω=== 5.174mA79.0

V1.0

I

Vr

D

DSDS

Example 5.5 Given that drain current is ID = 0.4mA, gate-to-source threshold voltage is VGS(th) = 2V, µnCox = 20µA/V2, aspect ratio is 10, calculate the value for resistance R, drain voltage VD, and effective channel resistance rDS.

Solution The gate and drain are tied together, therefore drain-to-gate voltage is VDG = 0 V. The NMOS is operation in saturation region since VDS > VGS – VGS(th). Thus, saturation equation (5.4) is used for calculation. [ ]2)th(GSGSD VVKI −=

0.4mA = [ ]2GS

26 2V10V/A10x202

1 −⋅⋅ −

From the equation, it yields two values for gate-to-source voltage i.e. VGS = 0 or 4V. Since the threshold voltage VGS(th) is 2.0V, therefore the gate-to-source voltage VGS is 4.0V. VDS = VD – VS = 4.0V


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R = Ω=−=−k15

mA4.0

V4V10

I

VV

D

DDD

RDS =VD/ID = 4.0V/0.4mA = 10.0kΩ.

5.3 MOSFET as a Capacitor If the MOSFET is biased in accumulation mode, the MOS of MOSFET is acted as capacitor. The insulator oxide layer between the gate and the channel forms a

parallel capacitor plate where its capacitance Ci = i

i

d

LWε, where LW is the cross

sectional area, di oxide thickness and εi the permittivity of oxide.

5.4 MOSFET as a Resistor If a MOSFET is connected as shown in Fig. 5.12, it has a variable resistance,

which depends on the VGS and VDS bias. The ac resistance shall be mg

1 ||ro≅mg

1 .

Figure 5.12: MOSFET connected as resistor and its characteristics

5.5 Small Signal Amplifier The transfer characteristic curve for depletion-enhancement MOSFET DE MOSFET is shown in Fig. 5.10. The Q-point is set at VGS = 0 so that ac signal can be varied the gate-to-source above and below this Q-point.


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The transfer characteristic curve for enhancement MOSFET E MOSFET is shown in Fig. 5.13. The Q-point of E MOSFET cannot be laid on drain current ID axis because E MOSFET requires a minimum VGS voltage, which is termed as threshold voltage VGS(th) in order for operation.

Figure 5.13: Transfer characteristics curve for enhancement MOSFET

5.5.1 Equivalent Circuit for Enhancement MOSFET From Fig. 4.14 of JEFT equivalent circuit in Chapter 4, the output resistance ro of MOSFET is at least a few orders higher than the drain resistance RD. Similar it is true for MOSFET.

Practically there is no gate-to-source current. Thus, the gate-to-source resistance Rin(gate) is extremely high such that it can be treated as open circuit, which is similar like the JFET. Thus, the ac equivalent circuit of MOSFET is similar to the JFET.

Showing here is a number of equivalent circuits, which are useful for

determining the small signal ac voltage gain later on. Fig. 5.14 and Fig. 5.15 show the equivalent circuits.


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Figure 5.14: MOSFET equivalent circuit using transconductance formula

Figure 5.15: MOSFET equivalent circuit using ID formula

5.5.2 Finite Output Impedance of MOSFET Reference to the graph shown in Fig. 5.7, it states the drain current ID is independent of drain-to-source voltage VDS at saturation (at the beginning of pinch-off) which shall mean that MOSFET has infinite output impedance ro. In reality this is not true. Theoretically, at pinch-off, the channel shape and pinch-off point do not change upon further applying drain-to-source voltage VDS. In reality the shape of channel changed and pinch-off point moved away from the drain. The change modifies the effective channel length of the device, which is termed channel length modulation. The illustration is shown in Fig. 5.16.


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Figure 5.16: Channel modulation caused by further increase of VDS beyond pinch-off VDS

saturation voltage VDSSat The voltage drop across the channel is VDSSat = VGS-VGS(th). Any increase of VDS voltage beyond VDSSat (VDS - VDSSat) will drop across ∆L. This causes acceleration of electron from the channel to drain. From equation (5.4), ID is inversely proportional to the channel length L. Since channel length L decreases, ID current increases. Equation (5.4) shall then be modified to

( ) ( )IC W

LV V VD

n OXGS GS th DS= − +

µλ

21

2

( ) , where λ = 1/VM and VM is the Early

voltage, which can be ranged from 20 to 200V. Figure 5.17 illustrates how Early voltage VM can be determined.

Figure 5.17: The graph shows the Early voltage point


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The graph in Fig. 5.17 shows that the output impedance ro of the MOSFET is now having a finite value, which can be defined as

D

M

D

DSM

ttanconsVD

DSO I

V

I

VV

I

Vr

GS

≅+

=∂

∂=

=

D

M

I

V≅ for a fixed VGS voltage after

neglecting small VDS voltage. 5.5.3 Analysis of MOSFET Amplifier The amplifier configurations for MOSFET are same like the JFET's. The analysis of small-signal amplifier for DE and E MOSFET is same like JFET. Instead of repeating the procedure of analysis, examples are used as illustrations. Example 5.6 A common-source amplifier shown in figure using a NMOS has ID = 5mA at VGS = 7.5V, VGS(th) = 5V, gm = 6mS, Vin = 48mV rms, and VM = 50V. Find VGS, ID, VDS, rDS, Rin, Vout and ac voltage gain.

Figure 5.18: A common source amplifier

Solution Saince the source is grounded, the gate-to-source voltage is

V19.6V15k47k33

k33V

RR

RV DD

21

2GS =

Ω+ΩΩ=

+=


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Using equation (5.4), substitute VGS = 7.5V and VGS(th) = 5.0V, and ID = 5.0mA to determine the K values of the MOSFET, which is [ ]2)th(GSGSD VVKI −= . Thus,

the K value is [ ] 22 mAV8.0V5V5.7/mA5K −=−= The drain current ID at VGS = 6.19V is [ ] mA13.1V5V19.6mAV8.0I 22

D =−= − The drain voltage is VD = VDS = 15V - 1.13mA x 3.3kΩ = 11.26V. The drain-to-source resistance rDS is rDS = VDS/ID = 11.26V/1.13mA = 9.96 kΩ. The ac equivalent circuit of the amplifier is shown in figure below.

Figure 5.19: ac circuit of a common source amplifier

The input impedance Rin is equal to R1||R2 = 47.0kΩ||33.0kΩ = 19.4kΩ . The output impedance ro is ro = VA/ID =50V/1.13mA = 44.6kΩ The output voltage is Vout = -gmVgs(ro||RD) = 6.0mS x 3.07kΩ x Vgs = 18.4Vgs The input voltage is Vin = Vgs Therefore, the ac voltage gain is AV = Vout/V in = -18.4Vgs/Vgs = -18.4V/V The output voltage is Vout = - AVV in = -18.4 x 48mV rms = - 0.874V rms. Example 5.7 Calculate the ac voltage gain Av and input impedance Rin of the amplifier circuit shown in figure. Given that K = 0.125mA/V2, threshold voltage VGS(th) = 1.5V, and Early voltage VM = 75.0V.


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Figure 5.20: A drain feedback common source amplifier

Solution The ac equivalent circuit is shown in figure.

Figure 5.21: ac circuit of a drain feedback common source amplifier

Using equation (5.4), which is [ ]2)th(GSGSD VVKI −=

The drain current ID is [ ]2

GS2

D 5.1VV/mA125.0I −= Also, the drain voltage VDS is VDS = 15V - ID x 10.0kΩ.


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Since there is no current flow into the gate, the voltage across drain and gate shall be zero, thus, gate-to-source voltage is equal to drain voltage i.e. VGS = VDS. Solving the above two equations, the drain current is ID = 1.06mA and drain voltage is VDS = 4.4V. Using equation (5.3), which is equation ( )[ ]2

)th(GSGSD VVKI −= . Differentiating this

equation to obtain transconductance, which is ( ) ( ) mS725.0V5.1V4.4V/mA125.0x2VVK2g 2

)th(GSGSm =−=−≅

The output impedance of the MOSFET is ro = VM/ID = 75V/1.06mA = 67.9kΩ The ac voltage gain AV is AV = - gm(RL|| ro||RD) = - 0.725mS x 4.66kΩ = -3.37V/V From the ac equivalent circuit shown in Fig. 5.21, the input current ii is ii = (Vin -Vout)/RG The input impedance Rin is Rin = Vin/ii = VinRG/(V in - Vout)

=

−

in

outG V

V1/R = 10x106 /(1+ 3.37) = 2.28MΩ.

One will also see that the input impedance Rin is also equal to the Miller’s input

resistance, which is defined as )A1(

R

V

G

+, for this amplifier.

Example 5.8 Design the amplifier circuit shown in figure below that its transistor operates in saturation region with ID = 0.5mA and VD = 3.0V. The enhancement-type PMOS transistor have VGS(th) = -1.0V and K = 0.5mA/V2. What is the largest value of RD can have while maintaining saturation-region operation? Note that normally RG1 and RG2 are in MΩ range.


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Figure 5.22: A common drain amplifier

Solution Using eqution (5.4), which is ID = K(VGS – VGS(th))

2. Substituting ID = 0.5mA, K = 0.5mA/V2, and VGS(th) = -1.0V, the gate-to-source voltage VGS of the PMOS shall be ±1.0V – 1.0V, which are 0V or -2.0V. Since the threshold voltage of the PMOS is -1.0V, therefore, its gate-to-source voltage VGS should be – 2.0V. Since gate-to-source voltage is VGS = VG - VS then the gate votlage VG shall be VG = VGS + VS = -2.0V + 5.0V = 3.0V. Thus, the ratio of RG1 and RG2 shall be 2:3. Thus the value of RG1 And RG2 can be 2.0 MΩ and 3.0MΩ. The resistance value of drain resistor RD shall be VD/ID = 3.0V/0.5mA = 6.0kΩ. For the PMOS to maintain in saturation mode, VSD ≥ VSG - VSG(th) = 2.0V – 1.0V = 1.0V. This shall mean the drain voltage must be maintain within VD ≤ VS – 1.0V. Thus, the maximum drain voltage VDmax shall be VS -1.0V = 4.0V. Thus, the maximum value of drain resistor RD = VD/ID = 4.0V/0.5mA = 8.0kΩ for maintaining operating in saturation region.


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Example 5.9 The NMOS amplifier circuit shown in figure below has Early voltage VM = 50.0V, gate-to-source voltage VGS(th) = 0.9V and operates with drain voltage VD = 2.0V. What is the voltage gain of this amplifier? If drain current ID is double, what will be the voltage gain?

Figure 5.23: A drain feedback common source amplifier Solution Let’s test to see which region the MOSFET is operating in. VDS = VDG + VGS Since gate current is very small thus, VDG = 0 then VDS = VGS

VDS ≥ VGS - VGS(th) Thus, the value of LHS > the value of RHS since VDS = VGS and VGS(th) > 0V.

Therefore, the MOSFET operates in saturation region. The ac equivalent circuit of this amplifier is shown in figure below.


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Figure 5.24: ac circuit of drain feedback common source amplifier

From the theory discussed earlier, the voltage gain AV is AV = -gm (ro||RL) The output impedance ro of the MOSFET is ro at ID = 500.0µA is VM/ID = 50.0V/500.0µA = 100.0kΩ The drain-to-source voltage is VDS = VDG + VGS. Since VDG = 0V and VS = 0V then the drain voltage shall be VD = VDS = VGS = 2V. Transconductance gm of the amplifier is gm = 2ID/(VGS - VGS(th)) = 2x 500µA/(2V - 0.9V) = 0.909mS Thus the voltage gain is AV = - 0.909mS(100Ω||10kΩ) = -8.26V/V When ID is double to 1mA, ro = 50V/1.0mA = 50.0kΩ From the saturation formula, ID = K 2

)th(GSGS )VV( − , the constant K

K = 500µA/ ( ) 22 V/mA413.0V9.0V2 =− Thus, the saturation ID formula shall be ID = 0.413mA/V2(VGS - 0.9V)2

If I D = 1.0mA then VGS = 0.65V or 2.46V. Certainly, VGS cannot be 0.65V since VGS(th) is 0.9V. Thus, VGS shall be 2.46V. The transconductance gm for VGS = 2.46V is


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gm = mS28.1V9.0V46.2

mA1x2 =−

The voltage gain AV when ID = 1.0mA is AV = - 1.28 mS(50 kΩ||10 kΩ) = - 10.8V/V

5.6 Multistage Amplifier MOSFET and JFET share the same ac equivalent circuit. Therefore, the way to analyse the multistage amplifier is same as the way how to analyse the multistage amplifier of the JFETs.

We shall discuss a multistage amplifier that contains both bipolar junction transistor and MOSFET device here.

Figure 5.25 shows a cascaded amplifier that contains both bipolar junction

transistor and MOSFET.

Figure 5.25: A cascoded BiMOS amplifier circuit

The voltage gain of the first stage n-channel MOSFET amplifier is - gmRD, when gm is the transconsductance that follows equation (5.6)

[ ])th(GSGS

D

GS

Dm VV

I2

dV

dIg

−== . However, owing to loading effect from the bipolar


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junction transistor amplifier stage, the load of this amplifier shall be RD||R3||R4||(β+1)VT/IE. Thus, voltage gain AV1 of n-channel MOSFET amplifier stage shall be

AV1 = [ ]

)th(GSGS

ET43DD

VV

I/V)1||R||R||RI2

−+β

− (5.7)

The voltage gain AV2 of second stage is

AV2 = T

EC

V

IRα− (5.8)

The overall gain AV of the amplifier shall be AV = AV1xAV2, which is

AV = [ ]

)th(GSGS

ET43DD

VV

I/V)1||R||R||RI2

−+β

T

EC

V

IRα⋅ (5.9)

Tutorials 5.1. State the difference in terms of voltage biasing and output characterisitcs

between a depletion-enhancement MOSFET and an enhancement MOSFET.

5.2. State the conditions for an enhancement MOSFET to operate in triode

and saturation regions. Given that ID = 0.75 mA, RD = RS = 5.0 kΩ, and VGS(th) = 0.5 V. Determine the operation condition of the circuit below.


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5.3. For active load circuit below, given that R = 15.0kΩ.

(i) What is the ID current and drain voltage VD if the active load resistance of 25kΩ is desired?

(ii) What is the gate to source voltage VGS for this circuit?

5.4. Describe how a MOSFET can be configured as a capacitor? Given that

dielectric constant of SiO2 is 3.9, permittivity in free space ε0 = 8.854

x10-14F/cm, W = 200µm, L = 10µm, and thickness of oxide di = 100Ao

, calculate the capacitance.

5.5. The NMOS circuit shown figure has K = 0.5x10-3A/V2, threshold voltage VGS(th) = 2V, RG1 = 4.7MΩ, RG2 = 2.2 MΩ, RD = 2.2kΩ, and RS = 500Ω. Determine the values of VGS, ID, and VDS.


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5.6. The common source amplifier is shown in the figure has VGS(th) = 3V and K = 1mA/V2. Find VGS, ID, VD and the ac output voltage. If a load RL of 3.3kΩ is connected at the output what is the ac current in the load?

5.7. The depletion MOSFET shown in the circuit is required to supply the

variable resistor RD with a constant current of 100.0µA. If the threshold voltage is VGS = -1.0V. Find the range of resistor RD can have while the current through it remains constant at 100.0µA.


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5.8. Calculate the ac voltage gain and output voltage of the BiMOS amplifier shown the figure.

References 1. Theodore F. Bogart Jr., Jeffrey S. Beasley, and Guillermo Rico, “Electronic

Devices and Circuit”, sixth edition, Prentice Hall, 2004. 2. Adel S. Sedra and Kenneth C. Smith, "Microelectronic Circuits", fourth

edition, Oxford University Press, 1998. 3. Robert L. Boylestad, and Louis Nashelsky, “Electronic Devices and Circuit

Theory”, eighth edition, Prentice Hall, 2002.

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