Chapter 3 Metal Oxide Semiconductor (MOS)

8/3/2019 Chapter 3 Metal Oxide Semiconductor (MOS)

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Metal-Oxide-Semiconductor(MOS)

EBB424E

Dr. Sabar D. HutagalungSchool of Materials & Mineral Resources Engineering,Universiti Sains Malaysia


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MOS (Metal-Oxide-Semiconductor)

Assume work function of metal and semiconductor aresame.


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MOS materials


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MOS structure

Shown is the semiconductor substrate with a thin oxide layerand a top metal contact, also referred to as the gate.

A second metal layer forms an Ohmic contact to the back of thesemiconductor, also referred to as the bulk.

The structure shown has a p-type substrate. We will refer to this as an n-type MOS capacitor since the

inversion layer contains electrons.
http://ece-www.colorado.edu/~bart/book/book/chapter6/ch6_2.htm


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Structure and principle of operation

To understand the different bias modes of anMOS we consider 3 different bias voltages.

(1) below the flatband voltage, VFB

(2) between the flatband voltage and thethreshold voltage, VT, and (3) larger than the threshold voltage. These bias regimes are called the

accumulation, depletionand inversionmodeof operation.


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Structure and principle of operation

Charges in a MOS structure under accumulation,depletion and inversion conditions


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Four modes of MOS operation

The four modes of operation of an MOS structure: Flatband, Depletion, Inversion and Accumulation.

Flatband conditions exist when no charge is present inthe semiconductor so that the Si energy band is flat.

Surface depletion occurs when the holes in thesubstrate are pushed away by a positive gate voltage.

A more positive voltage also attracts electrons (theminority carriers) to the surface, which form the so-called inversion layer.

Under negative gate bias, one attracts holes from thep-type substrate to the surface, yielding accumulation


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MOS capacitor structure


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MOS capacitor- accumulation


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Accumulation occurs typically for -ve voltages where the-ve charge on the gate attracts holes from the substrateto the oxide-semiconductor interface.

Depletion occurs for positive voltages. The +ve charge on the gate pushes the mobile holes into

the substrate. Therefore, the semiconductor is depleted of mobile

carriers at the interface and a -ve charge, due to the

ionized acceptor ions, is left in the space charge region.

MOS capacitor- accumulation


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MOS capacitor- flat band


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The voltage separating the accumulation anddepletion regime is referred to as the flatbandvoltage, VFB.

The flatband voltage is obtained when theapplied gate voltage equals the workfunctiondifference between the gate metal and thesemiconductor.

If there is a fixed charge in the oxide and/or at

the oxide-silicon interface, the expression for theflatband voltage must be modified accordingly.

MOS capacitor- flat band


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MOS capacitor- depletion


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MOS capacitor- inversion


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Inversion occurs at voltages beyond thethreshold voltage.

In inversion, there exists a negatively

charged inversion layer at the oxide-semiconductor interface in addition to thedepletion-layer.

This inversion layer is due to minoritycarriers, which are attracted to the interfaceby the positive gate voltage.

MOS capacitor- inversion


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MOS Capacitance

CV measurements of MOS capacitors provide a wealthof information about the structure, which is of directinterest when one evaluates an MOS process.

Since the MOS structure is simple to fabricate, thetechnique is widely used.

To understand CV measurements one must first befamiliar with the frequency dependence of themeasurement.

This frequency dependence occurs primarily in

inversion since a certain time is needed to generate theminority carriers in the inversion layer. Thermal equilibrium is therefore not immediately

obtained.


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Capacitance depends on frequency of applied signal. If speed of variation is slow enough so that electrons

can be generated by thermal generation fast enough tobe created in phase with applied signal, then Cs is verylarge

If variation is too high a frequency, electronconcentration remains fixed at the average value and

capacitance depends on capacitance of depletion region

MOS Capacitance


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Influence of gate on surface potential


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Gate-depletion capacitive divider


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Capacitance in series


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CV Curve


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CV Curve


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CV Curve


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C-V characteristic of p-type Semiconductor

nMOS


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pMOS

C-V characteristic of n-type Semiconductor


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Low frequency capacitance of an nMOS capacitor. Shown are the exact solution for the low frequency

capacitance (solid line) and the low and high frequencycapacitance obtained with the simple model (dotted lines). Na= 1017 cm-3 and tox = 20 nm.


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(a) The thresholdvoltage and theideal MOSstructure

(b) In practice, there are several charges in the oxide and at the oxide-semicond interface that effect the threshold voltage: Qmi= mobile ioniccharge, Qot= trapped oxide charge, Qf= fixed oxide charge, Qit=charge trapped at the interface.


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Effects of Real Surfaces


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Charge Distribution


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Key Definitions


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Potential Definition


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Depletion Width


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Gate Voltage (depletion case)


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-depletion capacitance


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-depletion capacitance


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n-Si


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p-Si


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Exact capacitance


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C vs f


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C vs f


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C vs scan rate


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Parallel plate capacitance

P ll l l i


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An n-channel MOS transistor. The gate-oxidethickness, TOX, is approximately 100 angstroms (0.01mm). A typical transistor length, L = 2 l. The bulk maybe either the substrate or a well. The diodes representpn-junctions that must be reverse-biased


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The channel and the gate form the platesof a capacitor, separated by an insulator- the gate oxide.

We know that the charge on a linearcapacitor, C, is

Q= C V The channel charge, Q.


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At lower plate, the channel, is not a linearconductor.

Charge only appears on the lower plate whenthe voltage between the gate and the channel,VGC, exceeds the n-channel threshold voltage.

For nonlinear capacitor we need to modify theequation for a linear capacitor to the following:

Q= C(VGC Vt)


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The lower plate capacitor is resistive and conductingcurrent, so that the VGCvaries. In fact, VGC= VGSat the source and VGC= VGSVDSat

the drain. What we really should do is find an expression for the

channel charge as a function of channel voltage andsum (integrate) the charge all the way across thechannel, from x= 0 (at the source) to x= L (at thedrain).

Instead we shall assume that the channel voltage,VGC(x), is a linear function of distance from the sourceand take the average value of the charge, which is

Q= C[(VGS Vt) 0.5 VDS]


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The gate capacitance, C, is given by the formula for aparallel-plate capacitor with length L , width W , andplate separation equal to the gate-oxide thickness, Tox.

Thus the gate capacitance is

C = (W L eox)/Tox = W L Cox where eox is the gate-oxide dielectric permittivity For SiO2 , eox ~ 3.45 x 1011 Fm1, so that, for a typical

gate-oxide thickness of 100 (= 10 nm), the gatecapacitance per unit area, Cox ~ 3 fFmm2.


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The channel charge of transistor

The channel charge in terms of the transistorparametersQ= WL Cox [(VGS Vt) 0.5 VDS]

The drainsource current is

IDS = Q/tf= (W/L) mnCox[(VGS Vt) 0.5 VDS] VDS= (W/L)k'n[(VGS Vt) 0.5 VDS] VDS ......(*)

The tf is time of flight - sometimes called the transit

time is the time that it takes an electron to crossbetween source and drain. mn is the electron mobility (mp is the hole mobility)


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The constant k'n is the processtransconductance parameter (or intrinsictransconductance ):

k'n= mnCox We also define bn , the transistor gain factor

(or just gain factor ) asb

n= k'

n(W/L)

The factor W/L is the transistor shape factor.


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Equation (*) describes the linear region (or triode region) ofoperation. This equation is valid until VDS= VGS Vt and then predicts that

IDSdecreases with increasing VDS. At VDS= VGS Vt = VDS(sat) (the saturation voltage ) there is no

longer enough voltage between the gate and the drain end of the

channel to support any channel charge. Clearly a small amount of charge remains or the current would go

to zero, but with very little free charge the channel resistance in asmall region close to the drain increases rapidly and any furtherincrease in VDS is dropped over this region.

Thus for VDS> VGS Vt (the saturation region, or pentode

region, of operation) the drain current IDSremains approximatelyconstant at the saturation current, IDS(sat) , whereIDS(sat) = (bn/2)(VGS Vt)2; VGS> Vt ..... (**)


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Figure below shows the n-channel transistor I-Vcharacteristics for a generic 0.5 mm CMOSprocess that we shall call G5 .

We can fit Eq.(**) to the long-channeltransistor characteristics (W = 60 mm, L = 6mm).

If IDS(sat) = 2.5 mA (with VDS= 3.0 V, VGS= 3.0

V, Vt = 0.65 V, Tox =100 ), the intrinsictransconductance is


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MOS n-channel transistorcharacteristics for a generic 0.5 mmprocess (G5). (a) A short-channeltransistor, with W=6 mm and L=0.6mm (drawn) and a long-channeltransistor (W=60 mm, L=6 mm)

(b) The 6/0.6 characteristicsrepresented as a surface. (c) Along-channel transistor obeys asquare-law characteristic betweenIDS and VGS in the saturation region(VDS = 3 V). A short-channel

transistor shows a more linearcharacteristic due to velocitysaturation. Normally, all of thetransistors used on an ASIC haveshort channels.

(a)


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(b)


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(c)


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k'n= [2(L/W) IDS(sat)] /(VGS Vt)2= [2(6/60) (2.5x103 )]/[(3.0 0.65)2]= 9.05 x 105 AV2 ~ 90 mAV2

This value of k'n, calculated in the saturationregion, will be different (typically lower by afactor of 2 or more) from the value of k'n

measured in the linear region. We assumed the mobility, mn, and the

threshold voltage, Vt, are constants.


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For the p-channel transistor in the G5process, IDS(sat) = 850 mA (VDS= 3.0 V,VGS= 3.0 V, Vt = 0.85 V, W = 60 mm, L

= 6 mm). Then k'p=[2(L/W) IDS(sat)] /(VGS Vt)2

= [2(6/60) (850x106)]/[(3.0 (0.85))2]

= 3.68 x 105 AV2

P h l MOS i


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P-channel MOS transistor

The source and drain of CMOS transistors lookidentical.

The source of an n-channel transistor is lower inpotential than the drain and vice versa for a p-channel

transistor. In an n-channel transistor the threshold voltage, Vt, is

normally positive, and the terminal voltages VDSandVGSare also usually positive.

In a p-channel transistor Vt is normally negative and

we have a choice: We can write everything in terms ofthe magnitudes of the voltages and currents or we canuse negative signs in a consistent fashion.

P h l MOS i


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P h l MOS i


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Here are the equations for a p -channel transistor usingnegative signs:IDS=k'p(W/L)[(VGSVt) 0.5 VDS] VDS ; VDS> VGSVt

IDS(sat) = bp/2 (VGS Vt)2

; VDS< VGS Vt

In these two equations Vt is negative, and VDS& VGSare also normally negative (3 V


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MOSFET Capacitances

Overlap Capacitance


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Overlap Capacitance

Chapter 3 Metal Oxide Semiconductor (MOS)

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