ccd imagers V1 - epfl.ch · Autumn semester 2007 EPFL CCD Imagers Bibliography: « Solid-State...

Autumn semester 2007

EPFL

CCD Imagers

Bibliography:

« Solid-State Imaging with Charge-Coupled Devices », Albert J.P. Theuwissen, Kluwer academic publishers.


EPFL

CCD and CMOS Imagers

Main differences between these technologies:

CCD CMOS

sensing element MOS capacitor photodiode

pixel readout charge packet transfert voltage readout

matrix readout sequential windowing


EPFL

Ideal MOS capacitance

The charges applied to the gate of the CMOS

capacitance have to be compensated:

•Combination of small amount of minority carriers and ionized doping atoms

•Ionized doping atoms and no minority carriers available

•Enough minority carriers available

VG>0

P-Si

Depletion region

Neutral bulkx

VG

Ф

x

Equivalentbucket

0

DEEP DEPLETION

VG>0

P-Si

Depletion region

Neutral bulkx

VG

Ф

x

Equivalentbucket

0

VG

Ф

x

Equivalentbucket

0

DEEP DEPLETIONVG>0

P-SiNeutral bulkx

VG

Ф

x

Equivalentbucket

0

VG>0

P-SiNeutral bulkx

VG

Ф

x

Equivalentbucket

0

VG

Ф

x

Equivalentbucket

0

STRONG INVERSIONVG>0

P-SiNeutral bulkx

VG

Ф

x

Equivalent

bucket

0

VG>0

P-SiNeutral bulkx

VG

Ф

x

Equivalent

bucket

0

VG

Ф

x

Equivalent

bucket

0

WEAK INVERSION

CCD situation


EPFL

Real MOS capacitance

Influence of different parameters on the surface potential:

•Doping concentration of the silicon

•Thickness of the gate dielectric

•The gate voltage

10V 10V

P-Si Higher doped Si Lower doped Si

10V 10V

Ф

P-Si

10V 2V

Ф

P-Si


EPFL

Physic of the CCD

10V 10V

P-Si Qn=0 Qn=0.8 x Qn,sat

The potential wells might be filled with minority carriers.

This behavior can be compared to buckets which might be filled with water


EPFL

Charge transfert illustrationCharge transfer packet from one gate to another.

The movements of free carriers is driven by three different mechanisms:

1. the thermal diffusion2. self induced fields3. fringing fields

For complete charge transfer of a collapsing well, it is necessary to shape the clock pulses: trailing edge should be a slope and not a step

10V 0V0V 0V10V 0V0V 0V

10V 10V0V 0V10V 10V0V 0V

10V 10V0V 0V10V 10V0V 0V

5V 10V0V 0V5V 10V0V 0V

0V 10V0V 0V0V 10V0V 0V

1/

2/

3/

4/

5/


EPFL

Charge transfer mechanisms (1/4)

• Thermal diffusion of charge carriers:

even in absence of any electric field, a charge packet will

redistribute its local gradient by means of thermal diffusion;

y

tyQqDJ n

ndiffδ

δ ),(=

nnq

kTD µ=

y

tyJ

t

tyQn

δ

δ

δ

δ ),(),(=

−=

²4

²exp).0(

²

8)(

L

tDQntQn nπ

π

Thermal diffusion current

Current density transfer in amount

of charge

Thermal diffusion amount of charge

With L, the gate length and Dn, the diffusion constant


EPFL


• Self induced fields:

A gradient in charge concentration will repel the charges to decrease the gradient;

snns EQJ ..µ=

Current due to the self induced field Es

Current density transferred in amount of charge

Thermal diffusion and self-induced drift processes can be combined

using a diffusion effective constant:

( )

n

Dox

n

snn

n

DCC

Q

y

EµQy

t

tyQ

+

+=

=

1.

..

),(

β

δ

δ

δ

δ

δ

δn

Dox

neff D

CC

QD .1

.

+

+=

β


EPFL


• Fringing fields:

Fringing fields are the electric field due to the gate voltage, which

allow the devices to operate faster. This surface potential is set by the gate voltage and is also influenced by its neighboring gates. It is geometry dependant.

fnns EQJ ..µ=

Current due to the fringing field Ef

Fringing field:

( )

4

min,1/5

/5.

2.

².

+

∆=

Lx

LxV

L

tAE

d

doxf

0V 5V 10V 0V

Ф Ef,min=0

0V 5V 10V 0V

Ф Ef,min=0

0V 5V 10V 0V

Ф

0V 5V 10V 0V

Ф Ef,min≠ 0

Schematic illustration of the surface potential without fringing fields

Schematic illustration of the surface potential with fringing fields


EPFL


10-4

10-5

10-6

10-7

10-8

10-9

10-10

Time (s)

1 10 100Gate length (µm)

Thermal d

iffusion

NA=1016/cm3

NA=2.1014/cm3

tox=100nm

∆VG=10V

Compared to fringing field induced transfer, thermal diffusion and self-induced drift are slow processes.

Transport time as a function of gate length, with the thermal diffusion as a theoritical limit


EPFL

Charge transfer efficiencyThe charge-transfer process is degraded by:

– the limited time available to perform the charge transport;

– charge trapping by the surface states.

0

90

99

99,9

99,99

99,999

Transfer efficiency

(%)

0 10 20 40 50 time (ns)

tox=100nm

L=10µm

NA=1015/cm3

Ef,min=90V/cm

NA=2.1014/cm3

Ef,min=410V/cm

Transfer efficiency as a function of the transfer time

Charge trapping process:

1/ electrons are “falling” from the conduction band into the lower energy levels of the surface states;

2/ these electrons not recombine (no holes)

3/ they become free again and move forward a potential well, containing a different charge packet (the charge packet where the electrons originally come from has already moved)

Time to transfer influence


EPFL

Transfer time optimization

To optimize the transfer efficiency:

1. A transfer time available long enough;

2. A low number of surface state (to minimize the interactions)

3. High fringing field to speed up the transfer speed;


EPFL

SCCD and BCCD

Surface channel CCD Buried channel CCD

0V 5V10V 10V 0V 5V

Ф

x

0V 5V10V 10V 0V 5V

Ф

x

Fringing fields in different depths

SCCD BCCD:

n-type channel added to move the transport channel more deeper, and derive a maximum of the fringing field.

VG>0

p-SiNeutral bulkx

Qn

VG

Ф

x0

Qn ≠ 0

VG

Ф

x0

Qn = 0

Cox

CD

Cox

CD

VG>0

p-SiNeutral bulkx

n-Si

VG

Ф

x0

Qn ≠ 0

VG

Ф

x0

Qn = 0

Cox

CD1

CD2

Cox

CD1

CD2


EPFL

BCCD

Charge transport in buried-channel CCD take

place in the bulk:

+ Maximum value of the fringing fields to speed up the charge transport

+ Any interaction with the interface states (no charge trapping)

- Charge handling capability smaller (~ one-third of a charge packet compared to the SCCD)


EPFL

Transport systems

Different sections of a CCD: input, transport, output

CCD can be driven in a four-phase system, a three-phase system, a two-phase system, a one and a half system, a virtual phase system or a ripple-clock mode.

Ф5

p-Si

Ф2 Ф3 Ф4Ф1 Ф6

n+

input

n+

output

transport

Charges packets are transported under the influence of digital pulses applied to the CCD gates


EPFL

Four phase clocking system

Ф1Ф2 Ф3 Ф4Ф1 Ф2

t1

t2

t3

t4

t5

t6

t7

t

Ф2

Ф3

Ф4

Ф1

t1 t2 t3 t4 t5 t6 t7 t1 t2

Ф2

Ф3

Ф4

Ф1

t1 t2 t3 t4 t5 t6 t7 t1 t2

Charge transport section Timing diagram

one CCD cell = four CCD gates

Smaller potential well = 2 CCD gates

Drawbacks: the charge storage is limited to 50% of the CCD cell


EPFL

three phase clocking system


t1

t2

t3

t4

t5

t6

t

Ф2

Ф3

Ф1

t1 t2 t3 t4 t5 t6 t1


one CCD cell = three CCD gates

Smaller potential well = one CCD gates

Drawbacks: the charge storage is limited to 33% of the CCD cell


EPFL

two phase clocking system (1/2)

Ф2 Ф1Ф1

t1

t2

t3

t4

t5

t


Ф2

Ф1

t1 t2 t3 t4 t5 t1

one CCD cell = four CCD gates

Smaller potential well = one CCD gates

The charge storage is limited to 25% of the CCD cell

- More complicated CCD structure;

- Smaller charge-handling capability; + very simple clock

- Unidirectional transport


EPFL

two phase clocking system (2/2)


Ф2 Ф1Ф1

n+

t1

t2

t3

t

Ф2

Ф1

t1 t2 t3 t1 t2 t3

Extra n-type-doped region under the CCD gates (potential locally deeper)

More reproducible than the previous technology.


EPFL

One-and-a-half phase clocking system

Ф1Ф1

n+

t1

t2

t3

t

ФDCФDC


ФDC

Ф1

t1 t2 t3 t1 t2 t3

The second clocking gate ФDC

is a DC signal, with a level between the positive and the negative levels of Ф1


EPFL

Virtual phase system

Ф1 Ф1Ф1

n

t1

t2

t3

t

p


Ф1

t1 t2 t3 t1 t2 t3

One phase transport system.

The non-clocking phase is internally-biased.

Limitation of the charge storage


EPFL

Ripple clocking systemФ5Ф2 Ф3 Ф4Ф1 Ф6 Ф7 Ф1

t1

t2

t3

t

t4

t5

t6

t7

t8

t9

Charge transport sectionTiming diagram

Ф6

Ф7

Ф5

tt1 t2 t3 t4 t5 t6 t7 t8 t9

Ф2

Ф3

Ф4

Ф1

+ Compactness / Charge storage capacity 50%

- Slow clocking / High clock number


EPFL

Systems pros and cons

four-phase system - - ~ 50% - -

three-phase system - ~33% -

one and a half system + ~50% + +

virtual phase system + ~50% + + +

ripple-clock mode. + + + ~50% - - -

two-phase system

compactnesscharge-handling

capabilityclock waveform

- complicated

structure~25% +


EPFL

Channel definitionФ5Ф2 Ф3 Ф4Ф1 Ф6

n+

input

n+

output

Channel definition


n+

input

n+

output

Channel definition

Top view

Channel definition can be done by:

Channel stopper implant Oxide isolation DC biased field shields

p+

Ф

Ф

p-Si

p+

Ф

Ф

p-Si

Ф

Ф

p-Si

Ф

Ф

p-Si

Ф

p-Si

Ф0V 0V

Ф

p-Si

Ф0V 0V


EPFL

Input structures

Input structure: to supply minority carriers

(in imaging, input structures useful to test the devices)

A diode,

as a source in MOS transistor

To control the amount of stored charges, two alternatives:

-The “diode cut-off” technique trough VS;

-The” fill and spill” method through VG

n+

VG

p-Si

Vs


EPFL

Diode cut-off technique

p-Si

Ф2 Ф3Ф1

n+

VsVG

t1

t2

t3

t

t4

t5


Ф2

Ф3

VG

Ф1

t1 t2 t3 t4 t5 t

+ elementary construction

- noise and no-linearity problems


EPFL

Fill and spill techniqueCharge transport section

Timing diagram

p-Si

Ф2 Ф3

n+

VsVDC VIN

t1

t2

t3

t

t4

t5

t1 t2 t3 t4 t5

t

Ф2

Ф3

VS

t1 t2 t3 t4 t5

t

Ф2

Ф3

VS

Input structure:

diode combined with 1 or 2 extra MOS capacitors

- Limited charge handling capacity


EPFL

Output structures

Output structure:

measure the charge carriers contained in a potential well and convert it in a voltage

Two different outputs structures:

-the floating diffusion with reset

-the floating gate without reset


EPFL

The floating diffusion output

Ф2 Ф3

n+

VDC

VDD

Vout

RL

ФR

t1

t2

t3

t

t4

t5

Ф2

Ф3

VOUT

ФR

t1 t2 t3 t4 t5 t

Most widely used output structures


EPFL

The floating gate output

Ф2 Ф3

VDC

VDD

RL

ФR

t1

t2

t3

t

t4

Ф2 Ф3

For non-destructive read-out


EPFL

Conclusion

• Various transport mechanisms

• Different channel definitions

• Input structures (but not really important for CCD imaging applications)

• Output structures (extremely important)

ccd imagers V1 - epfl.ch · Autumn semester 2007 EPFL CCD Imagers Bibliography: « Solid-State...

Documents

Transcript of ccd imagers V1 - epfl.ch · Autumn semester 2007 EPFL CCD Imagers Bibliography: « Solid-State...