bo don kenh mux

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    KhoaKhoa CNTTCNTTBoBo monmon KyKy thuathuatt MaMayy ttnhnh

    Pham Tng Hai

    oan Minh Vng

    Phan nh The Duy

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    Logic Design 1 - Chapter 4 2

    TTii liliuu thamtham khkhoo

    Digital Logic Design Principles, N. Balabanian &B. Carlson John Wiley & Sons Inc., 2004

    Digital Design, 3

    rd

    Edition, J.F. Wakerly,Prentice Hall, 2001

    Digital Systems

    , 5

    th

    Edition, R.J. Tocci, PrenticeHall, 1991

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    Logic Design 1 - Chapter 4 3

    ChngChng 4.4.

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    4/18Logic Design 1 - Chapter 4 4

    DDnn nhnhpp

    Mch s c cc ng ra chph thuc vo gi tr/trng thi ca ccng vo thi im hin hnh c gi l mch lun l t hp(combinational logic circuits) hay gi tt l mch t hp

    C th c nhiu mch t hp c thit k p ng cng 1 chcnng ra. Cc mch s ny c nh gi (nhm la chn mchno thch hp hn) da trn nhiu yu t khc nhau. Tc hot ng

    phc tp Gi thnh phn cng

    Nng lng tiu tn

    S p ng v mt linh kin

    Thit k ch trng tng yu t ny c th dn n s gim st

    yu t khc

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    5/18Logic Design 1 - Chapter 4 5

    MMchch ccngng nhnh phnphn

    Mch thc hin tc v cng i vi 2 gi tr nh phn

    Hiu sut ca mch nh gi theo tc thc hin php ton C th da trn cc cng lun l ch to theo cng ngh thin v tc

    Tc c th tng ng k ty theo cch thit k mch m khng quph thuc vo cng ngh ch to cng lun l

    Cn nhc la chn gia thit k u tin cho tc v thit k thinu tin cho chi ph phn cng

    S khi ca mch cng nh phn

    Y

    S

    n

    n n+1

    Binary

    Adder

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    MMchch ccngng (MC)(MC) totonn phphnn

    C th xy dng mch cng 2 s nh phnn-bitt cc mch cng nh phn 1-bit

    S khi ca mch cng

    ton phn (full adder) Bng s tht Ba Karnaugh

    xi

    yi

    Full

    Adder

    Si

    Ci+1

    Ci

    Ci yi xi Si Ci+1

    0

    0

    0

    01

    1

    1

    1

    0

    0

    1

    10

    0

    1

    1

    0

    1

    0

    10

    1

    0

    1

    0

    1

    1

    01

    0

    0

    1

    0

    0

    0

    10

    1

    1

    1

    00 01 11 100 1 1

    1 1 1Ci

    yixiSi

    00 01 11 10

    0 1

    1 1 1 1Ci

    yixiCi+1

    Dng hm ca cc ng ra

    Si = xi yi Ci + xiyi Ci

    + xi yi Ci + xiyi Ci

    = xi yi CiCi+1 = xiyi + xi Ci + yi Ci

    = xiyi + Ci (xi + yi)

    = xiyi + Ci (xiyi + xi yi)= xiyi + Ci (xi yi)

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    Logic Design 1 - Chapter 4 7

    MCMC bbnn phphnn vv MCMC rippleripple--carrycarry

    Mch cng ton phnSi = xi yi CiCi+1 = xiyi + Ci (xi yi)

    Mch cng bn phn(half adder)

    xiyi

    Si

    Ci+1

    Ci

    xi

    yi

    Half

    Adder

    Si

    Ci+1

    xi

    yi

    Si

    Ci+1

    Mch cng ripple-carry

    Gii hn do thi gian tr ca cc tnhiu carry !

    Fu

    llAd

    der

    A3

    B3

    C3

    S3

    Fu

    llAd

    der

    A2

    B2

    C2

    S2

    Fu

    llAd

    der

    A1

    B1

    C1

    S1

    Ha

    lfAd

    der

    A0

    B0

    C4

    S0

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    Logic Design 1 - Chapter 4 8

    MMchch ccngng CarryCarry--LookaheadLookahead

    Tnh carry t cc bit ca tonhngA,B v Co

    nh nghaGenerated Carry Gi = AiBi

    Propagated CarryPi = Ai Bi Ta tnh c

    Ci = Ai-1Bi-1 + Ci-1 (Ai-1 Bi-1)= Gi-1 + Pi-1 Ci-1

    = Gi-1 + Pi-1 (Gi-2 + Pi-2 Ci-2)

    = Gi-1 + Pi-1 Gi-2 + Pi-1Pi-2 Ci-2

    Tnh ln ltC1 = G0 + P0 C0

    C2 = G1 + P1 G0 + P1P0 C0

    C3 = G2 + P2 G1 + P2P1 G0 + P2P1P0 C0

    C4 = G3 + P3 G2 + P3P2 G1+ P3P2P1 G0

    + P3P3P1P0 C0

    P1

    P2

    P3

    G1

    G2

    C0

    P0

    G0

    P1

    P2

    P3

    P2

    P3

    G3

    P3

    C4

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    Logic Design 1 - Chapter 4 9

    MMchch ccngng CarryCarry--LookaheadLookahead

    Tng qut

    Ci+1 = Gi + Pi Gi-1 + PiPi-1 Gi-2 + PiPi-1Pi-2 Gi-3 +

    + PiPi-1Pi-2 P1 G0 + PiPi-1Pi-2 P1P0 C0Mch cng Carry-Lookahead

    1

    2

    3

    S0

    1

    2

    3

    S1C1

    C2

    C3

    C4

    P1

    P2

    P3

    S2G

    1

    G2

    G3

    S3

    0

    0

    C0

    P0

    G0

    P1

    P2

    P3

    Carry

    -Look

    ah

    ea

    d

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    Logic Design 1 - Chapter 4 10

    MMchch trtr nhnh phnphn

    Biu din s nguyn m nh phn di dng b 2

    Mch cng 2 s di dng b 2 c khc g so vi mch

    cng nh phn xem xt ?Mch tr c thay th bng mch chuyn i b 2 v

    mch cng

    A1A2A3

    S0

    B1B2B3

    S1

    C1C2C3C4

    S2

    M

    S3

    A0

    B0

    Overflow

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    Logic Design 1 - Chapter 4 11

    BB ddnn knhknh

    D liu sinh ra v tr A nhng c s dng v tr B truyn d liu t A n B qua knh truyn thng

    Lm sao c th truyn d liu t nhiu ngun khc nhau trn

    cng mt knh truyn duy nht ?

    C ch cho php chn d liu no truyn trn knh truyn gi l kthut dn knh (multiplexing)

    Thit b thc hin dn knh gi l b dn knh (multiplexer)

    Pha thu, u bn kia ca knh truyn thng, cn b phn knh(demultiplexer) phn phi d liu trn knh truyn n cc ng ra

    communication

    channeldatain

    dataout

    Mu

    ltiple

    xer

    Demu

    ltip

    lexer

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    Logic Design 1 - Chapter 4 12

    BB ddnn knhknh

    B dn knh s l mch c 2n ng d liu vo

    1 ng d liu ra

    n ng vo selecthay selector

    B dn knh vi n = 3

    Mu

    ltiple

    xer

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    r

    s0

    s1

    s2

    D0

    r

    s0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    s1

    s2

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    Logic Design 1 - Chapter 4 13

    XyXy ddngng mmchch tt hhpp tt bb ddnn knhknh

    Tn ti cc mch dn knhc thng mi ha didng MSI

    Dng b dn knh hinthc 1 mch t hp bt k ?

    B dn knh c dng 2 lpAND-OR

    Cng AND c n+1 ng nhp

    Dng s-o-p chnh tc ca 1hm chuyn mch n+1 bin

    B dn knh m-1 selectorcth c s dng hinthc mch t hp ca hm mbin

    Th df(x, y, z) = (1, 2, 4, 7)

    = z y x + z y x + z y x + z y x

    gn s0 = y v s1 = z

    f = s1 s0 x + s1 s0x + s1 s0 x + s1 s0x

    = s1 s0 D0 + s1 s0D1 + s1 s0 D2 + s1 s0D3

    suy ra D0 = D3 = x v D1 = D2 = x

    V mch ?

    Th df(w, x, y, z) = (0, 4, 9, 13, 14)

    Thit k ?

    V mch ?

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    Logic Design 1 - Chapter 4 14

    BB gigiii mm BB mm hhaa

    Mch t hp nhn n ng nhp (n 1) v nh tuyn dliu t cc ng nhp n mt trong s ti a 2n ng ra

    gi l b gii m (decoder)B m ha (encoder), mch ngc li vi b gii m, l

    mch nhn d liu t mt s rt ln cc ng nhp

    ri bin i thnh d liu xut ra trn mt s nh hncc ng xut (khng nht thi t ch1 ng xut)

    C s gn ging gia

    B m ha vi b dn knh B gii m vi b phn knh

    Hy chra s khc bit gia cc mch trn ?

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    Logic Design 1 - Chapter 4 15

    BB phnphn knhknh

    B phn knh vi 8ng xut Mch lun l

    Bng s tht

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    C0

    C1

    C2

    Datainput

    x

    Control inputs Data outputs

    C2 C1 C0 D0 D1 D2 D3 D4 D5 D6 D7

    0 0 0 x 0 0 0 0 0 0 0

    0 0 1 0 x 0 0 0 0 0 0

    0 1 0 0 0 x 0 0 0 0 0

    0 1 1 0 0 0 x 0 0 0 0

    1 0 0 0 0 0 0 x 0 0 0

    1 0 1 0 0 0 0 0 x 0 0

    1 1 0 0 0 0 0 0 0 x 0

    1 1 1 0 0 0 0 0 0 0 x

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    Logic Design 1 - Chapter 4 16

    BB gigiii mm ngng nn rara 22nn

    B gii m ng n ra 2n (n-to-2n line decoder) cxy dng t b phn knh 2n ng xut bng cch: B bt ng nhp d liux

    Mi cng AND chcn li n ng nhp

    B gii m ng 3 ra 8Control inputs Data outputs

    C2 C1 C0 D0 D1 D2 D3 D4 D5 D6 D7

    0 0 0 1 0 0 0 0 0 0 0

    0 0 1 0 1 0 0 0 0 0 0

    0 1 0 0 0 1 0 0 0 0 0

    0 1 1 0 0 0 1 0 0 0 0

    1 0 0 0 0 0 0 1 0 0 0

    1 0 1 0 0 0 0 0 1 0 0

    1 1 0 0 0 0 0 0 0 1 0

    1 1 1 0 0 0 0 0 0 0 1

    Deco

    der

    3x

    8

    D0

    D1

    D2

    D3

    D4

    D5

    D6

    D7

    s0

    s1

    s2

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    Logic Design 1 - Chapter 4 17

    BB gigiii mm ngng nn rara 22nn

    MSI gii m ng thng dng 2 4 , 3 8 , 4 16

    Gii m ma trn cng AND

    Gii m cy Xy dng mch t hp t cc

    b gii m ng

    74LS138

    A2A1A0

    E3

    E2E1

    Q7Q6Q5Q4Q3Q2

    Q1Q0

    74LS154

    E1E0

    A3A2A1A0

    1514

    1312111098765432

    10

    74LS139

    A1aA0aEa

    A1bA0bEb

    Q3aQ2aQ1aQ0aQ3bQ2bQ1bQ0b

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    Logic Design 1 - Chapter 4 18

    BBii ttpp

    Problem 4.4

    Problem 4.7

    Problem 4.10

    Problem 4.11

    Problem 4.12

    Thy Phan nh Th [email protected]