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Basic CMOS structures

Ramon CanalNCD2015

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MOS: Metal Over Silicon• Objectives:

– Design different types of logical structures through the use of MOS Technology

• An introduction to the basic concepts of combinational logic structures

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MOS Technology• Ideal behavior: digital switch

D

P

F

Puerta

Drenaje

Fuente

NMOSAcumulación

D

P

F

PMOSAcumulación

D F

P = 0

D F

P = 1

D F

P = 1

D F

P = 0

Drenador

Gate

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MOS Technology• CMOS Inverter: Complementary MOS

D

P

F

D

P

F

1 (VDD)

Input Output

1 (VDD)

Input = 0 Output = 1

1 (VDD)

Input = 1 Output = 0

Input Output

0 (GND) 0 (GND) 0 (GND)

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MOS Technology• Series nMOS transistors:

– Output = 0 if S1=1 and S2=1

D

P

F

D

P

F

S1

S2

S1= 0

S2= 0

S1= 1

S2= 0

S1= 0

S2= 1

S1= 1

S2= 1

Output

DM, Tardor 2004 6

MOS Technology• Series nMOS transistors:

– Output = 1 if S1=0 and S2=0

D

P

F

D

P

F

S1

S2

S1= 1

S2= 1 S2= 1

S1= 0 S1= 1

S2= 0

S1= 0

S2= 0

Output

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MOS Technology• Paralꞏlel nMOS transistors:

– Output = 0 if S1=1 or S2=1

D

P

F

D

P

F

S1 S2

S2= 0S1= 0 S1= 0 S2= 1

S2= 1S1= 1S1= 1 S2= 0

Output

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MOS Technology• Paralꞏlel nMOS transistors:

– Output = 1 if S1=0 or S2=0

D

P

F

D

P

F

S1 S2

S1= 1 S2= 1 S1= 1 S2= 0

S2= 0S1= 0S1= 0 S2= 1

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Complementary CMOS• Complementary CMOS logic gates

– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

Pull-up OFF Pull-up ONPull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

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CMOS Gates• NAND

VDD

GNDBA

out

1

0

0

1A

B

OUT

1 1

1 0

(A+B)

(A · B)

Pull−down

Pull−up

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CMOS Gates• NOR

(A · B)

VDD

GND

BA

out1

0

0

1A

B

OUT

(A+B)

Pull−down

Pull−up

0 0

01

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CMOS Gates• Complex gates

VDD

GND

BA

out

C

D

C

B

A

D

OUT

0

1

AB00 01 11 10

00

01

11

10

CD

1 1 1

1 0 0

0 0 0 0

1 1 1 1

D + (A · B · C)

D ·(A+B+C)

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CMOS Gates• Design of inverted functions :

– F= !(……)– AND “”:

• Pull-down: Transistors nMOS in series• Pull-up: Transistors pMOS in parallel

– OR “+”:• Pull-down: Transistors nMOS in parallel• Pull-up: Transistors pMOS in series

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General CMOS structure:

VDD

GND

PULL

UP

PULL

DOWN

Out

In1

In2

In3

In1

In2

In3

C1

C3

C2

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MOS transistor resistance• An approximation to the drive current ability.

• The resistance is:– Directly proportional to the channel Length (L).– Inversely proportional to the transistor width (W).

– R~L/W

• In bulk CMOS, pmos transistors have double the resistance of the nmos.

Rsp 2 Rs

• Transistor sizes can be defined as:• Real values (in lambdas or nm)• The ratio (i.e. Form factor) against the minimum sized (2λ)

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Ideal Voltage Transfer Curve

• The real curve is much more complex. It depends on the resistance and capacitances of all the materials/layers involved.

Vdd

Vout

VinVdd0 Vdd/2

Logic "1" output

Logic "0" output

B = NOT(A)A

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Real Voltage Transfer Curve

• The transfer curve determines the noise margins (NM) and the region of uncertainty.

Vout

Vin0

VOH

VOL

VIL VIH VOH

dVoutdVin

= −1

dVoutdVin

= −1

Vout = Vin

VOL

VIL

VIH

VOH

Vin Vout

NMH

NML

TransitionRegion

Vin Vout

VDD

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CMOS Inverter• Function implemented in the pull-up and the pull-down• Small static power when compared to previous

technologies (i.e. Nmos, bipolar)

VDD

GND

PULL

UP

PULL

DOWN

Vin Vout

F(Vin) =1 −> Vout=0

Red transistoresacumulación

Vout

VDD

GND

Lpu/Wpu

(Zpu)

(Zpd)

Lpd/Wpd

Vin

F(Vin) =1 −> Vout=1

Red transistoresacumulación

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CMOS Inverter

VinVout

VDD

GND

Zpu

Zpd

VDD0 DD0.5V

Vout

Vin

VDD

HighZpu/Zpd

LowZpu/Zpd

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Inversor CMOS• Simetrical delays if Rpu=Rpd (given 1Rsp = 2Rs)

VinVout

VDD

GND

Zpu

Zpd

VDD

GND

VDD

GND

Vin=1 Vout=0 Vin=0 Vout=1

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CMOS Inverter DelaysVDD

GND

1:1 1:1

D A D B

g

Vout = 1Vi = 0Vin = 1

1:2 1:2

10 C

VDD

GND

1:1 1:1

D A D B

g

Vin = 0 Vi = 1 Vout = 0

1:2 1:2

10 C

1 1

2 4 2 2 32 2 2 22 23 10 132 4

i g g g

s g sp g

C C C C

R C R C

0 0

1 2

2 23 10 134 2

sp s

sp g s g

R R

R C R C

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Other CMOS gates

PU(A,B)=A+B

VDD

A

B

C

GND

NAND

VDD

A

B

C

GND

NOR

1:4

1:4

PD(A,B)=A+B

PU(A,B)=A B

PD(A,B)=A B

1:2

1:2 1:1 1:1

1:21:2

DM, Tardor 2005 23

Case study

Standard Cell implementation

DM, Tardor 2005 24

Standard Cell Implementation• Cells designed in a certain pattern• Due to the standard pattern they can be

used in several circuits

+ Design reuse- Non-adaptative design

DM, Tardor 2005 25

A typical MOS gate VDD

GND

PULL

UP

PULL

DOWN

Out

In1

In2

In3

In1

In2

In3

C1

C3

C2

DM, Tardor 2005 26

Standard Cell Structure

DM, Tardor 2005 27

Standard Cell Structure

P-diff

N-diff

VDD

GND

Channel for interconnects (poly or metal)

Metal 1

Metal 3

Metal 2

Metal 4

Metal 5

Poly

DM, Tardor 2005 28

Standard Cell Structure

P-diff

N-diff

VDD

GND

Metal 1

Metal 3

Metal 2

Metal 4

Metal 5

Poly

The inputs of the transistors are connected to the poly layer. Horizontal connections are not recommendable since they increase the manufacturing costs.

IN IN

IN

IN IN

DM, Tardor 2005 29

Standard Cell Structure

P-diff

N-diff

VDD

GND

Metal 1

Metal 3

Metal 2

Metal 4

Metal 5

Poly

The inputs of the transistors are connected to poly or to metal –in case they are lateral inputs.

IN IN

IN

IN IN

DM, Tardor 2005 30

Standard Cell Structure

P-diff

N-diff

VDD

GND

Transistors are placed in a serial way. If we want them in paralꞏlel we will have to add metal connections.

A OUT

B

IN

CA

DM, Tardor 2005 31

Standard Cell Structure

P-diff

N-diff

VDD

GND

Transistors are placed in a serial way. If we want them in paralꞏlel we will have to add metal connections.

A OUT

B

IN

CA

CBAOUT

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Basic CMOS structures

Ramon CanalNCD2015