From transistors to digital logiccomputer- 2018-02-06آ  Complementary MOS or CMOS. CMOS processes...

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Transcript of From transistors to digital logiccomputer- 2018-02-06آ  Complementary MOS or CMOS. CMOS processes...

  • A

    GND

    VDD

    Y

    Computer Architecture Paul Mellies

    From transistors to digital logic

  • 1 0

    1

    1

    0 0

    0 0 1

    1 1

    1

    0

    0

    0 0

    000 1 1

    1 1

    0

    The digital abstraction

    Every light bulb is either ON or OFF

  • The digital abstraction

    Every light bulb is either ON or OFF

    1 0 1 0 0 1 0 0

    1 0 0 1 10 1 1

    1 0000 1 1 0

  • Additional idea : transistors are switches !

    drain

    source

    gate

    gate = 0 gate = 1

    drain

    source

    gateNMOS

    PMOS

    source

    drain

    source

    drain

    source

    drain

    source

    drain

    ON

    ON

    OFF

    OFF

  • Additional idea : transistors are switches !

    drain

    source

    gate

    gate = 0 gate = 1

    drain

    source

    gateNMOS

    PMOS

    source

    drain

    source

    drain

    source

    drain

    source

    drain

    ON

    ON

    OFF

    OFF

    good for 0’s bad for 1’s

    good for 1’s bad for 0’s

  • Additional idea : transistors are switches !

    drain

    source

    gate

    gate = 0 gate = 1

    drain

    source

    gateNMOS

    PMOS

    source

    drain

    source

    drain

    source

    drain

    source

    drain

    ON

    ON

    OFF

    OFF

    good for 0’s bad for 1’s

    good for 1’s bad for 0’s

    Fine, but what does that mean exactly ?

  • gate

    source of electrons

    drain of electrons

    gate

    source of holes

    drain of holes

    N-channel MOSFET enhancement mode

    P-channel MOSFET enhancement mode

    di re

    ct io

    n of

    th e c

    ur re

    nt �

    ow

    Enhancement-mode MOSFET transistors

    The device is OFF at rest. A positive voltage must then be applied to the gate

    wrt. the source in order to switch the device ON.

    The device is OFF at rest. A negative voltage must be applied to the gate wrt. the source in order to switch the device ON.

  • gate

    source of electrons

    drain of electrons

    gate

    source of holes

    drain of holes

    N-channel MOSFET enhancement mode

    P-channel MOSFET enhancement mode

    di re

    ct io

    n of

    th e c

    ur re

    nt �

    ow

    Enhancement-mode MOSFET transistors

    The device is OFF at rest. A positive voltage must then be applied to the gate

    wrt. the source in order to switch the device ON.

    The device is OFF at rest. A negative voltage must be applied to the gate wrt. the source in order to switch the device ON.

    body body

  • A 3D picture of an NMOS transistor

    Picture reproduced from the excellent book by Jaeger and Blalock : Microelectronic -- Circuit Design ( Mac Graw Hill, fourth edition )

  • The three operation modes of a NMOS transistor

    = 0DI

    VTN

    CUT-OFF

    GSV +

    _

    DSV +

    _

    ID

    drain

    source

    gateGSV

    TNwhere V denotes the threshold voltage

  • Here, Kn denotes the transductance parameter of the NMOS transistor

    The three operation modes of a NMOS transistor

    VTN

    LINEAR OR TRIODE

    ≥ ≥ GSV +

    _

    DSV +

    _

    ID

    drain

    source

    gate

    DSVGSV

    TNwhere V denotes the threshold voltage

    0-

    VTNVGS 2 DSV

    nK DSV--D = I

  • The linear or triode operation mode

    GSV +

    _

    DSV +

    _

    ID

    Drain-source voltage ( V )

    drain

    source

    gate

    Dr ain

    -so ur

    ce cu

    rre nt

    ( μ A )

    800

    600

    400

    200

    0 0 0.2

    GSV = 5 V

    GSV = 4 V

    GSV = 3 V

    GSV = 2 V

    0.4 0.6 0.8

  • Exercise :

    For this speci�c NMOS transistor, can you give for each Gate-Source Voltage :

    2 V 3 V 4 V 5 V

    an approximation of the Drain-Source resistance at the origin ?

  • pMOS transistors work in just the opposite fashion, as might be guessed from the bubble on their symbol shown in Figure 1.31. The substrate is tied toVDD. When the gate is also atVDD, the pMOS transistor is OFF.When the gate is at GND, the channel inverts to p-type and the pMOS transistor is ON.

    Unfortunately, MOSFETs are not perfect switches. In particular, nMOS transistors pass 0’s well but pass 1’s poorly. Specifically, when the gate of an nMOS transistor is at VDD, the drain will only swing between 0 and VDD−Vt. Similarly, pMOS transistors pass 1’s well but 0’s poorly. However, we will see that it is possible to build logic gates that use transistors only in their good mode.

    nMOS transistors need a p-type substrate, and pMOS transistors need an n-type substrate. To build both flavors of transistors on the same chip, manufacturing processes typically start with a p-type wafer, then implant n-type regions called wells where the pMOS transistors should go. These processes that provide both flavors of transistors are called Complementary MOS or CMOS. CMOS processes are used to build the vast majority of all transistors fabricated today.

    In summary, CMOS processes give us two types of electrically controlled switches, as shown in Figure 1.31. The voltage at the gate (g) regulates the flow of current between the source (s) and drain (d). nMOS transistors are OFF when the gate is 0 and ON when the gate is 1. pMOS

    n

    p

    gate source drain

    substrate

    n

    (a) GND

    GND

    n

    p

    gatesource drain

    substrate

    n

    (b)

    VDD

    GND

    - - - - - - -

    channel

    +++++++

    Figure 1.30 nMOS transistor operation

    Gordon Moore, 1929–. Born in San Francisco. Received a B.S. in chemistry from UC Berkeley and a Ph.D. in chemistry and physics from Caltech. Cofounded Intel in 1968 with Robert Noyce. Observed in 1965 that the number of transistors on a computer chip doubles every year. This trend has become known as Moore’s Law. Since 1975, transistor counts have doubled every two years.

    A corollary of Moore’s Law is that microprocessor performance doubles every 18 to 24 months. Semiconductor sales have also increased exponentially. Unfortunately, power consumption has increased exponentially as well (© 2006, Intel Corporation. Reproduced by permission).

    g

    s

    d

    g

    d

    s

    nMOS

    pMOS

    g = 0

    s

    d

    d

    s

    OFF

    ON

    g = 1

    s

    d

    d

    s

    ON

    OFF

    Figure 1.31 Switch models of MOSFETs

    30 CHAPTER ONE From Zero to OneThe two switching positions of an NMOS transistor

    switched OFF switched ON

    Threshold voltage : voltage required to turn on a transistor

    Note : the MOS terminal which is acting as the drain is determined by the potentials.

  • Here, just as before, Kn denotes the transductance parameter of the NMOS transistor

    GSV +

    _

    DSV +

    _

    ID

    drain

    source

    gate

    VTN ≥ ≥ DSV GSV 0-

    The three operation modes of a NMOS transistors

    SATURATION

    TNwhere V denotes the threshold voltage

    VTNVGS2 nK -D = I

    2

  • Voltage Gate-Source

    Voltage Drain-Source

    Summary : the three modes of an NMOS transistor

    V -GS

    VTN

    VTN

    cut-o� saturation

    linear

  • Voltage Gate-Source

    Voltage Drain-Source

    Summary : the three modes of an NMOS transistor

    V -GS

    VTN

    VTN

    cut-o� saturation

    linear

    VTNVGS2 nK -D = I

    2

    VTNVGS 2 DSV

    nK DSV--D = I

  • Summary : the three modes of an NMOS transistor

    V + DS

    VTN

    V TN

    Voltage Gate-Source

    Voltage Drain-Source

    cut-o�

    saturation

    linear

  • Summary : the three modes of an NMOS transistor

    V + DS

    VTN

    V TN

    Voltage Gate-Source

    Voltage Drain-Source

    cut-o�

    saturation

    linear

    VTNVGS2 nK -D = I

    VTNVGS 2 DSV

    nK DSV--D = I

    2

  • Summary : the three modes of an NMOS transistor

    V + DS

    VTN

    V TN

    Voltage Gate-Source

    Voltage Drain-Source

    cut-o�

    saturation

    linear

    VTNVGS 2 DSV

    nK DSV--D = I

    VTNVGS2 nK -D = I

    2

    VDS2 nK

    D = I 2

  • Characteristics of the NMOS transistor

    GSV +

    _

    DSV +

    _

    ID