CMOS Transistors, Gates, and...
Transcript of CMOS Transistors, Gates, and...
CMOS Transistors, Gates, and Wires
6.375 Complex Digital SystemsChristopher BattenFebruary 15, 2006
Cd
RP
CgCW/2CW/2
RW
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 2
Should the hardware abstraction layers make today’s lecture irrelevant?
Algorithm
Circuits
Application
Guarded Atomic Actions
Register-Transfer Level
Devices
Gates
Physics
Previous Two Lectures
Today’s Lecture
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 3
Should the hardware abstraction layers make today’s lecture irrelevant?
Algorithm
Circuits
Application
Guarded Atomic Actions
Register-Transfer Level
Devices
Gates
Physics
Physical design issues are increasingly pushing their way up the abstraction layers
It is essential for modern digital designers to have some intuition about the lower level physical design issues
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 4
CMOS Transistors, Gates, and Wires
input0
input1
output
TransistorsWires
Gates
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Metal Oxide-Semiconductor Field-Effect (MOSFET) Transistor
CONDUCTION:If a channel exists, a horizontal field will cause a drift current from the drain to the source.
EhSource diffusion
Drain diffusion
Gate
bulk
INVERSION:A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain.
Ev
Inversionhappens here
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Overview of operation of a NMOS transistor
Source diffusion
Drain diffusion
Gate
bulk
ID
VDS
ID
VGS
lg(ID)
VGS
V
timeVt Vt
VDSVGS
ID
Vin Vout
VGS
VDS
D
S
G
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Key qualitative characteristics of MOSFET transistors
• Threshold voltage sets when transistor turns on – also impacts leakage• IDS is proportional to mobility x (W/L)• NMOS mobility > PMOS mobility => ReffN < ReffP (assume mobility ratio is 2)• Increase W = Increase I = Decrease Reff
• Increase L = Decrease I = Increase Reff
• Cg proportional to ( W x L ) and Cd proportional to W
Width
Length
Cg CdReff
VoutVin
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 8
CMOS Transistors, Gates, and Wires
input0
input1
output
TransistorsWires
Gates
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 9
The most basic CMOS gate is an inverter
Vin Vout
WN/LN
WP/LP
Let’s make the following assumptions1. All transistors are minimum length2. All gates should have equal rise/fall
times. Since PMOS are twice as slow as NMOS they must be twice as wide to have the same effective resistance
3. Normalize all transistor widths to minimum width NMOS
2α
1α
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 10
The most basic CMOS gate is an inverter
Vin Vout
WN/LN
WP/LP 2α
1αA Y
VDD
GND
PMOS
NMOS
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 11
A simple RC model for the inverter can provide significant insight
Reff = Reff,N = Reff,PCg = Cg,N + Cg,PCd = Cd,N + Cd,P
Vin Vout Vin
Cg CdReff
Reff
Vout
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 12
A simple RC model for the inverter can provide significant insight
Vin
Cg CdReff
Reff
Vout
CL
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A simple RC model for the inverter can provide significant insight
Cg CdReff
Reff
Vout
CL
Vin = “0”
Charge RC Time Constant = Reff x ( Cd + CL )
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 14
The most basic CMOS gate is an inverter
Cg CdReff
Reff
Vout
CL
Vin = “1”
Discharge RC Time Constant = Reff x ( Cd + CL )
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 15
Larger gates are faster since they decrease Reff (but they also increase Cd!)
2
1
Cd = (0.5x1.42) + (1x2.40) = 3.11 fFCL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.37 fFTPLH = 2.2 x (10.83/1) x 5.37 = 128psTPHL = 2.2 x (4.93/0.5) x 5.37 = 116ps
2
1
4
2
2
1
Cd = (1x1.42) + (2x2.40) = 3.66 fFCL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.92 fFTPLH = 2.2 x (10.83/2) x 5.92 = 70.5psTPHL = 2.2 x (4.93/1) x 5.92 = 64.2ps
Ignores the fact that previous gate now must drive a bigger
gate capacitance!
kΩ/µm10.83Reff,P x µm
kΩ/µm4.93Reff,N x µm
fF/µm1.48Cg,P/µm
fF/µm1.55Cg,N/µm
fF/µm2.40Cd,P/µm
fF/µm1.42Cd,N/µm
UnitsValueParam
Process gen = 0.25µmSupply voltage = 5VMin width NMOS = 0.5µm
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 16
Simple RC model can also yield intuition on energy consumption of inverter
Cg CdReff
Reff
Vout
CL
Vin= “0”
2CV2)VC(C
V)dVC(CVdt
dtdVCV
dtdtdQVI(t) dtVP(t) dtE
DDDDLd
DD
0
outLdDD
T
0
DD
T
0
DD
T
0
DD
T
0
10
=+=
+==
===
∫∫
∫∫∫→
• During 0 1 transition, energy CVDD2 removed from power supply
• After transition, 1/2 CVDD2 stored in capacitor, the other 1/2 CVDD
2
was dissipated as heat in pullup resistance
• The 1/2 CVDD2 energy stored in capacitor is dissipated in the
pulldown resistance on next 1 0 transition
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 17
Larger gates use slightly more energy, real concern is affect on previous gate
2
1
Cd = (0.5x1.42) + (1x2.40) = 3.11 fFCL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.37 fFE0>1 = 5.37 x 52 = 134fJ
2
1
4
2
2
1kΩ/µm10.83Reff,P x µm
kΩ/µm4.93Reff,N x µm
fF/µm1.48Cg,P/µm
fF/µm1.55Cg,N/µm
fF/µm2.40Cd,P/µm
fF/µm1.42Cd,N/µm
UnitsValueParam
Process gen = 0.25µmSupply voltage = 5VMin width NMOS = 0.5µm
Cd = (1x1.42) + (2x2.40) = 3.66 fFCL = (0.5x1.55) + (1x1.48) = 2.26 fF
Cd+CL = 5.92 fFE0>1 = 5.92 x 52 = 148fJ
Ignores the fact that previous gate now must drive a bigger
gate capacitance!
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Was negligible, increasing due to thin gate oxidesGate Leakage
Usually negligibleDiode Leakage
Approaching 10-40% of active powerSubthreshold Leakage
Fast edges keep to <10% of cap charging current Short Circuit Current
Many other types of power consumption in addition to dynamic power
Cg CdReff
Reff
Cg CdReff
Reff
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 19
More complicated gates use more transistors in pullup/pulldown networks
For every set of input logic values, either pullup or pulldownnetwork makes connection to VDD or GND– If both connected, power rails would be shorted together– If neither connected, output would float (tristate logic)
VDD
VOUT
Pullup network, connects output to VDD, contains only PMOS
Pulldown network, connects output to GND, contains only NMOS
Input NInput 1
Input 0
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 20
Series and parallel MOSFET networks provide natural duals of each other
A BAA
B
AA
BA B
Conducts if A=1 OR B=1Conducts if A=1 AND B=1Conducts if A=1
Conducts if A=0 AND B=0Conducts if A=0 OR B=0Conducts if A=0
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 21
NAND and NOR gates illustrate the dual nature of the pullup/pulldown networks
A
B(A.B)
BA
(A.B)
A
B(A+B)
AB (A+B)
NAND Gate NOR Gate
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 22
Designers can use a methodical approach to build more complex gates
• Goal is to create an logic function– We can only implement inverting logic with one CMOS stage
• Implement pulldown network– Write – Use parallel NMOS for OR of inputs– Use series NMOS for AND of inputs
• Implement pullup network– Write pullup network– Use parallel PMOS for OR of complemented inputs)– Use series PMOS for AND of complemented inputs)
),x,x(fPD 21 K=
),x,x(f 21 K
),x,x(g),x,x(fPU 2121 KK ==
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 23
Designers can use a methodical approach to build more complex gates
A
B
C(A+B).C
C)BA(f ⋅+=
C)BA(PD ⋅+=
C)BA(
C)BA(
C)BA(PU
+⋅=
++=
⋅+=
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 24
CMOS Transistors, Gates, and Wires
input0
input1
output
TransistorsWires
Gates
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 25
Wires are an old problem
Cray-1 Wiring
Cray-31993
Cray-3 wiring
Cray-1 1976
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 26
Modern interconnect stacks have six to nine or more metal layers
IBM CMOS7 process6 layers of copper wiring1 layer of tungsten local interconnect
© IBM
© IBM
Metal 1
Metal 6
Metal 5
Metal 4
Metal 2Metal 3
Via 5-6
Via 1-2
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 27
Wire resistance is a function of height, width, and length
Width
LengthHeight
( )( ) widthheight
y resistivitlength resistance×
×=
• Height (Thickness) fixed in given manufacturing process• Resistances quoted as Ω/square• TSMC 0.18mm 6 Aluminum metal layers
– M1-5 0.08 Ω/square (0.5 mm x 1mm wire = 160 Ω)– M6 0.03 Ω/square (0.5 mm x 1mm wire = 60 Ω)
1.6x10-8 Ω-mbulk silver
1.7x10-8 Ω-mbulk copper
2.8x10-8 Ω-mbulk aluminum
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 28
Wire capacitance is relative to the substrate and to neighboring wires
• Capacitance depends on geometry of surrounding wires and relative permittivity (εr) of insulating dielectric– silicon dioxide (SiO2) εr = 3.9– silicon flouride (SiF4) εr = 3.1– SiLKTM polymer εr = 2.6
W1ε
W2
H2
H1
D12
DD1S1
Capacitive coupling to neighbors is becoming a
serious problem!
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 29
Wire capacitance is relative to the substrate and to neighboring wires
• Capacitance depends on geometry of surrounding wires and relative permittivity (εr) of insulating dielectric– silicon dioxide (SiO2) εr = 3.9– silicon flouride (SiF4) εr = 3.1– SiLKTM polymer εr = 2.6
• Can have different materials between wires and between layers, and also different materials on higher layers
W1
ε12
εD1
ε1
ε2
W2
H2
H1
D12
DD1S1
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 30
This IBM experimental 130nm process includes two metals and two dielectrics
E. Barth, IBM Microelectronics
Al
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 31
Distributed RC wire model gives accurate results but is computationally expensive
How does the delay scale with longer wires?– Wire delay increases quadratically– Edge rate also degrades quadratically
R1
C1
R2
C2
RN
CN
Rdriver
Cload
Ci
N
i
ij
1jjR Delay ∑ ⎟⎠⎞
⎜⎝⎛ ∑∝
=
=
Use Penfield-Rubenstein equation to find delay
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 32
Lumped Π model can provide a quick reasonable approximation
Cload
Rw
Cw/2 Cw/2
Rdriver
( ) ⎟⎠
⎞⎜⎝
⎛ +×++×∝ loadw
wdriverw
driver C2
CRR2
CR Delay
Rw is lumped resistance of the wireCw is lumped capacitancePartition half of Cw at each end
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Estimate the rise time of node A using an RC delay model
16
8
2
1
Metal 2 wire(250u x 0.250u)
A
Cg = ( 0.5 x 1.55 ) + ( 1 x 1.48 ) = 2.26 fFCd = (4 x 1.42 ) + ( 8 x 2.40 ) = 24.88 fFRp = 10.83/8 = 1.35 kΩRw = ( 250 / 0.25 ) x 0.07 = 70 ΩCw = (( 250 x 0.25 ) x 0.0016 ) + ( 250 x 0.084 ) = 21.14 fF
TPLH = 2.2 x ( 1350 x (21.14/2 + 24.88) + (1350 + 70) x (21.14/2 + 2.26) ) = 66ps
fF/µm0.084CL,M2 / µm
fF/µm20.016CA,M2 / µm2
Ω/sq0.07RM2 / sq
kΩ/µm10.83Reff,P x µm
kΩ/µm4.93Reff,N x µm
fF/µm1.48Cg,P / µm
fF/µm1.55Cg,N / µm
fF/µm2.40Cd,P / µm
fF/µm1.42Cd,N / µm
UnitsValueParam
Process gen = 0.25µmSupply voltage = 5VMin width NMOS = 0.5µm
Cd
RP
CgCW/2CW/2
RW
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 34
Estimate the rise time of node A using an RC delay model
16
8
2
1
Metal 2 wire(250u x 0.250u)
A
fF/µm0.084CL,M2 / µm
fF/µm20.016CA,M2 / µm2
Ω/sq0.07RM2 / sq
kΩ/µm10.83Reff,P x µm
kΩ/µm4.93Reff,N x µm
fF/µm1.48Cg,P / µm
fF/µm1.55Cg,N / µm
fF/µm2.40Cd,P / µm
fF/µm1.42Cd,N / µm
UnitsValueParam
Process gen = 0.25µmSupply voltage = 5VMin width NMOS = 0.5µm
How should we buffer up this signal? Should we have a few big stages or
many small stages?
16
8
8
2
2
1
6
3
2
1
16
8
14
7
10
5
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In deep submicron technologies many predicted an interconnect doomsday
National Technology Roadmap for Semiconductors, SIA, 1997
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 36
Is there really an interconnect doomsday looming?
--
Decrease
Decrease
Affect on Capacitance
Affect on Resistance
Scaling Impact
--~ ConstantHeight
IncreasesDecreasesWidth
DecreasesDecreasesLength
Local wire delay tracks improvement
in gate delay
R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, Apr 2001
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 37
Is there really an interconnect doomsday looming?
--
Decrease
--
Affect on Capacitance
Affect on Resistance
Scaling Impact
--~ ConstantHeight
IncreasesDecreasesWidth
--~ ConstantLengthGlobal wire delay
increases relative to wire delay!
R. Ho, K. Mai, M. Horowitz, Proc. of the IEEE, Apr 2001
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 38
No doomsday, just one more physical design issue to carefully manage
National Technology Roadmap for Semiconductors, SIA, 2005
6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 39
Take away points• Simple RC models of CMOS transistors, gates, and
wires can provide reasonable insight into the power and delay of circuits
• A methodological approach enables creating static CMOS gates relatively straightforward
• Although global wire delay is getting worse relative to gate delay, local wire delay is scaling with gate delay which forces designers to better manage global wires early in the design process
Next Lecture: Srini Devadas will be discussing algorithms and issues in
synthesis and place+route