Analog Mixed Signal Design in FinFET Processes

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Before We Start

Moderator Presenter

Aimee Kalnoskas Design World

Eric Naviasky Cadence

Analog Mixed-Signal Design in FinFET Processes

Eric Naviasky, Fellow, Cadence Design Systems, Inc. February 24, 2015

•  I am not o  I want to encourage other designers to embrace FinFETs as fully as I have

•  It is not the 3-D nature of the devices o  Extreme sub-micron is the source of most of the problems o  This is the same for planar devices (FDSOI)

•  The FinFETs offer areas of improvement for the AMS designer as well as new challenges

Why am I picking on FinFETs?

The benefits Why you should look forward to designing in FinFET processes

Beautiful MOS device characteristics

FinFet

FinFet

FinFet

40nm

40nm

40nm

Vds Vds Vgs

Id Id

LogId

Sub  threshold  slope  is  close  to  ideal

gbs  or  Body  effect  is  much  smaller

gds is  much  lower

ΔVbs

The benefits Part 2 - Why look forward to designing in FinFET processes?

40nm

FinFet

Ron

V  channel

•  Gm is high •  Devices have high Ft-> lots of Gm and very small gate

capacitance •  Device parasitic capacitances are small •  The lithography is very good •  A nice selection of Vt0 - T gates work again!

The benefits Part 3 - Why look forward to designing in FinFet processes?

•  Digital is almost free o  Programmable values for analog components are easy to implement and can

reduce the difficulty of meeting varying system requirements and handling corners o  Auto-calibration and adaptive loops are your new best friend o  Much higher levels of adaptive cleverness are easily possible – yesterday’s auto zero

has been replaced by today’s convolutions and DFTs. More effects can be corrected.

•  Current density o  High Idsat Type equation here. and skinny thin metal => the metal that hooks up a

minimum-sized device cannot carry the drain current it can produce o  Current limit may correspond to as little as Id (VT0 + 150mV) > Max Ft

•  Matching o  Tiny devices with small Avt still have poor absolute matching o  In 3-sigma land, 1 minimum-sized device Ids > 2 minimum-sized devices Ids

•  Metal resistance o  Metal is thin, narrow and resistive. 400mOhms/ o  Thicker metals at the top of the stack are reserved for the power distribution

The challenges The obstacles associated with designing in FinFET processes

•  Unit-sized devices o  Fins come in one W o  L is heavily restricted (sometimes to one size) o  gds doesn’t change linearly with L. Bias blocks and high-gain single stages are hard. o  Sizing for noise (bigger, longer devices have lower 1⁄𝑓 noise) is not practical.

Broadband noise is reduced by more current, 1⁄𝑓 noise goes down only √𝑁 as you parallel devices and raise current to maintain density.

•  Complex and slow device models o  The device models are more complex (3-5X BSIMX) and run slower in the simulator

The attractively challenged

•  The parasitic capacitances dominate the design o  Schematic sims without good capacitance estimates mean very little – only

extracted RC sims count o  This causes many more cycles through design and layout

•  Layout is very painful because of the density and regularity rules o  All devices are on a grid o  Do not mix different sizes, types, components, etc., without a buffer zone o  Density is critical. De-cap must have the same poly density as your circuit. o  Resistors come in few or one size and have an effective voltage limit per segment

for reliability

The attractively challenged (part 2)

•  Bias block design - DC precision amplifier for bandgap or V to I converter o  In the old days, you might use a 1um X 1um device for input stage or mirrors to get a low gds and low noise

o  In FinFET, this would look like an array of approximately 60 X 16 minimum-sized devices for each transistor (~1000 devices)

o  Stacking is not the same as longer L. output impedance and noise performance will not be the same.

•  Metal line resistance / current handling o  Lower layer min metal line = ~10 Ohms per um o  Maximum average current <100uA

•  W/L of smallest efficient device (no wasted space) o  Approximately 50

Interesting calculations

Potentially less dense Some analog devices may exhibit lower density

40nm  single  4um X  1um  FET

Equivalent  device  in advanced  FinFET  process

•  Matching: use stacks of devices o  OK for low-frequency applications o  Matching is not as good on long devices o  Output conductance is as good or better o  Frequency response is worse

•  Digital correction is the best solution •  Electro-migration current limitation

o  Use dynamic circuits. The RMS current limit is much higher than the average.

Design solutions architecture selection

•  The device model is more complex => the sim runs slower •  Brute force

o  Buy bigger servers, use simulators that take advantage of many processors (such as APS) o  This requires very small learning curve and has minimal risk of missing something

•  Finesse o  Adopt a two-part simulation protocol with transistor-level simulation as complex as you can get

to in a reasonable amount of time (1 hour), and above that use behavioral models o  This requires that you become proficient with behavioral modeling and that you understand the

design well enough to know what has to be modeled and what is “close enough” o  This can save a lot of time or produce a spectacular disaster – use carefully

•  Always estimate parasitic C (and sometimes R) in schematic simulations. They will make a large difference and “zero” is not a reasonable guess.

Challenge: slow simulations

•  Develop a template based approach •  Each layout element should have the same density of

critical layers. This is to protect the blocks nearby, not to protect this block.

•  Group all devices of a type in a single area and accept the higher interconnect distance. The line lengths will not get shorter if you try to mix things due to buffer zones.

•  Floorplan very early to help with estimating parasitic R&C

Challenge: layout

Template-based layout •  All devices are laid out with a fixed dimension and fixed density of critical layers •  In some processes the critical layers are fixed patterns with deviations from the

fixed pattern only with cut layers

A few examples

•  Overview o  Provides additional process information not available from fab o  November 2013 test chip tapeout o  3 wafer probe sites o  Focus on process and analog ESD

16FF test structures chip

Test  Structure Test  Goal DCO Risk  reduction  for  PLL

ESD  Clamp  and  I/O  network  

ESD  configuration  testing

Current  DAC   MOS  matching  and  proximity  effects

Ring  Oscillator with/without  extra  routing  parasitics  

Simple  amp   Gain  and  mismatch  parasitics  

R  matching  Array   Proximity  effects  on  R  matching

USB3.0 PHY #1 Tablet application

USB3.0 PHY #2 Smartphone application

FinFET multiprotocol PHY

•  16Gbps  PCIe®  4.0,  10GKr,  and  many  other  standards  down  to  1.25G •  Less  than  10mW/Gbps •  Rx  –  5  tap  DFE  and  powerful  CTLE  handle  loss  to  30dB •  Tx  –  3  tap  FFE •  Dual-­‐‑path  RX  for  improved  JTOL

DDR 16FF test chip DDR4/DDR3/DDR3L

FinFET conclusions •  Analog behavior of the transistors is very nice •  Matching and current density limits are problematic •  Digital control is cheap - time to start using it •  Layout is hard - shift to templates •  Very good performance has been demonstrated in these

processes

Jump in, the water is fine.

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Questions? Aimee Kalnoskas Design World akalnoskas@wtwhmedia.com

Eric Naviasky Cadence enav@cadence.com

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