Si-Based Transistor and Analog-Mixed- Signal Circuit ...
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Si-Based Transistor and Analog-Mixed- Si-Based Transistor and Analog-Mixed- Signal Circuit Scaling and the Natural Signal Circuit Scaling and the Natural Progression of Moore's Law to Si Quantum Progression of Moore's Law to Si Quantum Computing at the Atomic Scale Computing at the Atomic Scale Sorin Voinigescu University of Toronto Aarhus University, August 14, 2017
Transcript of Si-Based Transistor and Analog-Mixed- Signal Circuit ...
Si-Based Transistor and Analog-Mixed-Si-Based Transistor and Analog-Mixed-Signal Circuit Scaling and the NaturalSignal Circuit Scaling and the Natural
Progression of Moore's Law to Si QuantumProgression of Moore's Law to Si QuantumComputing at the Atomic ScaleComputing at the Atomic Scale
Sorin VoinigescuUniversity of Toronto
Aarhus University, August 14, 2017
Growth in High Tech Sector
● Ubiquitous access
– Social media and augmented reality
– Entertainment (streaming media, VR and gaming)
● Control and coordination (Artificial Intelligence + IoT)
– Data mining
– Machine learning
– Autonomous navigation
– Ambient sensing2
What makes it possible?
● Higher data rate communications systems
– wireless and fibre-optics links
● Compute and storage capacity
● Sensors
But
– Moore's law is coming to an end...
– Ever increasing energy consumption....
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Agenda
● State-of-the-art Si technology performanceState-of-the-art Si technology performance
● Si transistor HF performance scaling
● CMOS-based coupled quantum dot qubits
● Benchmark circuit scaling
● Conclusions
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Applications
● mm-wave 5G @ 28 – 72 GHz => fT/f
MAX > 3f
0 = 215 GHz
● Automotive radar @ 76 – 81 GHz => fT/fMAX > 3f0 = 245 GHz
● 56-112 GBaud fiberoptic systems => fT/fMAX > 4fB = 225-450 GHz
All need thick dielectric/thick metal backend
All need very low phase noise
All need large output swing > 4Vpp differential
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State of the Art Si Technology
Agenda
● State-of-the-art Si technology performance
● Si transistor HF performance scalingSi transistor HF performance scaling
● CMOS-based coupled quantum dot qubits
● Benchmark mm-wave AMS circuit scaling
● Conclusions
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Higher fT,
higher fMAX
,
lower NFMIN
,
still the only efficient way to save power and improve
performance SIMULTANEOUSLY
Goldilocks Scaling
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Atomistix Si FET Scaling Simulation
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Interesting things
happen to bulk materials
in atomic-scale devices
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Bandgap in thin [100] Si nanowire
Atomistix simulationsJ. Bateman, MASc Thesis 2014
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Bandgap in Si nanowire as a function ofchannel direction
Atomistix simulationsH. Farooq, MASc Thesis 2015
Direct bandgap along [100] and [110]directions!
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Atomistix: Short Channel Effects
• Ballistic transport (Ion
does not depend on L)
• Subthreshold Slope degradation at low L
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Ideal DG(FinFET) Scaling
[S. Voinigescu et al, IEEE Proc. 2017]
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gm Scaling: FDSOI vs. FiNFET
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fT Scaling: SiGe HBT vs. FiNFET
fT/f
MAX= 500/700 GHz
[IHP IEDM 2016]
[M. Schroter et al, IEEE Proc. 2017]
[S. Voinigescu et al, IEEE Proc. 2017]
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1nm MoS2 SWCNT FET
Desai et al., Science Oct. 2016
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On CMOS Scaling
• Atomistix shows Si MOSFET scalable to 2 nm
CMOS HF performance scaling uncertain due to
– Ballistic transport
– Bandgap increase
– Surface scattering
• BEOL kills intrinsic MOSFET performance
• HF circuit performance scaling already peaked at 28nm-40nm
Agenda
● State-of-the-art Si technology performance
● Si transistor HF performance scaling
● CMOS-based coupled quantum dot qubitsCMOS-based coupled quantum dot qubits
● Benchmark mm-wave AMS circuit scaling
● Conclusions
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Coupled Quantum Dot Qubit
● 22nm, 12nm, 5nm FDSOI CMOS● Quantum dot (QD) under each top gate● Individual gate control of each QD● Potential barrier between dots● Back gate for entanglement (tunnel barrier) control
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Principle of operation
Information encoded in particle spin
Basis states
|↑> = |0>; |↓> = |1>
Superposition states
|Ψ> = a|↑> + b|↓>
a and b are complex numbers● a = cos(θ/2)● b = eiφsin(θ/2)● |a|2 + |b|2 =1● Only two real variables: φ, θ
Bloch sphere|↑>
|↓>
θ
φ
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Qubit Gate Operations
● Spin Rotations ● Apply a μwave/mm-wave
voltage oscillation of fR for
pulse duration τS on QD gate
● Spin Swap● Apply a pulsed inter-dot
voltage (across the barrier)
Bloch sphere
|↑>
|↓>
θ
φ
H s(t )=J (t ) S⃗ L⋅S⃗ R
θ=2π f R τS
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E-level splitting due to well coupling
Rabi frequency
[S. Voinigescu, IJE, February 1989]
f R=Δ E=1meV2πℏ
=241.47GHz
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E-level splitting due to DC magnetic field
Zeeman effect
Em=57.87μ eV⋅m⋅B [T ]
f m=13.96GHz⋅m⋅B [T ]
m = 1,2...
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Quantum Computing with Qubits
● N qubits = 2N complex amplitudes● Analog (microwave & mm-wave)
signals for spin manipulation andreadout
● Electron spin + electron energy● ΔE <0.1 meV => T< 0.1 K● Problems:
● Thermal noise ~kT● mm-wave frequency signals● Atomic scale fabrication
precision
Bloch sphere
|↑>
|↓>
θ
φ
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Coupled QD Qubit Gate in 22nm FDSOI
● Multi-gate MOSFET structure = Series-stacked FDSOI cascode● Also similar to charge coupled devices● Both hole spin and electron spin qubit on same die
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Coupled Quantum Dot Qubit
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5 Coupled QD electron-spin Qubit
Similar to series-stacked
SOI cascode PAs and
antenna switches!
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22nm FDSOI Qubit mm-Wave TestStructures
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Qubit Spin Readout Circuit
IDS
= 20-40 μA, Cgd
, Cgs
= 20-80 aF, low gain, >100 GHz BW. Very difficult to measure!
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TIA Readout Circuit
● Small size input stage needed● noise figure, gain and bandwidth are important design considerations
<WSA-2> 32
On CMOS Qubits
Quantum computing is NOT digital
Need energy deltas > 1 meV for > 10 K operation
Need sub-5nm dimensions in all directions
Need fR > 200 GHz and/or B > 10 T
Si QC needs low-noise mm-wave circuits and low-T operation
Si QC must be compatible with CMOS at 4 K or higher
Needs skilled mm-wave IC designers and measurements
Agenda
● State-of-the-art Si technology performance
● Si transistor HF performance scaling
● CMOS-based coupled quantum dot qubits
● Benchmark mm-wave AMS circuit scalingBenchmark mm-wave AMS circuit scaling
● Conclusions
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AMS Benchmark Circuits
● Tuned
– LNA
– PA
– VCO
● Broadband
– TIA
– THA
– Linear Large-Swing Driver
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Stacked CMOS inverter: 28nmFDSOI vs. 45nm PDSOI
S.Shopov et al., IEEE JSSC, July 2016
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140GHz CS n-MOSFET PAE, Pout
28nm FDSOI vs. 45nm PDSOI
S.P. Voinigescu et al., IEEE Proc. 2017
SiGe HBT Scaling: NFMIN
, MAG
[M. Schroeter et al. IEEE Proc. 2017]
SiGe HBT 220GHz PA in Node 5
[M. Schroeter et al. IEEE Proc. June 2017]
SiGe HBT PA & VCO Scaling
[M. Schroeter et al. IEEE Proc. June 2017]
• Pout = 7.2 dBm at 240 GHz
• PN10 MHz = -104 dBc/Hz
• PDC = 386 mW (w/o divider)
• PDC = 566 mW (w/ divider)
• DC-to-RF eff iciency is 1.3%
Funding by Robert Bosch GmbH
[S. Shopov, CSICS 2015, JSSC Oct. 2016]
240GHz Synthesizer
220-270GHz Doubler Design
Measurement Results Across Dies
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Time-Interleaved 200GS/s Receiver
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CMOS TIA
[S. Shopov et al., JSSC July 2016]
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CMOS TIA: 28nm FDSOI vs. 45nm PDSOI
[S. Shopov et al., JSSC July 2016]
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92GHz Linear TIA
[K. Vasilokopoulos et al. BCTM 2015]
Gain: 13 dB
BW3dB: 92 GHz
NF < = 6 dB to 88GHz
Group delay: 6 ±1.5 ps
Vcc: 2.3 V
Power: 48 mW
400 fJ/bit
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S-params and Noise Figure
Record low-noise
in Si: NF <= 6dB
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Linearity and Eye Diagrams
120Gbps output
96Gbps output
P1dB
: -9 dBm
Equivalent to 4 mApp
Up to 120 Gb/s (PRBS-31)
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TIA Scaling
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108-GS/s Quasi-CML THA
55-nm SiGe BiCMOS
[K. Vasilakopoulos et al., IMS 2016]
Vcc: 2.5 V & 1.8V
Power: 87 mW
BW3dB: 40 GHz
Up to 108 GS/s
THD: -49dB @ 90 GS/s
IIP3: 8dBm @ 90 GS/s
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THA Waveform Measurements
8 GHz @ 40GS/s 12 GHz @ 60GS/s
18 GHz @ 90GS/s 12 GHz @ 108GS/s
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THA Scaling
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4x62GHz 25% Duty-Cycle PhaseGenerator
N.Weiss, IEEE CSICS 2017
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4x54GHz 25% duty-cycle phase generator
160GS/s ADC Front End in 22nm FDSOI
●
160GS/s ADC Front End in 22nm FDSOI
●
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● MOSFETs theoretically scalable to 2-3 nm gate length
● fMAX
, NFMIN
, PAE, saturate/degrade in sub 28-nm CMOS
● Unlike CMOS, HBT mm-wave performance STILL scales
● Double-gate MOSFET qubit at >10 K at 5nm and below
● THz spin manipulation and readout circuits needed
• 200Gb/s radio feasible at 240 GHz
• 250GHz bandwidth TIA with < 4dB noise figure
• 400GS/s ADCs and DACs feasible
Conclusions
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• Graduate students:
– Stefan Shopov, James Bateman, Hassan Farooq,
James Hoffman, Kostas Vasilakopoulos, Robert Baker,
Sadegh Dadash, Naftali Weiss, Shai Bonen, Utku
Alakusu, Alireza Zandieh
• STMicroelectronics, Global Foundries, CMC
• NSERC, DARPA, Ciena, Robert Bosch GmbH, Finisar
Acknowledgments
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Quadrature 62GHz Outputs
Linear 120GBaud 5Vpp DA
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120Gb/s, 4.8Vpp
NRZ Eye Diagrams [R. Baker et al. IMS 2017]
