A BuiltA Built--In SelfIn Self--Test Approach for Test Approach for Analog Circuits in MixedAnalog Circuits in Mixed--Signal Signal

Systems Systems

Chuck StroudChuck StroudDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering

Auburn UniversityAuburn University

Outline of PresentationOutline of Presentation•• Need for Test & Overview of BISTNeed for Test & Overview of BIST•• MixedMixed--Signal BIST ArchitectureSignal BIST Architecture

Test Pattern GeneratorTest Pattern GeneratorOutput Response AnalyzerOutput Response Analyzer

•• Fault Detection with BISTFault Detection with BIST•• Experimental ResultsExperimental Results

Fault SimulationFault SimulationHardware PrototypeHardware Prototype

•• Parameterized VHDL ModelParameterized VHDL Model•• Summary & ConclusionsSummary & Conclusions•• DemonstrationDemonstration

The Need for TestThe Need for Test2000 International Technology Roadmap for 2000 International Technology Roadmap for

SemiconductorsSemiconductors (by the Semiconductor Industry (by the Semiconductor Industry Association Association -- SEMATECHSEMATECH) predicts by 2014:) predicts by 2014:

•• Test machines will cost Test machines will cost more than $20M each!!!more than $20M each!!!•• It will cost It will cost moremore to test a transistor than to to test a transistor than to

manufacture it!!!manufacture it!!!•• BuiltBuilt--In SelfIn Self--Test (BIST) is the most likely solutionTest (BIST) is the most likely solution

Analog BIST is needed for mixedAnalog BIST is needed for mixed--signal systemssignal systemsFault diagnosis is needed with BISTFault diagnosis is needed with BISTMethods are needed for automatic Methods are needed for automatic implementation of BISTimplementation of BIST

Analog Circuit BehaviorAnalog Circuit BehaviorFrequency response using nominal component valuesFrequency response using nominal component values

GainGainPhasePhase

Analog Circuit BehaviorAnalog Circuit BehaviorFrequency response using component variationsFrequency response using component variations

GainGainPhasePhase

What is BuiltWhat is Built--In SelfIn Self--Test?Test?•• Basic idea:Basic idea: Add circuitry to integrated circuit (chip) Add circuitry to integrated circuit (chip)

or printed circuit board to make it test itselfor printed circuit board to make it test itselfOnly power and clock needed during BIST sequenceOnly power and clock needed during BIST sequencePass/Fail result reported at end of BIST sequencePass/Fail result reported at end of BIST sequence

No need for external test equipmentNo need for external test equipment

•• Necessary components:Necessary components:Test Pattern Generator (TPG)Test Pattern Generator (TPG)Output Response Analyzer (ORA)Output Response Analyzer (ORA)For system level use:For system level use:

Test controllerTest controllerInput isolationInput isolation

•• Penalties:Penalties: area overhead, performancearea overhead, performance•• Benefits:Benefits: low testing time & costlow testing time & cost

TPGTPG

ORAORA

CircuitCircuitUnderUnderTestTest

TestTestControlControl

MUXMUX

SystemSystemInputsInputs

SystemSystemOutputsOutputsPass/FailPass/Fail

BIST BIST StartStart

AnalogAnalogSystemSystemInputsInputs

ADCADC AnalogAnalogCktryCktry

SystemSystemFunctionFunction

DigitalDigitalSystemSystemOutputsOutputs

AnalogAnalogSystemSystemOutputsOutputs

SystemSystemFunctionFunction

DigitalDigitalSystemSystemInputsInputs

Digital CircuitryDigital Circuitry

DACDAC

Analog CircuitryAnalog Circuitry

AnalogAnalogCktryCktry

MixedMixed--Signal BIST Architecture Signal BIST Architecture

BISTBISTCompleteComplete

TPGTPG

ORAORA

TestTestControlControl

BISTBISTStartStart

BISTBISTResultsResults

MuxMux

101011000111011010101011000111011010

101011000111011010101011000111011010

AnalogAnalogLoopLoop--backback

SystemSystem--Level Use of BIST Level Use of BIST

ADCADC

DACDAC AnalogAnalogCktryCktryTPGTPG

ORAORA

AnalogAnalogCktryCktry

AnalogAnalogCktryCktry

AnalogAnalogCktryCktry

•• Multiple BIST sequences w/ analog Multiple BIST sequences w/ analog loopbackloopback MUXMUXPass/fail results indicate location of faulty analog circuitryPass/fail results indicate location of faulty analog circuitry

•• Location & number of analog Location & number of analog loopbackloopback MUXsMUXsDetermine analog diagnostic resolution & fault coverageDetermine analog diagnostic resolution & fault coverageCan tradeCan trade--off diagnostic resolution and fault coverage with off diagnostic resolution and fault coverage with analog area overhead & performance penaltiesanalog area overhead & performance penalties

Test Pattern GenerationTest Pattern GenerationTPG generates 16 test waveforms:TPG generates 16 test waveforms:•• counter (up, down, & up/down)counter (up, down, & up/down)

ramp, ramp, sawtoothsawtooth & triangle waveforms& triangle waveforms•• LFSR (pseudoLFSR (pseudo--random patterns)random patterns)

noisenoise--like waveformslike waveforms•• magnitude registermagnitude register

programmable amplitude DC testprogrammable amplitude DC testimpulse & step responsesimpulse & step responses

•• frequency sweepfrequency sweepvarying & constant amplitudes varying & constant amplitudes

•• bit reversal (for most waveforms)bit reversal (for most waveforms)noise & random frequencies/amplitudesnoise & random frequencies/amplitudes

Counter/LFSRCounter/LFSR

Bit ReversalBit ReversalMUXMUX

Count ValueCount ValueHolding Holding RegReg

MagMag RegReg

Output DataOutput DataMUXMUX

SystemSystemDataData

To DACTo DAC

Frequency SweepFrequency SweepVarying AmplitudeVarying Amplitude

PseudoPseudo--RandomRandomPatternsPatterns

Frequency SweepFrequency SweepVarying AmplitudeVarying Amplitude

Bit ReversalBit Reversal

Triangular WaveTriangular Wave& Bit Reversal& Bit Reversal

Sample Test WaveformsSample Test Waveforms

Time

0s 1.0s 2.0s 3.0s 4.0s 5.0s 6.0s 7.0s 8.0sV(1)

0V

2.0V

4.0V

5.0V

Time

0s 0.5s 1.0s 1.5s 2.0s 2.5s 3.0s 3.5s 4.0s 4.5sV(2)

0V

2.0V

4.0V

6.0V

Time

0s 100ms 200ms 300ms 400ms 500msV(1) V(2)

0V

2.5V

5.0V

Time

0s 40ms 80ms 120ms 160ms 200ms 240msV(2)

0V

2.5V

5.0V

Actual Waveforms from Demo UnitActual Waveforms from Demo UnitVarying amplitude frequency sweepVarying amplitude frequency sweepobserved at DAC outputobserved at DAC output

Triangle wave observed at DAC outputTriangle wave observed at DAC output

Step function observed at DAC outputStep function observed at DAC output SawSaw--tooth observed at DAC outputtooth observed at DAC output

Output Response AnalyzerOutput Response AnalyzerORA is a double precision accumulator:ORA is a double precision accumulator:•• Allows range of values to determine Allows range of values to determine

pass/fail statuspass/fail statuscomponent tolerancescomponent tolerancesprocessing variationprocessing variationtemperature & voltage variationtemperature & voltage variationDAC/ADC noiseDAC/ADC noise

•• Modes of operation:Modes of operation:digital test of BIST circuitrydigital test of BIST circuitryanalog magnitude testanalog magnitude test

sums ADC output magnitudessums ADC output magnitudesanalog difference testanalog difference test

sums |TPG input sums |TPG input -- ADC output|ADC output|

Absolute ValueAbsolute ValueSubtractorSubtractor

MUXMUX

Double PrecisionDouble PrecisionAccumulatorAccumulator

BIST ResultsBIST Results

From ADCFrom ADCFrom TPGFrom TPG

Absolute Value DifferenceAbsolute Value Difference

•• Detects faults causing:Detects faults causing:NoiseNoisePhase shiftPhase shiftOvershoot/ringingOvershoot/ringing

Input step function

Output response

Correct signatureFault detection signature

Analog Fault Detection with BISTAnalog Fault Detection with BIST

•• Acceptable variation distributionsAcceptable variation distributionsObservation:Observation: all variations produce normal all variations produce normal distribution of signaturesdistribution of signatures

•• Detected vs. undetected faultsDetected vs. undetected faults•• Potentially detected faultsPotentially detected faults

PPdetectdetect = #detects/#simulations= #detects/#simulations

•• Fault Coverage = (#detect + Fault Coverage = (#detect + ΣΣPPdetectdetect)/#faults)/#faults

00 22NNgood good cktckt bad bad cktcktbad bad cktckt

PPdetectdetect

Fault Simulator ResultsFault Simulator ResultsOpAmp1, Sum Vout, 250 runs, 2/16/02,

-0.1 to 0.1 V sawtooth input, 250-µs period

0

20

40

60

80

100

120

0 1000 2000 3000 4000 5000 6000

BIST Accumulator Sum

Cou

nts

No Faults All Faults

Faults: MOS source-drains, resistor, and capacitor opens and shorts.

Process variations:resistor and capacitor (MOS process variations planned).

BIST Results with Benchmark CircuitsBIST Results with Benchmark CircuitsBenchmark

Circuit #

Comps # Op Amps

Hard Faults

Soft Faults

Fault Coverage

Op Amp 1 11 - 22 6 98.6%CTSV Filter 9 3 84 36 97.8%Op Amp 2 10 - 20 2 100%

Leapfrog filter 17 6 154 46 100%Differential amp 9 - 34 18 95.0%

Comparator 3 1 26 8 95.4%Single stage amp 6 - 16 12 100%Elliptical filter 22 3 90 62 100%Low-pass filter 4 1 30 14 100%

General trends:General trends:•• Frequency sweep waveforms perform best for filtersFrequency sweep waveforms perform best for filters•• Count/LFSR test waveforms perform best for amplifiersCount/LFSR test waveforms perform best for amplifiers

Noise & Phase Shift DetectionNoise & Phase Shift DetectionNoise and Phase Shift Detection with Difference Summing ModeNoise and Phase Shift Detection with Difference Summing Mode

Amplitude of noise as a % of the amplitude of the input signal

Diff Summing FCMag Summing FC

45%Faul

tC

ove

rage

100

80

60

40

20

0

Phase shift as a % of the input waveform period

1 2 3 4 5 86 7 9

20%

Diff Summing FCMag Summing FC

Fau

ltC

ove

r ag e

100

80

60

40

20

00.5 1 2 4 5

Actual Benchmark Circuit ResultsActual Benchmark Circuit ResultsGood low pass filter w/count-up

Faulty low pass filter w/count-up

DAC output test waveformDAC output test waveform

Faulty lowFaulty low--pass output responsepass output response

DAC output test waveformDAC output test waveform

Good lowGood low--pass output responsepass output response

Resultant good circuitResultant good circuitsignature distribution in ORAsignature distribution in ORA

Resultant faulty circuitResultant faulty circuitsignature distribution in ORAsignature distribution in ORA

Fault is always detectedFault is always detected

Parameterized VHDL ModelsParameterized VHDL Models•• Automated synthesis in any design Automated synthesis in any design •• Parameterized VHDL includes:Parameterized VHDL includes:

TPGTPGSupports DAC sizes: 4 to 24Supports DAC sizes: 4 to 24--bitsbits

ORAORASupports ADC sizes: 4 to 24Supports ADC sizes: 4 to 24--bitsbitsUser specified accumulator sizeUser specified accumulator size

Reduces aliasing probabilityReduces aliasing probability

Test controllerTest controllerUser programmable initialization & User programmable initialization & BIST sequence lengthsBIST sequence lengths

Choice of processor interfacesChoice of processor interfacesCustom, serial, parallelCustom, serial, parallelIEEE 1149 Boundary ScanIEEE 1149 Boundary Scan

TestTestControlControl

Processor InterfaceProcessor Interface

TPGTPG

ORAORA

Demonstration Unit 1997Demonstration Unit 1997•• Original demo unitOriginal demo unit

3 analog benchmark circuits in discrete parts3 analog benchmark circuits in discrete partsDAC, DAC, OpAmpOpAmp, & Low Pass Filter, & Low Pass Filter

Test Pattern Generator 1997Test Pattern Generator 1997

Demonstration Unit 2002Demonstration Unit 2002•• PC control & displayPC control & display•• Benchmark circuit PCBBenchmark circuit PCB

low/high/bandlow/high/band--pass filterpass filterwith physical fault injectionwith physical fault injection

•• DACDAC--ADC PCBADC PCBwith analog with analog loopbackloopback

•• MixedMixed--signal BIST PCBsignal BIST PCBwith MOSIS TinyChipswith MOSIS TinyChips

•• CPLDCPLD--based BIST PCBbased BIST PCBfor synthesis of VHDLfor synthesis of VHDLparameterized 4 to 12 bitsparameterized 4 to 12 bits

ORAORATPGTPG

BIST Implementation 2002BIST Implementation 2002Test Pattern GeneratorTest Pattern Generator Output Response AnalyzerOutput Response Analyzer

•• Includes test controllerIncludes test controller

Parameterized VHDL Generics Parameterized VHDL Generics

# inputs to DAC# inputs to DAC4 4 ≤≤ NNDAC DAC ≤≤ 2424NNDACDAC

# analog # analog loopbackloopback control bitscontrol bitsNNLPBKLPBK ≤≤ NNACUMACUM -- 22NNLPBKLPBK

# bits in BIST counter# bits in BIST counterNNBCNTBCNT

# bits in initialization counter# bits in initialization counterNNICNT ICNT + N+ NBCNTBCNT≤≤ NNACUMACUM

NNICNTICNT

# bits in freq. sweep shift reg.# bits in freq. sweep shift reg.NNPSR PSR ≥≥ 11NNPSRPSR

# bits in 1/2 of# bits in 1/2 ofdoubledouble--precision accumulatorprecision accumulator

NNACUM ACUM ≥≥ maxmax(N(NADC, ADC, NNDACDAC))

NNACUMACUM

# outputs from ADC# outputs from ADC4 4 ≤≤ NNADC ADC ≤≤ 2424NNADCADC

Bits controlled by genericsBits controlled by genericsRangeRangeGenericGeneric

shift registershift register

addressaddressdecodedecode

readreadMUXMUX

Processor InterfacesProcessor Interfaces•• Custom InterfaceCustom Interface

incorporation with system specific incorporation with system specific interfacesinterfacesall data busses & write enables all data busses & write enables accessibleaccessible

•• Parallel InterfaceParallel Interfaceaddress decoder & read multiplexeraddress decoder & read multiplexerwith & without synchronizationwith & without synchronization

•• Serial InterfaceSerial Interfaceserial shift registerserial shift registerwith & without synchronizationwith & without synchronization

•• Boundary ScanBoundary Scaninterface to IEEE 1149 standardinterface to IEEE 1149 standard

TPGTPG ORAORATestTestControlControl

TDI TDO

Capture/update

sync

sync

syncsync

VHDL Synthesis ResultsVHDL Synthesis Results

108.7108.71298129891.891.85996365996361147114788888885.785.71773177364648093288093281534153412121212121284.984.917161716646480176680176615061506121244121288.988.91441144162.662.6690625690625127612761212448886.886.813051305646462468062468011591159121212124489.289.21227122762.662.6581594581594110011001212884494941157115761.361.35549615549611044104412124444

Freq.Freq.(MHz)(MHz)

##gatesgates

Freq.Freq.(MHz)(MHz)

AreaArea((µµmm22))

##gatesgates

NNACUMACUMNNADCADCNNDACDAC

Speed optimizeSpeed optimizeArea optimizeArea optimize

•• AMI 0.5AMI 0.5µµm CMOS standard cell synthesis results:m CMOS standard cell synthesis results:745 745 µµm to 900 m to 900 µµm on a sidem on a side60 MHz to 109 MHz operation60 MHz to 109 MHz operation

VHDL Synthesis VHDL Synthesis •• Used Mentor GraphicsUsed Mentor Graphics

serial processor interfaceserial processor interface4, 8, and 124, 8, and 12--bit versionsbit versions

•• Synthesized & verifiedSynthesized & verifiedvia simulation in:via simulation in:

1.51.5µµm AMI CMOSm AMI CMOS0.50.5µµm AMI CMOSm AMI CMOS

in actual hardware in:in actual hardware in:Cypress 39K CPLDsCypress 39K CPLDs

Using WARPUsing WARPXilinx Xilinx VirtexVirtex FPGAsFPGAs

Using ISEUsing ISE

VHDL SynthesisVHDL SynthesisSynthesis in Spartan 2s50 FPGASynthesis in Spartan 2s50 FPGA

with room to sparewith room to spare

Project TPG ArchitectureProject TPG Architecture

W Ad Data8

8 8

ADEC8Dat

Mag Cont

PDIPSL

PEPDO

PISR

Mag Cont

88WEs

2

Mag Cont

LFSR/counterdin cocont

8

CVAL

4

BISTFS

1 0

8

BITR

CO

8LCNT

LCNT

Par Register8

CVAL

ShiftReg

TFF

OTOG

ld

TCO

3

FS BIST

2

PSR

CVAL

ODAT

8Cval

8

Mag

8SDAT

8TOUT

OTOGFSDSEL

5

FFs

TCOlogic

BIST

Project ORA ArchitectureProject ORA Architecture

W Ad Data8

88 8 8 8

4

2ADEC

8Dat

Bis

t

Bcn

tA

chi

Acl

o

WEs

PDIPSL

PEPDO

PISR8

SubAbs

TDAT ADAT

88co

8

REG2

5

Dat

WE3

DSEL

ACLO coen ACHIen

8

2

OFS

Aclo8

Achi

ACUM

8

DatWE0

8

DatWE1

ICNT coen

4Icnt

4DatWE2

BCNTcoen

4Bcnt

4DatWE2

BIST

Bist

Dat

WE

3

Idone

Idone

Dat

WE3

Done

DONE

Dat

WE3

CONT

Ben

Sdat

Icnt

2

TC

O

TC

O

3

LPBK

Idon

eD

ON

EO

FSL

PBK

Summary & ConclusionsSummary & Conclusions

•• Most of BIST circuitry in digital domainMost of BIST circuitry in digital domainminimizes impact on analog circuitryminimizes impact on analog circuitry

•• TPG produces 16 test waveformsTPG produces 16 test waveformshigh fault coverage in wide variety of analog high fault coverage in wide variety of analog cktsckts

•• ORA has multiple summing modesORA has multiple summing modesaccumulator allows range of acceptable valuesaccumulator allows range of acceptable valuesabsolute value difference detects noise/phase shiftsabsolute value difference detects noise/phase shifts

•• Parameterized VHDL for use in any designParameterized VHDL for use in any designimplemented & verified in hardwareimplemented & verified in hardware