A new FEEB & ROCB Design issues for the next stage DAQ Chain for MUCH

Madhusudan DeyVECC,KOLKATA

CBM collaboration meet at VECC 30th July – 1st August, 2010

DET FEEB

ROC

DCB

ABB

ABB

BNeT

FLES

Legacy DAQ Chain

FEEB ROC: Readout Controller Board

 

AnnexBuilding

MainComputing

Building

60 meter

300 meter

Optical Link

Optical Link

Dipole magnet, Silicon Tracking Stations and Muon detection

system Requirements for GEM PCBS:

Station:1135 ×135 sq mm for 281 Modules cater·        287,500 Readout Channels FEEBa2! Size of the Board Important!Station:2 +Station:3 ·

      326.2×326.2 sq mm for 228 Modules Caters 232,500 Readout Channels

FEEBa4! Size of the Board Important!

SIS-100 geometry

Data Combiner:Data Reduction FPGA Brd.TX/RX

(left) modular type arrangement and (right) slat type arrangement of modules

Sector type layout of the stations

The options, other than the module-type will need GEM foils of non-standard sizes and we need to find suitable vendor for doing this. We have however kept the options open so that we can take a final call at suitable time.

Detector PCB

Communication HUB

• A radiation tolerant ASIC HUB Chip for data aggregation & communication , capable of aggregating data from several Front end Asics (FEEB) onto a single output link

• Data from 2, 4 or 8 CBM-XYTER chips (FEBa2, FEBa4 and FEBa8, respectively) can be aggregated to fill a 2.5 Gbps link based on a 2.5 Gbps SERDES circuit.

• The ‘Hub Asic’ must also be able to handle clock distribution, sync and slow control traffic and operate with a deterministic latency at the Word clock level.

 • Convert the input data from FEEB into a serial stream (Cu or

Optical?)

• De-serialize the frame transmitted from the computing building and feed the data to the FEEB.

…………………………….

ASIC ASIC

ASIC ASIC

Each ASIC supports 128 channels..

Pads

PCB Board with

Optical HUB

MUX

PCB front view

PCB back view

Many such FEE PCBs & HUBs inside the MUCH

ASIC

ASIC

ASIC

ASIC

MUX

Optical link

ASIC

ASIC

ASIC

ASIC

MUX

ASIC

ASIC

ASIC

ASIC

MUX

ASIC

ASIC

ASIC

ASIC

MUX

FEBa4

ASIC

ASICA

SIC

ASIC

MUX

ASIC

ASICA

SIC

ASIC

ASIC

ASICA

SIC

ASIC

MUX

ASIC

ASICA

SIC

ASIC

ASIC

ASICA

SIC

ASIC

MUX

ASIC

ASICA

SIC

ASIC

ASIC

ASICA

SIC

ASIC

MUX

ASIC

ASICA

SIC

ASIC

FEBa8

VIRTEX 6 FPGA

BOARD

1. Capable of handling 6.6 Gbps Links(12-48)

2. Capable of handling few 11.18 Gbps Links Links (24 nos)

3. Can be implemented data reduction algorithm based on certain predefined fixed criteria

4. Have enough space for other collaborators try their own algorithm

5. Design & fabrication feasible

6. Prototype board developments require 6-9 months

7. Can suggest procedures for board functionality tests

8. Can suggest form factors and nos.

9. Can suggest communication protocol w.r.t HUB

10.At most handle 48 links equivalent to minimum of 48 X256 =12288 CHANNELS new ROCB WITH DATA REDUCTION = 42 nos.

2.5 Gbps from HUB

2.5 Gbps from HUB

VIRTEX 6 FPGA

BOARD

12

CH

OPTICAL

TX/RX

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

VIRTEX 6 FPGA

BOARD

Conceptual

Schema for

ANNEXE Building

24 Links per board possible

ROCB nos reduce to

42 nos for 5.2 lakh

channels

1. 4x4 mm pads ?

2. Hit rate 2.5 MHz per channel

3. FEBa2 ? FEBa4 ? FEBa8 ?

4. Gross data rate?

5. SLAT TYPE ?

6. Form Factor FEEB /LAYOUT /Wiring Details ?

7. HUB Board Design & Fabrication( Who & When?)

8. Multi channel Trans/Receiver 10 Gbps available with 12 channel ?

8 Questions???