Summary DAQ

Summary DAQSummary DAQ

Walter F.J. Müller, GSI, Darmstadt

12th CBM Collaboration Meeting17 October 2008

17 October 2008 12th CBM Collaboration Meeting -- Walter F.J. Müller, GSI 2

This year'sThis year'sbig eventbig event


Config: September Test Beam @ Config: September Test Beam @ GSIGSI

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB1nxGen

BEAMAUX...

ROC EthA

BSYNC-M

AUX

DABC

OnlineAnalysi

sROOT

discr

FEB1nxGen

MAPMT

ROC EthA

BSYNC-S

AUX

FEB1nxGenFEB1nxGen

GEMVECC

Basic BeamDiagnostics

MAPMT Tests

GEM chamberTests

The PlanThe Plan


BeamBeaming into an all new ing into an all new TerritoryTerritory All is new in the setupAll is new in the setup

Detectors FEB (front end board) ROC (read out controller) DAQ Analysis

and the whole paradigm: go self-triggered and time-go self-triggered and time-stampedstamped

Huge effort by many persons to MAKE FEE/DAQ WORKMAKE FEE/DAQ WORK FEB R.Lalik (AGH) and C.Schmidt (GSI) build 3 FEB Rev B

boards ROC N.Abel, S. Müller-Klieser (KIP), and S.Linev (GSI) did all

levels of data handling DAQ-1 R,Karabowicz (GSI) setup n-XYTER test & control DAQ-2 S.Linev, J.Adamcewski, V.Friese (GSI) setup DAQ and

Online Analysis


Config: September Test Beam @ Config: September Test Beam @ GSIGSI

ROC EthA

B

SYNC-M

AUX

FEB1nxGen Rev B

ROLU

ROC EthA

BSYNC-S

AUX

DABC

OnlineAnalysi

sROOT

discr

ROC EthA

BSYNC-S

AUX

GEMVECC

FEB1nxGen Rev B

Si-Strip

Si-Strip

The real thingThe real thing

FEB1nxGen Rev B

SYNC-S

BEAM. discr

NIM toECL toLVDS

GEM chamberTest

STS Test

Basic BeamDiagnostics


STSSTS


STSSTS GEMGEM

SEUSEU

some glue


DAQ Test Beam SummaryDAQ Test Beam Summary

The whole chain workedThe whole chain worked Radek saw the very first spill in the online monitor ! we had only about 7 hours beam over 3 days, and took

data already on day one.

11stst successful proof of concept successful proof of concept everything worked 'in principle'

Good basis to get all the details rightGood basis to get all the details right sure we had some 'surprises' and 'undocumented

features' can all be addressed now based on real experience


Next StepsNext Steps


Next Steps – Three Lines of Next Steps – Three Lines of ActionAction Basic Laboratory Tests

The Starter Kits

FEE/DAQ for first round of Demonstrators proof of concept at module level do by end 2009 (STS) or early 2010 (RPC)

Design of CBM readout chain towards ROB's and FLES interface


The Starter KitsThe Starter Kits


Config: n-XYTER Starter KitConfig: n-XYTER Starter Kit

FEB1nxGen ROC

EthA

BSYNC-M

AUX

OnlineAnalysi

sROOT

No special infrastructure needed, just

ROC + PC

Det

I know: It's overdueI know: It's overdue


Config: TDC Starter KitConfig: TDC Starter Kit

FEET

ROC EthA

BSYNC-M

AUX

OnlineAnalysi

sROOT

No special infrastructure needed, just

ROC + PC

CLKGEN

CLK

25

0

CLK

15

6

Just an adapter:2 ROC user ports 8 FEET ports+ clock inputs

SYNC_TDC andSYNC_250 is

generated in ROC

R2F

A

B

CLK

25

0

A

B

C

D

E

FC

LK1

56

G

H

SYN

C_T

156/250 MHzclock

Det

8 channel:preamplifierdiscriminatortime digitizer

Planned for summer '09


STS STS Demonstrator Demonstrator

00

In-DepthIn-DepthSensor TestSensor Test


ROC EthA

BSYNC-S

AUX

FEB1nxGenFEB1nxGen

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

Config: Test Beam @ IHEPConfig: Test Beam @ IHEP

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB1nxGen

BEAMAUX...

ROC EthA

BSYNC-S

AUX

MIDAS

OnlineAnalysi

s

discr

ROC EthA

BSYNC-S

AUX

FEB1nxGenFEB1nxGen

RFDUT

someauxdets

SYNCmessag

esender

CAMAC DAQ System

SVD-2Beam

Tracker

BeamTelescope

Si StripDemonstrator 0

High precisionbeam tracker(25 μm pitch)from SVD-2experiment

Hybrid DAQSystem:

triggered + time-

stamped

April '09


STS & RPC STS & RPC Demonstrator Demonstrator

11


DAQ over Optics OverviewDAQ over Optics Overview

…

ABBDCB

ROC

ROC

…

ABBDCB

ROC

ROC

…

Use one optical linkone optical link for clockclock distribution timetime synchronization datadata transfer controlscontrols traffic

Specific communication protocol for CBM usage

Guarantee for Deterministic Latency Messages (DLM)

High data bandwidth for data stream ROC => ABB

High reliability for control messages ABB => ROC

Fault detection and fault tolerance

FEB

FEB

FEB

FEB

FEB

FEB

FEB

FEB

DCB: F. Lemke. U. Brüning, ZITI HdABB: Wenxue Gao, A. Kugel, ZITI Hd


Data Combiner BoardData Combiner Board

Programmable core logic Xilinx FPGA - Virtex-4 FX60 Platform ROM ensures low configuration time

High speed serial links 6x SFP connectors DDR2-DRAM (32bit wide, up to 512MByte) FLASH memory (512MBit) Gigabit-Ethernet Transceiver

with RJ45-Connector Programming infrastructure

over JTAG and USB Connectors for user-specific

Mezzanine Boards Various additional

standard interfaces


CBM Protocol FeaturesCBM Protocol Features Standard initialization sequence Forward error correction of 1-Bit for all special

characters Protocol is extendable to continue sending over

switched and routed networks Open-ended hierarchical structure for concentrator

network Optimized data bandwidth up to 91.428 %

( 73.148 % with 8b/10b) Fast and efficient administration packets Well defined Deterministic Latency Messages Retransmission for Control Packets FPGA implementation easily portable to ASIC


ABB

SFP

DCB

SFPSFP

SFP

SFP

SFP

SFP

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

FEB4nx SiCBM01B2

ROC EthA

BSYNC-S

AUX

Config: CBM STS Demonstrator Config: CBM STS Demonstrator 11

FEB4nx SiCBM01B2

ROC SFPA

BAUX

FEB1nxGen

BEAMAUX...

ROC SFPA

BAUX

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BAUX

FEB4nxSiDem1CBM

STSDemo 1

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BSYNC-S

AUX

FEB4nxSiDem1

ROC SFPA

BAUX

FEB4nxSiDem1CBM

STSDemo 1

DCB

SFPSFP

SFP

SFP

SFP

SFP

DCB

SFPSFP

SFP

SFP

SFP

SFP

ABB

SFP

DABC

ABB

SFP

DC

B b

ackp

lan

eD

CB

backp

lan

e

12 ROC3 DCB3 ABB

some detailsyet to be

finalized


Config: CBM RPC Demonstrator Config: CBM RPC Demonstrator 11

FEET

ROC EthA

BSYNC-S

AUX

CLKGEN

CLK

25

0

CLK

15

6

SYNC_TDC andSYNC_250 is

generated in ROC

156/250 MHzclock

DABC

OnlineAnalysi

s

someauxdets

SYNCmessag

esender

RPCTest

Bench

FOPI RPCTest Environment

MBS System

CBMM-RPC

Demo 1

FEETFEET

FEETFEET

FEET

R2F

A

B

CLK

25

0

A

B

C

D

E

FC

LK1

56

G

H

SYN

C_TCLKdist

Startcounter

156 MHz clock

& SYNC_TDCdistribution

Hybrid DAQSystem:

triggered + time-

stamped


Towards the Towards the real thingreal thing


Design of the CBM readout Design of the CBM readout chainchain 'Starter Kits' and '1st round demonstrators' use

existing or pre-prototype read-out ASIC's, prime objective is fast availability to support tests of concepts and building blocks.

Key aspects for final CBM readout chain scalability to full CBM detector size and data rates

provide interface to FLES (First Level Event Selector) adapt to radiation environment

determine where COTS components can be used minimize functionality in exposed areas (on detector) put complex logic into unexposed or shielded areas


Cave LayoutCave Layout

Space foelectronics andother services

Shielding

Drawing: W. Niebur

For doses For doses consult FLUKA consult FLUKA calculations by calculations by

D. BertiniD. Bertini


ROC+DCB ROC+DCB ROB ROB

FEB ROB xxx

FLESSTS

FEET ROB xxx

FLESRPC ROC

on detector in annex buildingin 'cellar'

datadigitization

dataaggregation

dataaggregation

&buffering

dataprocessing


SummarySummary

We just got started, 'beamed in realitybeamed in reality' Clear path for the level 0 and 1 demonstrators

DAQ Workshop in December coordinate design work on CBM readout chain finalize DAQ/FLES IMoU part


The EndThe End

Thanks for Thanks for your attentionyour attention

Summary DAQ

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