Altera Corporation February 2008

CII51008-2.4

8. Cyclone II Memory Blocks

Introduction Cyclone® II devices feature embedded memory structures to address the on-chip memory needs of FPGA designs. The embedded memory structure consists of columns of M4K memory blocks that can be configured to provide various memory functions such as RAM, first-in first-out (FIFO) buffers, and ROM. M4K memory blocks provide over 1 Mbit of RAM at up to 250-MHz operation (see Table 8–2 on page 8–2 for total RAM bits per density).

Overview The M4K blocks support the following features:

■ Over 1 Mbit of RAM available without reducing available logic ■ 4,096 memory bits per block (4,608 bits per block including parity) ■ Variable port configurations ■ True dual-port (one read and one write, two reads, or two writes)

operation ■ Byte enables for data input masking during writes ■ Initialization file to pre-load content of memory in RAM and ROM

modes ■ Up to 250-MHz operation

Table 8–1 summarizes the features supported by the M4K memory.

Table 8–1. Summary of M4K Memory Features (Part 1 of 2)

Feature M4K Blocks

Maximum performance (1) 250 MHz

Total RAM bits (including parity bits) 4,608

Configurations 4K × 1 2K × 2 1K × 4 512 × 8 512 × 9

256 × 16 256 × 18 128 × 32 128 × 36

Parity bits v

Byte enable v

8–1

Overview

Table 8–2 shows the capacity and distribution of the M4K memory blocks in each Cyclone II device family member.

Packed mode v

Address clock enable v

Single-port mode v

Simple dual-port mode v

True dual-port mode v

Embedded shift register mode (2) v

ROM mode v

FIFO buffer (2) v

Simple dual-port mixed width support v

True dual-port mixed width support v

Memory Initialization File (.mif) v

Mixed-clock mode v

Power-up condition Outputs cleared

Register clears Output registers only

Same-port read-during-write New data available at positive clock edge

Mixed-port read-during-write Old data available at positive clock edge

Notes to Table 8–1: (1) Maximum performance information is preliminary until device characterization. (2) FIFO buffers and embedded shift registers require external logic elements (LEs)

for implementing control logic.

Table 8–2. Number of M4K Blocks in Cyclone II Devices (Part 1 of 2)

Device M4K Blocks Total RAM Bits

EP2C5 26 119,808

EP2C8 36 165,888

EP2C15 52 239,616

EP2C20 52 239,616

EP2C35 105 483,840

Table 8–1. Summary of M4K Memory Features (Part 2 of 2)

Feature M4K Blocks

8–2 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008

Cyclone II Memory Blocks

Control Signals

Figure 8–1 shows how the register clocks, clears, and control signals are implemented in the Cyclone II memory block.

The clock enable control signal controls the clock entering the entire memory block, not just the input and output registers. The signal disables the clock so that the memory block does not see any clock edges and will not perform any operations.

Cyclone II devices do not support asynchronous clear signals to input registers. Only output registers support asynchronous clears. There are three ways to reset the registers in the M4K blocks: power up the device, use the aclr signal for output register only, or assert the device-wide reset signal using the DEV_CLRn option.

1 When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.

EP2C50 129 594,432

EP2C70 250 1,152,000

Table 8–2. Number of M4K Blocks in Cyclone II Devices (Part 2 of 2)

Device M4K Blocks Total RAM Bits

Altera Corporation 8–3 February 2008 Cyclone II Device Handbook, Volume 1

Overview

Figure 8–1. M4K Control Signal Selection

Parity Bit Support

Error detection using parity check is possible using the parity bit, with additional logic implemented in LEs to ensure data integrity. Parity-size data words can also be used for other purposes such as storing user-specified control bits.

f Refer to the Using Parity to Detect Errors White Paper for more information.

Byte Enable Support

All M4K memory blocks support byte enables that mask the input data so that only specific bytes of data are written. The unwritten bytes retain the previous written value. The write enable (wren) signals, along with the byte enable (byteena) signals, control the RAM block’s write operations. The default value for the byte enable signals is high (enabled), in which

clock_b

clocken_aclock_a

clocken_b aclr_b

aclr_a

Dedicated Row LAB Clocks

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

renwe_b

renwe_a

6

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

byteena_b

byteena_a

addressstall_b

addressstall_a

8–4 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2008

http://www.altera.com/literature/wp/wp_stx_parity.pdf

Cyclone II Memory Blocks

case writing is controlled only by the write enable signals. There is no clear port to the byte enable registers. M4K blocks support byte enables when the write port has a data width of 1, 2, 4, 8, 9, 16, 18, 32, or 36 bits. When using data widths of 1, 2, 4, 8, and 9 bits, the byte enable behaves as a redundant write enable because the data width is less than or equal to a single byte. Table 8–3 summarizes the byte selection.

Table 8–4 shows the byte enable port control for true dual-port mode.

Figure 8–2 shows how the wren and byteena signals control the operations of the RAM.

When a byte enable bit is de-asserted during a write cycle, the corresponding data byte output appears as a “don’t care” or unknown value. When a byte enable bit is asserted during a write cycle, the corresponding data byte output is the newly written data.

Table 8–3. Byte Enable for Cyclone II M4K Blocks Note (1)

byteena[3..0]

Affected Bytes

datain × 1

datain × 2

datain × 4

datain × 8

datain × 9

datain × 16

datain × 18

datain × 32

datain × 36

[0] = 1 [0] [1..0] [3..0] [7..0] [8..0] [7..0] [8..0] [7..0] [8..0]

[1] = 1 - - - - - [15..8] [17..9] [15..8] [17..9]

[2] = 1 - - - - - - - [23..16] [26..18]

[3] = 1 - - - - - - - [31..24] [35..27]

Note to Table 8–3: (1) Any combination of byte enables is possible.

Table 8–4. Byte Enable Port Control for True Dual-Port Mode

byteena [3:0] Affected Port

[1:0] Port A (1)

[3:2] Port B (1)

Note to Table 8–4: (1) For any data width up to ×18 for each port.

Altera Corporation 8–5 February 2008 Cyclone II Device Handbook, Volume 1

Overview

Figure 8–2. Cyclone II Byte Enable Functional Waveform

Packed Mode Support

Cyclone II M4K memory blocks support packed mode. You can implement two single-port memory blocks in a single block under the following conditions:

■ Each of the two independent block sizes is less than or equal to half of the M4K block size. The maximum data width for each independent block is 18 bits wide.

■ Each of the single-port memory blocks is configured in single-clock mode.

f See “Single-Port Mode” on page 8–9 and “Single-Clock Mode” on page 8–24 for more information.

Address Clock Enable

Cyclone II M4K memory blocks support address clock enables, which holds the previous address value until needed. When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable.

inclock

wren

address

data

q (asynch)

an

XXXX

a0 a1 a2 a0 a1 a2

doutn ABXX XXCD ABCD ABFF FFCD

ABCD

byteena XX 10 01 11

XXXX

XX

ABCD

ABCDFFFF

FFFF

FFFF

ABFF

FFCD

contents at a0

contents at a1

contents at a2

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Cyclone II Memory Blocks

Figure 8–3 shows an address clock enable block diagram. The address register output is fed back to its input via a multiplexer. The multiplexer output is selected by the address clock enable (addressstall) signal. Address latching is enabled when the addressstall signal goes high (active high). The output of the address register is then continuously fed into the input of the register until the addressstall signal goes low.

Figure 8–3. Cyclone II Address Clock Enable Block Diagram

The address clock enable is typically used for cache memory applications to improve efficiency during a cache-miss. The default value for the address clock enable signals is low (disabled). Figures 8–4 and 8–5 show the address clock enable waveforms during the read and write cycles, respectively.

address[0]

address[N]

addressstall

clock

1 0

address[0] register

address[N