#5.2. Mach to hop - Cac mach khac.pptx

5/24/2018 #5.2. Mach to hop - Cac mach khac.pptx

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Chng 5phn 2

NHP MN MCH S

Mchthp:Cc loi mch khc


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Nidung

5. Mchgiim (Decoder)/ Mchm ho

(Encoder)

6. Mchdnknh (Multiplexer)/ Mchchia

knh (Demultiplexer)

7. MchtoParity/ Mchkimtra

8. Mchso snh (Comparator)


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5. Decoder/ Encoder


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Mchgiim (Decoder)

Nhiung vo/ nhiung ra Ng vo (n) thng thngt hnng ra (m)

Chuynm ng vo thnh m ng ra

nh x1-1:

Mim ng vo chtora mtm ng ra Cc m ng vo:

M nhphn

Your Code!

Cc m ng ra:

1-trong-m

Gray Code

BCD Code

enable

inputs


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Mchgiim nhphn (BinaryDecoders)

Mchgiim n-ra-2n: n ng vo v 2nng ra M uvo: n bit nhphn

M ura: 1-trong-2n

V d: n=2, mchgiim 2-ra-4

Ch x (k hiung vo dont care)


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Giim nhphn 2-ra-4


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74x139: BiutnglunlBngstht

Tnh hiuEnable tch ccmcthpv ng ra tchccmcthp


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Mchgiim hon chnh74x139


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74x138: Giim nhphn 3-to-8

Bngstht


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74x138

Biutnglunl

Mchlunl


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Ghp mchgiim

Mchgiim4ra16


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ngdngcamchgiim

Mtngdngphbinl giim achcho ccchip nh


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V d: giim BCD ran7 on


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n7 on(7-segment display)

n7 onl cchphbinhinthsthpphnhocsthplcphnSdngLED cho mion


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n7 on(7-segment display)

Bngcch iukhindng inqua miLED, mtsonssng v mtstt,

ttonn smong mun


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Giim BCD ra n7 onChuynsBCD sang thng tin thch hphinthtrn n7on


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Mchm ho

Nhiung vo/ nhiung ra

Chcnngngclivimchgiim

Outputs ( m ) t hninputs ( n)

Chuynm ng vo thnh mng ra

input

code

output

code

ENCODER


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Encoders vs. Decoders

Decoder Encoder

2^n-ra-nInput code: 1-trong-2^n

Output code: M nhphn

n-ra-2^nInput code: M nhphn

Output code:1-trong-2^n

decoders/encoders nhphn


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Mchm ho nhphn (BinaryEncoder)

2^n-ra-n encoder: 2^n ng vo v n ng ra Input code: 1-trong-2^n

Output code: M nhphn

V d: n=3, mchgiim 8-ra-3

Ng vo Ng raI0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y01 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

I1

I2

I3 Y1

Y2I4

I5

I6

I0

Y0

I7

Binary encoder


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Hinthcmchgiim 8-ra-3

Rt gn:Y0 = I1 + I3 + I5 + I7Y1 = I2 + I3 + I6 + I7Y2 = I4 + I5 + I6 + I7

I1

I2

I3

I4

I5

I6

I0

I7

Y1

Y0

Y2

Ng vo Ng raI0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y01 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1


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Hinthcmchgiim 8-ra-3

Giihn: I0khng nhhngnng ra Chmtng nhpckch hotti

mtthiim

ngdng: Giiquytnhngyu cutnhiu

thitb, nhngkhngphil nhng

yu cungthi.

Thitlpmcutin giiquytvncanhiuyu cu

I1

I2

I3

I4

I5

I6

I0

I7

Y1

Y0

Y2


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Cnc utin trong huhtcc ngdng


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Mchm ho c utin (PriorityEncoder)

Gn utin cho cc ng vo

Khi c nhiuhn1 ng vo c hiulc, ng ra tora m cang vo c utin cao nht.

Priority Encoder:H7=I7 (utin cao nht)H6=I6.I7H5=I5.I6.I7H4=I4.I5.I6.I7H3=I3.I4.I5.I6.I7H2=I2.I3.I4.I5.I6.I7H1=I1. I2.I3.I4.I5.I6.I7H0=I0.I1. I2.I3.I4.I5.I6.I7IDLE= I0.I1. I2.I3.I4.I5.I6.I7

EncoderA0=Y0 = H1 + H3 + H5 + H7A1=Y1 = H2 + H3 + H6 + H7

A2=Y2 = H4 + H5 + H6 + H7

I6

I5

I4 Y1

Y0I3

I2

I1

I7

Y2

I0

Binary encoder

I6

I5

I4

I3

I2

I1

I7

I0

Priority Circuit

H6

H5

H4

H3

H2

H1

H7

H0

IDLE

I6

I5

I4

I3

I2

I1

I7

I0

A1

A0

A2

IDLE

Priority encoder


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8-input priority encoder

I7 c utin cao nht, I0 thpnht

A2-A0 chasthtcang vo cutin cao nhtc hiulc

IDLE c hiulcnukhng c ng

vo no c hiulc


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74x148 8-input priority encoder

I/O tch ccmcthp Ng vo EnableGot Something": Group Select

Ng ra Enable


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74x148Bngstht


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74x148

27

Slunl

Cascading


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Cascadingpriority encoders

Mchm ho c utin 32-ng vo


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6. Multiplexer (MUX)/Demultiplexer (DeMUX)


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Multiplexer

A MUX truynmttrong nhngng vo can ra ng ra datrn tn hiuSelect

Ng vo SELECT sxcnhng vo no ctruynra Z


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2-ra-1 Multiplexer

Sel Out0 I0

1 I1

Out =I0* Sel+ I1*Sel


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4-ra-1 Mux

4-ra-1 Mux xutra mttrongbnng vo datrn gi trca2 tn hiuselect


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Xy dngMUX 4-ra-1

TMUX 2-ra-1


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MSI: 74x151 8-input 1-bit multiplexer

Bngstht

BiutngSlunl


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Demultiplexer

Demultiplexer (DEMUX)lyng vo duy nhtvphnphin ra vi ng ra. M ng vo SELECT sxc nhng ra no m ng vo

DATA struynqua

DATA ctruynra mtv chmtng ra cxc

nhbim cang voSELECT


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DEMUX

1-ra-8 demultiplexer

Ch : I l ng vo

DATA


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Tnghpcc hm logic tMUX

Cch hinthcLUT sdngMUX chnmtgitr(hngs) tlook-up table

V dhm XOR


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Giiphp slide trckhng hiuqu


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V d: HinthcmchvibngsthtsaubngmtMUX v cc cngkhc

A B X

0 0 1

0 1 1

1 0 0

1 1 1


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XOR 3 ng vo c thhinthcbng2 MUX 2 ra 1


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V d:HinthcmchvibngsthtsaubngmtMUX v cc cngkhc

A B C X

0 0 0 1

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 11 0 1 0

1 1 0 0

1 1 1 1


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BiuthcShannon

Btk hm boolean f(w1,w2, , wn) c thcvitdidng:

f(w1,w2, , wn)=*f(0,w2, ..., wn) +w1*f(1, w2, wn)


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BiuthcShannon

Example 1:f(w1,w2, w3)= w1w2+w1w3 + w2w3

Expanding this in terms of w1:f(w1,w2, w3)= w1(w2+w3)+ 1(w2w3)

f when w1=1 f when w1=0

Wrong??


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BiuthcShannon


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BiuthcShannon

V d2:

Chnxlmbinmrng


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BiuthcShannon

V d3:

Chnz lmbinmrng


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V d

Dng MUX 4 ra 1 v cc cnglunl cnthithinthchm sau:F (a, b, c, d) = SOP (1, 3, 5, 6, 8, 11, 15)

Yu cu: cv dl cc ng vo iukhincaMUX 4ra 1


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7. Parity Generator/ Checker


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CngExclusive OR v Exclusive NOR

XORX

Y

F

'' YXYXYX

'')'( YXYXYX

XOR:NAND 3 cp

XNOR:

XOR: AND-OR

Bngstht


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XOR and XNOR Symbols

CcbiutngtngngcacngXOR

CcbiutngtngngcacngXNOR


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ngdngcaXOR: MchParity

MchParity chn: tngsbit 1 trong chuibit (kcbit parity) l schn. Parity bit = 1, nuss1 trong chuibit (khng kparity) l sl

Parity bit = 0, nuss1 trong chuibit (khng kparity) l schn

MchParity l: tngsbit 1 trong chuibit (kcbit parity) l sl. V d: MchParity 4-bit

Input Even Parity Odd Parity0000 0 10001 1 01101 1 01111 0 11100 0 1

EVENODD

ODDEVEN


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Tree structure

Daisy-Chain Structure

EVEN

EVEN


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Source: http://en.wikipedia.org/wiki/Parity_bit
http://en.wikipedia.org/wiki/Parity_bithttp://en.wikipedia.org/wiki/Parity_bit


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Mchkimtra parity MSI: 74x280

NOTE: the 74x280 chip defines the even/odd paritybit opposite to the definition in the previous slides


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Mchkimtra parity


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d i


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ngdngcngXOR: Parity



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8. Comparator

M h h


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Mchso snh

Mchso snh so snh 2 sXutra 1 nuchngbngnhau

Xutra 0 nuchng khc nhau

Datrn cngXOR,trv0 nung vo gingnhauv 1 nuchng khc nhau

Datrn cngNXOR,trv1 nung vo gingnhau v 0 nuchng khc nhau

M h h 1 bit


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Mchso snh 1 bit

a b gt eq lt

0 0 0 1 00 1 0 0 1

1 0 1 0 0

1 1 0 1 0

M h h 4 bit


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Mchso snh 4 bit

a0

b3a3

b2a2

b1

a1

b0

eq

M h h 4 bit


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Mchso snh 4 bit

a0

b3a3

b2a2

b1a1

b0

gt

M h h 4 bit


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Mchso snh 4 bit

lt

M h h 4 bit


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Mchso snh 4 bit

74x85 l mchso snh tiu chunvinhngctnh sau:

if (A>B) lt=0, eq=0, gt=1

if (A


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Mchso snh 16 bit

Ghp 4 IC 74x85 xy dngmtmchso snh 16bita[ 15:0 ]

b[ 15:0 ]

[15:12]

4

4BA

gel gt

eqlt

4

4 BA

gel gt

eqlt

[15:12] [11:8] [11:8] [7:4]

4

4 BA

gel gt

eqlt

4

4 BA

gel gt

eqlt

010

[7:4] [3:0] [3:0]

gt eqlt

Final results ofcomparison

M h h 16 bit


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Mchso snh 16 bit

Mchsutin so snh 4 bit cao nht2 ng vo

Trongbcuny:a nhhnb nu4 MSB nhhn

a lnhnb nu4 MSB lnhn

Nu4 MSB ca2 sbngnhau, ktqucaphp so snhsl ktquso snh bit thphn

V d


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V d

Thitkmchtm slnnhtsnhnhttrong n s4 bit sdngmchso snh v MUXs


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#5.2. Mach to hop - Cac mach khac.pptx

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