5 – Need to handle the “true PF registers” Customer game...

Thermal arm-wrestling

Design of a video game using two programmable flags (PF) interrupts

Tutorial on handling 2 Hardware interrupts from an external device that cause the same IVG12 PF-Interrupt A

11/27/2014

Thermal Arm Wrestling, Copyright M. Smith, ECE, University of Calgary,

Canada 2 / 24 + extras

Problem to be solvedCustomer game concept

I WIN YOU WIN

•Has two TMP03 thermal sensors and a ready signal (LED)•At the ready signal – the two players have to use bio-feedbackto move the cursor into the winning area•Three play modes

•One person player – moves the cursor with one sensor•One person player – controls the cursor with two sensors sort of EXO-Sketch mode•Game mode – two players

Sensor reading is determined by the difference in temperature NOWcompared to the temperature at the ready signal

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Customer game planPlayer1_TemperatureNow, and Player1_TemperatureStartDitto player 2

While not started {Determine Player1 Temperature( ) , Player2 temperature( )Update Game Screen (with start information ) }

Cursor is centered ( ) – update Game screen ( )

While nobody has won {Determine Player1 Temperature( ) , Player2 temperature ( )Determine Player1, player2 difference in temperatureif player1 difference larger then decrease cursor, else cursor ++Update Game screenDetermine if somebody has won

}Display winning message

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5 – Need to handle the “true PF registers” to generate a hardware interrupt

Functions needed unsigned long int SetPFInterruptsASM( ??)

Returns old interrupt settings Set new settings

void StartPFInterruptsASM(???) void StopPFSettingsASM(???)

Hardware information Chapter 14

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PF registers

Direction, Data, Polarity and Enable all from Lab. 2

Flag Mask registers – 14-11 Flag mask Interrupt data register – basically

which PF pins have been set to allow to cause interrupt

Flag mask Interrupt Set register – sets PF pin that is allowed to cause an interrupt, without the need for a read – or mask – write operation

Flag Mask Interrupt Clear register – which PF pin is no longer allowed to cause an interrupt without the need for a read – and mask – write operation

Flag interrupt Sensitivity register (FIO_EDGE) – set for edge-sensitive – also need FIO_BOTH

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6 – Build a test to show that write the needed code (in ASM) to set up the PF interrupts

Registers described in Chapter 14 Stop all interrupts for the moment – CLI instruction Need to set FIO_MASKA_D bits

1 Write only needed if “set” using FIO_MASK_S register Need to set FIO_POLAR for active rising edge – Lab 2 code

1 read – then mask – then 1 write Need to set FIO_INEN (R – mask – W) Need to set FIO_DIR (R – mask – W) Need to clear FIO_FLAG_D so that don’t think interrupt already

happened (1W if use FIO_FLAG_C register approach)) Need to set FIO_EDGE and FIO_BOTH (2R – mask 2W) Restart interrupts – STI instruction – but with PF interrupt stoppedPossibility that missing stuff

since first time tried this

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First Test for Set up PF interrupts

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Need to do code review After fixing the error – get this result

Check code – need to return old interrupt level FIO_MASKA_D – that requires a read that I had not designed in – change the test

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Move onto setting FIO_FLAG registers

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Check Ability to turn off PF interrupts

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Test for interrupts using switches

PF interruptsactive

NOTHING HAPPENING

SYSTEM ISHUNG

#pragma interruptvoid Hardware_PF_ISR(void) ;

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Turns out – missing stuff in set up IMASK -- Page 4-33

Global register – allows IVG12 interrupts to occur SIC_IMASK – Page 4-28

System interrupt mask – especially for peripheral devices

Enabling PF Interrupt A during SetUpPFInterrupts( ) fixed the problem of getting INTO interrupts – but the function never came out BECAUSE

Bit 11 of FIO_FLAG_D MUST BE CLEARED inside interrupt service routine – clearing the interrupt bit!!!!!!

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What is the necessary code for the C++ interrupt service routine to handle the PF11 interrupts?

Add your code here Essentially 3 lines of code needed

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Add this stage Either PF11 interrupt

Need PF10 interrupt

Need both

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Core timer interruptPF interrupt

Core timer interrupt SetEVT_ASM(ik_timer, CoreTimerISR)

PF11 interrupt SetEVT_ASM(ik_ivg12, PF11_ISR);

PF10 interrupt SetEVT_ASM(ik_ivg12, PF10_ISR);

See Blackfin reference sheet If Core timer and PF11 interrupts occurred – different

interrupt levels If Core timer and PF10 interrupts occurred – different

interrupt levels If PF11 and PF10 interrupts occurred – SAME

interrupt level

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PF11 and PF10 interruptPF interrupt

PF11 and PF10 interrupt SetEVT_ASM(ik_ivg12, PF_ISR);

ISR code must look like this

#pragma interruptvoid PF_ISR(void) {

If this interrupt was caused by PF11 interrupt – then do this action – CalculatePF11Temperature( );

But if this interrupt was caused by PF10 interrupt –then do this action – CalculatePF10Temperature( );

Clear the correct interrupt flag so the ISR can exit properly

}

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What hardware register can tell us which of the two PF lines caused an interrupt?

See hardware manual on page 14-13 for the information

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What is the necessary code for the C++ interrupt service routine to handle the PF10 interrupts?

Add your code here Essentially 3 lines of code needed

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PF11 interrupt test#pragma interruptvoid BothPF_ISR(void) {

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PF10 test

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Can handle both PF10 and PF11 interrupts – but ISR can’t tell the different

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Can handle both PF10 and PF11 interrupts – but ISR CAN tell the different

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Information taken from Analog Devices On-line Manuals with permission http://www.analog.com/processors/resources/technicalLibrary/manuals/

Information furnished by Analog Devices is believed to be accurate and reliable. However, Analog Devices assumes no responsibility for its use or for any infringement of any patent other rights of any third party which may result from its use. No license is granted by implication or otherwise under any patent or patent right of Analog Devices. Copyright Analog Devices, Inc. All rights reserved.

5 – Need to handle the “true PF registers” Customer game...

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