1 EE365 Sequential PLD timing Registers Counters Shift registers.
Registrid Registers
14
23/03/22 T. Evartson 1 Registrid Registers RG d 0 d 1 d n-1 c q 0 q 1 q n-1 TT c D TT c D TT c D TT c D q0 q1 q2 q3 c d0 d1 d2 d3 d 0 d 1 d n-1 c q 0 q 1 RG q n-1
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Registrid Registers. RG. q 0. d 0. d 0. RG. q 0. d 1. d 1. q 1. q 1. d n-1. q n-1. d n-1. q n-1. c. c. q 3. q 2. q 1. q 0. TT. TT. TT. TT. c. D. c. D. c. D. c. D. c. d 3. d 2. d 1. d 0. Asetusega register. d 0. RG. q 0. RG. q 0. d 0. - PowerPoint PPT Presentation
Transcript of Registrid Registers
19/04/23 T. Evartson 1
Registrid Registers
RG
d 0
d 1
d n-1
c
q 0
q 1
q n-1
TT
c D
TT
c D
TT
c D
TT
c D
q0q1q2q3
c
d0d1d2d3
d 0
d 1
d n-1
c
q 0
q 1
RG
q n-1
19/04/23 T. Evartson 2
RG
d 0
d 1
d n-1
c
q 0
q 1
q n-1R
d 0
d 1
d n-1
c
q 0
q 1
RG
q n-1
R
TT
c D
TT
c D
TT
c D
TT
c D
q0q1q2q3
C
d0d1d2d3
RRRR
RESET
Asetusega register
19/04/23 T. Evartson 3
19/04/23 T. Evartson 4
RG
d 0
d 1
c
q 0
q 1
q n-1
b0
b1
d n-1
bn-1
w
Register mis võimldab valida kahe info allika vahel.
TT
c
qi
1
&&
J K
1
&&M
1
11bi di
M=1 bi => RG
M=0 di => RG
C
19/04/23 T. Evartson 5
19/04/23 T. Evartson 6
q 3 q 2 q 1 q 0
LI RO
q 3 q 2 q 1 q 0
LO RIq 3 q 2 q 1 q 0
Nihkeregister Shift register
TT
cS
R
TT
cS
R
TT
cS
R
TT
cS
R
q3 q2 q1 q0
1
LI
c
19/04/23 T. Evartson 7
19/04/23 T. Evartson 8
19/04/23 T. Evartson 9
Nihkeregister paralleel laadimisega
TT
cR T
1
&&
1
di
PL=1 di => RG
PL=0 R1
TT
cR T
++
PL
C
qi+1
qi
RESET
19/04/23 T. Evartson 10
19/04/23 T. Evartson 11
19/04/23 T. Evartson 12
Reversiivsed nihkeregistrid
LI RO
q 3 q 2 q 1 q 0
LO RIq 3 q 2 q 1 q 0
M=1
M=0
TT
c D
TT
c D
TT
c D
qi-1qiqi+1
c
di+1 di-1
1
&&
1
M
di
19/04/23 T. Evartson 13
19/04/23 T. Evartson 14
