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Registers

By : Eng. Lina

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p g

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Benefits of registers

Flip-flops are limited because they can store only one bit. Most computers work with integers and single-precision floating-

point numbers that are 32 /64-bits long. A registeris an extension of a flip-flop that can store multiple bits. Registers are commonly used as temporary storage in a processor.

They are faster and more convenient than main memory. More registers can help speed up complex calculations.

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A basic register

Basic registers are easy to build. Registers are made using multiple flip-flops .

We can store multiple bits just by putting a bunch of flip-flops together! A 4-bit register is shown on the right, and its internal

implementation is below.

This register uses D flip-flops

its easy to store data without worrying about flip-flopinput equations. All the flip-flops share a common CLKand CLR (RESET)

signals.

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Registers

Another way to represent a 4-bit register

You could see the timing diagram in the followingSlide .

D Q

R

Reset

D Q

R

D Q

R

D Q

RCLK

I0

I1

I2

I3

A0

A1

A2

A3

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Registers

D Q

R

Reset

D Q

R

D Q

R

D Q

RCLK

I0

I1

I2

I3

A0

A1

A2

A3

CLK

I3

I2

I1

I0

A3

A2

A1

A0Note: New data has to go in with

every clock11/14/20135

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The input D3-D0is copied to the output Q3-Q0on everyclock cycle. How can we store the current value for more than one cycle?

Lets add a load input signal LD to the register. If LD = 0, the register keeps its current contents. If LD = 1, the register stores a new value, taken from inputs D3-D0.

LD Q(t+1)

0 Q(t)

1 D3-D0

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Shift Register

The binary information in a register can be - in addition to storing-canbe moved from stage to stage within the register or into or out of the

register upon application of clock pulses. This type of bit movement or shifting is essential for certain

arithmetic and logic operations used in microprocessors.

Shift Register :a group of FFs arranged so that binary numbers storedin the FFs can be shifted from one FF to the next FF, for every clockpulse.

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A shift registershifts its output once every clock cycle.

SIis an input that supplies a new bit to shift intothe register. For example, if on some positive clock edge we have:

SI = 1Q0-Q3= 0110

then the next state will be:

Q0-Q3= 1011

The current Q3(0in this example) will be lost on the next cycle.

Shift registers

Q0(t+1) = SIQ1(t+1) = Q0(t)Q2(t+1) = Q1(t)Q3(t+1) = Q2(t)

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Shift direction

The circuit and example make it look like the register shifts right.

But it really depends on your interpretation of the bits. If you considerQ3 to be the most significant bit instead, then the register is shifting

in the oppositedirection!

Q0(t+1) = SIQ

1(t+1) = Q

0(t)

Q2(t+1) = Q1(t)Q3(t+1) = Q2(t)

Present Q0-Q3 SI Next Q0-Q3

ABCD X XABC

Present Q3-Q0 SI Next Q3-Q0

DCBA X CBAX

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Shift Registers Classification

Shift registers can be classified into: Shift right registers.

Shift left registers. Serial in/Serial out shift registers. Serial in/Parallel out shift registers. Parallel in/Serial out shift registers. Parallel in/Parallel out shift registers. Universal shift registers.

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Serial/Parallel Data Conversion

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1 0 1 0 1 1 1 1Serial in Serial out

Shift registers can be used to convert from serial-to-parallel or the reverse from parallel-to-serial.

1 0 1 0 1 1 1 1Serial in

Parallel out

1 0 1 0 1 1 1 1 Serial out

Parallel in

1 0 1 0 1 1 1 1

Parallel in

Parallel out

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QUIZ

Q#1- This represents a ___ register.

a. Parallel-in, parallel-out

b. Serial-in, parallel-out

ANS: serial-in parallel-out

Q#2- This represents a ___ register.a. Parallel-in, parallel-out

b. Serial-in, serial-out

ANS: serial-in serial-out

Q#3- This represents a ___ register.a. Parallel-in, serial out

b. Serial-in, parallel-out

ANS: parallel-in serial-out

Q#4- This represents a ___ register.a. Parallel-in, serial out

b. Parallel-in, parallel-out

ANS: parallel-in parallel-out

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Serial-in / Parallel-output Shift Register

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Note the use of D FFs.Clock (CLK) inputs wired in parallel.

Clear (CLR) inputs can be activated with LOWor disabled with HIGH.

Preset (PS) inputs deactivated.

Parallel outputs here.Order= A B C D

Inputs here:(1) Data(2) Clock(3) Clear

Clear input:Active = 0

Deactivated = 1

Clock input:

Positive-edgetriggering

Clock Pulse 1

Clear = 0

Data = 1

0 0 0 01 0 0 0

Clock Pulse 2

Clear = 1

Data = 1

1 1 0 00 1 1 0

Clock Pulse 3

Clear = 1

Data = 1

Clock Pulse 4

Clear = 1

Data = 0

0 0 1 1

Clock Pulse 5

Clear = 1

Data = 0

0 0 0 1

Clock Pulse 6

Clear = 1

Data = 0

Clock Pulse 7

Clear = 1

Data = 1

1 0 0 00 1 0 0

Clock Pulse 8

Clear = 1

Data = 04-bit

serial-in

parallel outshift right

shift register

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Clock Pulse 1

Clear = 0

Data = 1

Clock Pulse 2

Clear = 1

Data = 1

Clock Pulse 3

Clear = 1

Data = 0

Clock Pulse 4

Clear = 1

Data = 0

Clock Pulse 5

Clear = 1

Data = 1

QUESTION #1This is a ___ type shift register.

A. Serial-in, parallel outB. Parallel-in, serial-out

A: Serial-in, parallel-out

QUESTION #2What is the 4-bit output (bit A on left, D on right) after pulse 1?

A: 0000

QUESTION #3What is the 4-bit output (bit A on left, D on right) after pulse 2?

A: 1000

QUESTION #4What is the 4-bit output (bit A on left, D on right) after pulse 3?

A: 0100

QUESTION #5What is the 4-bit output (bit A on left, D on right) after pulse 4?

A: 0010

QUESTION #6What is the 4-bit output (bit A on left, D on right) after pulse 5?

A: 1001

QUESTION #7What is the 4-bit output (bit A on left, D on right) after pulse 6?

A: 1100

Clock Pulse 6

Clear = 1

Data = 1

QUIZ

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Serial input / Serial output Shift Registers

4-Bit Shift Register

Serial

InputSerial

Output

D Q D Q D Q D Q

CLK

SI SO

Serial

InputSerial

Output

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Serial input / Serial output Shift Registers

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D Q D Q D Q D Q

CLK

SI SO

Q3

SI

Q2

Q1

Q0

CLK

Q3 Q2 Q1 Q0

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How SISO Shift register work

In order to get the data out of the register, they must be shiftedout serially.

This can be done destructively or non-destructively. For destructive readout, the original data is lost and at the end of

the read cycle, all flip-flops are reset to zero.

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How SISO Shift register work

To avoid the loss of data, an arrangement for a non-destructivereading can be done by adding two AND gates, an OR gate and an

inverter to the system. The construction of this circuit is shown below.

The data is loaded to the register when the control lineis HIGH =1 (i.e WRITE).

The data can be shifted out of the register when thecontrol line is LOW(ie READ).

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Serial data transfer

One application of shift registers is converting between serial dataand parallel data.

Computers typically work with multiple-bit quantities. ASCII text characters are 8 bits long. Integers, single-precision floating-point numbers, and screen pixels

are up to 32 bits long.

But sometimes its necessary to send or receive data serially, or one bit