2a. ECE301 - Introduction to VVerilog HDL

7/27/2019 2a. ECE301 - Introduction to VVerilog HDL

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VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Introduction to Verilog HDL

Prof.S.Sivanantham

VIT UniversityVellore, Tamilnadu. India

E-mail: [email protected]


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After completing this lecture, you will be able to:

Understand the features of HDLs and Verilog HDL Describe the HDL-based design flow

escr e e as c ea ures o e mo u es n er og

Describe how to model a design in structural style

Describe how to model a design in behavioral style

Describe how to model a desi n in mixed st le

Describe how to simulate/verify a design using Verilog HDL

ECE301 VLSI System Design FALL 2011 S.Sivanantham

Slides are adopted from Digital System Designs and Practices Using Verilog HDL and FPGAs , John Wiley


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HDL is an acronym ofHardware Description Language.

Two most commonly used HDLs: Verilog HDL (also called Verilog for short)

ery g -spee n egra e c rcu s

Features of HDLs:

.

Functional verification can be done early in the designcycle.

Designing with HDLs is analogous to computerprogramming.



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It is a general-purpose, easy to learn, and easy to use HDL

language. It allows different levels of abstraction to be mixed in the

.

It is supported by all logic synthesis tools.

It rovides a owerful Pro rammin Lan ua e Interface(PLI).

Allow us to develop our own CAD tools such as delay

ca cu ator.



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-Design specification

Desi n enter Tar et-inde endent art

Front-end design

Functional verification

PLD

CPLD/FPGA

GA/standard cell

Device selectedDevice selected Cell library selected

Synthesis and optimization Synthesis and optimization

Synt

hesis

Place and route Place and route

et-dependentpart

Post-synthesis verification Post-synthesis verification

mentation

Timing analysis

ProgrammingProgramming

Timing analysisTarg

Imple


PrototypingPrototyping Prototyping Back-end design


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The basic unit of a digital system is a module.

Each module consists of: a core circuit (calledinternal orbody) --- performs the

requ re unc on

an interface (calledports) --- carries out the requiredcommunication between VCC

the core circuit

and outside.

14 13 12 11 10 9 8


1 2 3 4 5 6 7

GND


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module --- The basic building block in Verilog HDL.

It can be an element or a collection of lower-level designblocks.module Module name

Port List, Port Declarations (if any)

Parameters (if any)

Declarations ofwires, regs, and other variables

Instantiation of lower level modules or primitives

Data flow statements (assign)

.into these blocks).

Tasks and functions.


endmodule statement


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Verilog HDL uses almost the same lexical conventions as Canguage.

Identifiers consists of alphanumeric characters, _, and $.

- .

White space:blank space (\b), tabs (\t), and new line (\n).

Comments:

// indicates that the remaining of the line is a comment.

/* .*/ indicates what in between them are comments.

Sized number: `

4`b1001 --- a 4-bit binary number


16`habcd --- a 16-bit hexadecimal number


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Unsized number: `

2007 --- a 32-bit decimal number by default `habc --- a 32-bit hexadecimal number

x or z va ues: x eno es an un nown va ue; z eno es ahigh impedance value.

Ne ative number: -`

-4`b1001 --- a 4-bit binary number

-16`habcd --- a 16-bit hexadecimal number

_ and ?

16`b0101_1001_1110_0000


8`b01??_11?? --- equivalent to a 8`b01zz_11zz


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In Verilog HDL

0 and1 represent logic values low and high, respectively.

z indicates the high-impedance condition of a node or net.

x n ca es an un nown va ue o a ne or no e.

Value Meaning

0 Logic 0, false condition

x

z

,

Unknown logic value

High impedance



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Verilog HDL has two classes of data types.

Nets mean any hardware connection points.

Variables represent any data storage elements.

Nets Variablesw re

tri

wand

supp y

supply1

tri0

reg

integer

real

trior

wortriand

tri1trireg

timerealtime



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A net variable

can be referenced anywhere in a module.

must be driven by a primitive, continuous assignment, , .

A variable

can be referenced an where in a module.

can be assigned value only within a procedural statement,task, or function.

cannot be an input or inout port in a module.



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Structural style

Gate level comprises a set of interconnected gateprimitives.

primitives.

Dataflow style specifies the dataflow (i.e., data dependence) between

registers.

s spec e as a set o cont nuous ass gnment statements.



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Behavioral or algorithmic style

is described in terms of the desired design algorithm

is without concerning the hardware implementation.

can be described in any high-level programming

language. Mixed style

is the mixing use of above three modeling styles.

is commonly used in modeling large designs. In industry, RTL (register-transfer level) means


= syn es za e e av ora a a ow cons ruc s


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Port Declaration

input: input ports.

output: output ports.

nou : rec ona por s

Port Connection Rules

Positional association



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module half_adder(x, y, s, c);

in ut x, ;

output s, c;

// -- half adder body-- //// instantiate primitive gates

xor xor1 (s, x, ;

Instance name is optional.

module full_adder(x, y, cin, s, cout);

and and1 (c, x, y);

endmodule

input x, y, cin;

output s, cout;

wire s1,c1,c2; // outputs of both half adders

// -- full adder body-- //

// instantiate the half adderhalf_adder ha_1 (x, y, s1, c1);

half_adder ha_2 (.x(cin), .y(s1), .s(s), .c(c2));

or (cout, c1, c2);

Connecting by using named association


endmodule.


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// gate-level hierarchical description of 4-bit adder-

module half_adder (x, y, s, c);input x, y;output s, c;

a a er o y// instantiate primitive gatesxor (s,x,y);and c xendmodule



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// gate-level description of full adder_ , , , ,

input x, y, cin;output s, cout;wire s1, c1, c2; // outputs of both half adders

u a er o y// instantiate the half adderhalf_adder ha_1 (x, y, s1, c1);half adder ha 2 cin s1 s c2_ _or (cout, c1, c2);endmodule



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// gate-level description of 4-bit adder

_ _ , , _ , , _

input [3:0] x, y;input c_in;

output [3:0] sum;

output c_out;

wire c1, c2, c3; // intermediate carries

// four_bit adder body// instantiate the full adder

full_adder fa_1 (x[0], y[0], c_in, sum[0], c1);

full_adder fa_2 (x[1], y[1], c1, sum[1], c2);

u _a er a_ x , y , c , sum , c ;

full_adder fa_4 (x[3], y[3], c3, sum[3], c_out);

endmodule



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xy

4-bit parallel adder

S

cout c0

x[0]x[1]x[2]x[3] y[0]y[1]y[2]y[3]

c0coutc1c2c3

y x

CinCoutS

y x

CinCoutS

y x

CinCoutS

y x

CinCoutS

x

s[0]s[1]s[2]s[3]

x

y

s

cout

cin

HA

s c

s

ys1 c2x

y


HA

c c


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module full_adder_dataflow(x, y, c_in, sum, c_out);

input x, y, c_in;output sum, c_out;

assign #5 {c_out, sum} = x + y + c_in;

endmodule

cin s

Full Adderxy cout



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module full_adder_behavioral(x, y, c_in, sum, c_out);

input x, y, c_in;output sum, c_out;reg sum, c_out; // sum and c_out need to be declared as reg types.

speci y t e unction o a u a er always @(x, y, c_in)// can also use always @(*) or always@(x or y or c_in)#5 {c_out, sum} = x + y + c_in;endmodule



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-

module full_adder_mixed_style(x, y, c_in, s, c_out);

input x, y, c_in;output s, c_out;reg c_out; x

scin

sc

sx

ys1c2

x

wire s1, c1, c2;// structural modeling of HA 1.xor xor_ha1 (s1, x, y);and and ha1 c1 x

ycout

HA

HA

c c1

_// dataflow modeling of HA 2.assign s = c_in ^ s1;assign c2 = c_in & s1;

e av ora mo e ng o ou pu ga e.always @(c1, c2) // can also use always @(*)c_out = c1 | c2;endmodule



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Module Under TestStimulus

Stimulus Block

Response

StimulusTop-Level Block

o u e n er esmu us oc

Res onse



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$display displays values of variables, string, or expressions

$display(ep1, ep2, , epn);

ep1, ep2, , epn: quoted strings, variables, expressions.

mon tormon tors a s gna w en ts va ue c anges.

$monitor(ep1, ep2, , epn);

mon o on ena es mon or ng opera on.

$monitotoffdisables monitoring operation.

s op suspen s e s mu a on. $finish terminates the simulation.



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Time scale compiler directive

`timescale time_unit / time_precision

The time_precision must not exceed the time_unit.

For instance, with a timescale 1 ns/1 ps, the delayspecification #15 corresponds to 15 ns.

uses e same me un n o e av ora an ga e-level modeling.

unit.



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--- -

// Gate-level description of 4-bit adder_ _ , , _ , , _

input [3:0] x, y;input c_in;output [3:0] sum;output c_out;wire C1,C2,C3; // Intermediate carries// -- four_bit adder body--// Instantiate the full adder

full_adder fa_1 (x[0],y[0],c_in,sum[0],C1);full_adder fa_2 (x[1],y[1],C1,sum[1],C2);full_adder fa_3 (x[2],y[2],C2,sum[2],C3);u _a er a_ x ,y , ,sum ,c_ou ;

endmodule



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--- -

[0]c_in

full adder

fa_1.ha_2.S

fa_1.ha_1.C

[0]

[0]

full_adder

fa_2

_

fa_3

_

fa_4fa_1.Coutfa_1.ha_2.Cfa_1.ha_1.S

[1]x

[1]yCin

[1]SCout

[2]x

[2]yCin

[2]SCout

[3]x

[3]yCin

[3]SCout

[0]

[0]

c_outsum[3:0]

[3:0]

y[3:0][3:0]

x[3:0][3:0]

After dissolving one full adder.



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---

`timescale 1 ns / 100 ps // time unit is in ns._ _ _

//Internal signals declarations:reg [3:0] x;

reg c_in;wire [3:0] sum;

wire c out;_// Unit Under Test port map

four_bit_adder UUT (.x(x), .y(y), .c_in(c_in), .sum(sum), .c_out(c_out));reg [7:0] i;

initial begin // for use in post-map and post-par simulations.// $sdf_annotate ("four_bit_adder_map.sdf", four_bit_adder);// $sdf_annotate ("four_bit_adder_timesim.sdf", four_bit_adder);


en


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---initial

=


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---

0ns 0 0 0 00 # 280ns 0 e 0 0e

# 20ns 0 1 0 01

# 40ns 0 2 0 02

# 60ns 0 3 0 03

# 300ns 0 f 0 0f

# 320ns 1 0 0 01

# 340ns 1 1 0 02

# 80ns 0 4 0 04

# 100ns 0 5 0 05

# 120ns 0 6 0 06

# 360ns 1 2 0 03

# 380ns 1 3 0 04

# 400ns 1 4 0 05140ns 0 7 0 07

# 160ns 0 8 0 08

# 180ns 0 9 0 09

420ns 1 5 0 06

# 440ns 1 6 0 07

# 460ns 1 7 0 08

# 220ns 0 b 0 0b

# 240ns 0 c 0 0c

# 500ns 1 9 0 0a

# 520ns 1 a 0 0b



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2a. ECE301 - Introduction to VVerilog HDL

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