2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 1 Introduction to Embedded Data Converters...

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Transcript of 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 1 Introduction to Embedded Data Converters...

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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 1 Introduction to Embedded Data Converters Akira Matsuzawa Tokyo Institute of Technology
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 2 Contents 1. Introduction 2. Characterization of data converters 3. Overview of high-speed A/D converters 4. Overview of high-speed D/A converters 5. Overview of over-sampling sigma-delta data converters 6. Basic design considerations
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 3 1. Introduction Mixed signal systems Software defined radio Digital read channel Mixed Signal SoC Progress of ADC and DAC Power and area Embedding
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 4 Basic mixed signal system DSPADCDAC Pre Filter Post Filter AGC Clock Continuous time =Analog Discrete time =Digital Continuous time =Analog Mixed signal systems basically consist of DSP, ADC, DAC, and pre/post filters. The signals are converted between continuous time and discrete time.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 5 Software defined radio IMT-2000 RF GSM RF Bluetooth RF GPS RF GPS BB Bluetooth BB GSM BB IMT-2000 BB MCU Power Multi-standards and multi chips Future cellular phone needs 11 wireless standards!! Current Yrjo Neuvo, ISSCC 2004, p.32 RF filter LNA X FilterADC Frequency Synthesizer Filter PA DAC X Filter DSP Mixer Future Multi-bands and Multi-standards on a single chip Future wireless systems need powerful ADC and DAC for software defined radio. On a chip
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 6 Mixed signal tech. ; Digital read channel Variable Gain Amp. Variable Gain Amp. Analog Filter Analog Filter A to D Converter A to D Converter Digital FIR Filter Digital FIR Filter Viterbi Error Correction Viterbi Error Correction Clock Recovery Clock Recovery Voltage Controlled Oscillator Voltage Controlled Oscillator Data Out Data In (Erroneous) Data Out (No error) Analog circuit Digital circuit Digital storage needs high speed mixed signal technologies. For the reduction of error rate, high speed ADC is the key. Pickup signal DVD 7b 400MHz
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 7 Mixed signal SoC Pixel Operation Processor Pixel Operation Processor IO Processor IO Processor AV Decode Processor AV Decode Processor Back -End System Cont- roller System Cont- roller CPU CPU2 VCO ADC Gm-C Filter Gm-C Filter PRML Read Channel PRML Read Channel Servo DSP Analog Front End Analog Front End Front-End Analog FE +Digital R/C 0.13um, Cu 6Layer, 24MTr Okamoto, et al., ISSCC 2003 Mixed signal SoC can realize full system integration for DVD application. Embedded analog is the key.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 8 Progress of high-speed ADC 0.1 10 Pd/ 2 N Gsps [mW] Pd of high speed CMOS ADCs Conversion rate [x100Msps] 1 1mW/2 N Gsps 10mW/2 N Gsps This Work 10 1 6b, 1GHz ADC 2W, 1.5um Bipolar 6b, 800MHz ADC 400mW, 2mm 2 0.25umCMOS 7b, 400MHz ADC 50mW, 0.3mm 2 0.18umCMOS ISSCC 2002 ISSCC 2000 Matsuzawa, ISSCC 1991 World lowest Pd HS ADC High speed ADC can be embedded in CMOS resulting in power reduction. ISSCC 1991 Sushihara and Matsuzawa, ISSCC 2002 Sushihara, et al, ISSCC 2000 1/8
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 9 Progress of A/D converter; video-rate 10b ADC 198019821993Now Board Level (Disc.+Bip) 20W $ 8,000 Conventional productWorld 1 st Monolithic Bipolar (3um) 2W $ 800 World lowest power CMOS (1.2um) 30mW $ 2.00 CMOS (0.15um) 10mW $0.04 SoC Core 1/2000 in Power and 1/200,000 in cost during past 20 years ADC was the bottle-neck for the digital TV and Video systems Technology progress has solved this problem. K. Kusumoto and A. Matsuzawa, ISSCC 1993. T. Takemoto and A. Matsuzawa, JSC, pp.1133-1138, 1982.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 10 Power reduction Area reduction Power and area reduction of video-rate 10b ADCs Power and area of ADC have been reducing continuously. Currently, ADC can be embedded on a chip
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 11 M. Hotta et al. IEICE 2006. June Power and area reduction of video-rate 10b ADCs
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 12 Embedding ADC on a CMOS chip 6b Video ADC 8b low speed ADC;DAC Digital Video filter 8b CPU 1993 Model: Portable VCR with digital image stabilizing CMOS ADC and DAC has been embedded on a CMOS chip. This has realized low cost and low power digital portable AV products. System block diagram A. Matsuzawa, JSC, pp. 470-480, 1993.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 13 2. Characterization of data converters Basic functions of ADC and DAC Static performance INL, DNL, monotonicity Quantization noise Dynamic performance SNR, SFDR, THD, SNDR, ENOB Sampling Jitter ERB Glitch Figure Of Merit Performances and applications Needed performances for wireless systems
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 14 Basic functions of ADC Time Voltage Time SamplingQuantization 0001 0010 0111 1000 1001 1000 0111 0101 0011 0010 0100 0111 0110 Coding Digital Sampling Quantization Coding Analog ADC Sampling: Sampling the analog signal with accurate timing. Quantization: Express the converted data with certain accuracy. CLK Voltage
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 15 Static performance INL: Integrated Non-Linearity INL and DNL are the major static performance indicators of ADC and DAC. DNL: Differential Non-Linearity
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 16 DNL and INL DNL profileINL profile
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 17 Monotonicity in DAC Keep monotonic In Out Large DNL Degrade monotonicity In Out 1/2 1/4 1/8 1/16 1/32 1/2 1/4 1/8 1/16 1/32 01111->10000 1/2 Binary weight At the change of MSB bit Binary coded DAC often degrades monotonicity. The monotonicity stands for the qualitative characteristics of data converters of which transfer function keep the monotonic increase or decrease. If the converter can not guarantee the monotonicity, The feedback loop doesnt work properly and results in backrush.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 18 Quantization noise Transfer characteristics Quantization noise Quantization causes noise Higher SNR needs higher resolution
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 19 Dynamic performance Dynamic performance indicates the ratio between signal and noise or distortion. We should use the suitable terms depending upon the type of application. F c =40MHz, f in =4MHz SFDR=49.8dB SNDR=44.9dB, ENOB=7.17-bit 2ndHD=-49.8dB, 3rdHD=-56.7dB
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 20 Sampling jitter effect Sampling jitter is converted to noise. When the input frequency becomes higher, the SNR becomes lower. Time Input signal t0t0 t
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 21 ENOB (bit) Input frequency (MHz) 300200100 3 4 5 6 SNR SNDR Effective Resolution Bandwidth 3dB (0.5bit) down ERB ERB is the input frequency where the SNDR has dropped 3dB (or ENOB 0.5 bit)
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 22 Glitch I/2 I/4 I/8 I/16 I/2 I/4 I/8 I/16 I/2 I/4 I/8 I/16 State 1: [1000]=8 State 2: [0111]=7 Intermediate: [1111]=15 8 15 7 Current Time Glitch Glitch is the spiky signal at code transition. Caused by overlapping of signals This appears within a few psec, However, energy is not negligible. Glitch causes the distortion of signal TgTg XgXg
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 23 Figure Of Merit 1995-2006 10b 12b Figure of merit shows energy efficiency for data conversion.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 24 Performance and application 6810121416 Resolution (bits) Conversion Rate (MHz) 0.1 1 10 100 1000 5 30 50 300 500 0.5 0.05 HDD/DVD Graphics Audio General Purpose DVC/DSC/Printer Video/ Communication Servo (-Computer) Automobile Meter Needed resolution and conversion rate depending upon the application.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 25 Needed SNR for certain BER in wireless system Q I 16QAM 10 BER Noise distribution Lower Bit Error Rate in the digital modulation needs higher SNR. n-PSK n-QAM 16QAM 64QAM 256QAM QPSK
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 26 BER requirement DAC requirement for QAMADC requirement for digital read-channel The lower the bit error rate the higher the required ADC/DAC resolution. Resolution (quantization noise) affects BER.
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  • 2006.06.14.VLSI symposia 2006, A. Matsuzawa, Tokyo Tech. 27 Signal intensity in wireless system Amp. ADC Filter ABC Thermal noise Thermal Noise + Quantization noise Wanted signal Adjacent signal Far signal Filter Frequency Intensity (dB) A BC Due to aliasing Due to distortion of ADC > Needed SNR > Needed dyn