A 15.5 dB, Wide Signal Swing, Dynamic Amplifier …...James Lin, Masaya Miyahara and Akira Matsuzawa...
Transcript of A 15.5 dB, Wide Signal Swing, Dynamic Amplifier …...James Lin, Masaya Miyahara and Akira Matsuzawa...
James Lin, Masaya Miyahara
and Akira Matsuzawa
Tokyo Institute of Technology, Japan
A 15.5 dB, Wide Signal Swing, Dynamic Amplifier Using a Common-Mode Voltage Detection Technique
Matsuzawa
& Okada LabMatsuzawa Lab.Tokyo Institute of Technology
Roadmap
• ITRS’s roadmap for future supply voltage [1]
• What are some foreseeable difficulties? [2]
3[1] ITRS, 2010
[2] A. Matsuzawa, ISSCC 2011 Forum
2010 2015 2020 2025
0.6
0.8
1.0
1.2
Year
Su
pp
ly v
olt
ag
e (
V)
Conventional Amplifier
• Amplifier design becomes increasingly
difficult with supply voltage lowering
4
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.30.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Ou
tpu
t v
olt
ag
e s
win
g (
VP
-P)
Supply voltage (V)
Conventional Signal Swing and Linearity
5
• Stacked architecture limits signal swing
Veff = VGS-VT[3] B. Razavi, McGraw-Hill
VINP VINN
VDD
Vb
VOUTN VOUTPRL RL
VDD (1.2 V)
Gnd
0.3 V (Veffn)
PMOS
2 X NMOS
Bias Voltage
Maximum
Voltage Swing
0.15 V (Veffp)
0.375 V
0.375 V
6
Motivation
• Ultra low voltage operation (0.5 V)
– Minimally stacked architecture
• Scalable power dissipation with speed
– Dynamic operation for mixed-signal
applications
• Dynamic amplifier A minimally stacked
amplifier with variable power consumption
is proposed
Conventional Applications
• Conventional applications:
– Pre-amplifiers for dynamic comparators [4]
– Receiver amplifiers for DRAM circuits [5]
7[4] B. Razavi, IEEE Press
[5] H. Fujisawa et al., ESSCIRC 2000
VINP VINN
CLK
CLK
V1
V2 Latches
VOUTP
VOUTN
VDD
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge V2
V1Clock
Proposed Waveform
8
• If discharging can be terminated
A single stage amplifier can be realized
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge
V2
V1
Clock
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge
V2
V1
Clock
Voc
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge
V2
V1Clock
Voc
VO
UT
VO
UT
Proposed Architecture
9
• A common-mode voltage detector with sampling
switches realize dynamic amplification
VINP VINN
CLK
VDD
V2V1
CL
M1
M2
M4M3
M5 M6
ID2ID1
CLK
CL
Common-
Mode Voltage
Detector
Signal Swing and Linearity
10
Co
nve
nti
on
al
@ 1
.2 V
Pro
po
se
d
@ 1
.2 V
Co
nve
nti
on
al
@ 0
.5 V
Pro
po
se
d
@ 0
.5 V
• Minimally stacked architecture gives extra
margin for signal swing
Drain-Source Voltage, VDS
Dra
in-S
ou
rce
Cu
rre
nt,
ID
S
VDD (0.5 V)
Linear
RegionSaturation Region
2 X Veffn
0.3 V
Veffp
0.15 V
0.05
V
Drain-Source Voltage, VDS
Voc
Linear
RegionSaturation Region
0.3 VD
rain
-So
urc
e C
urr
en
t, I
DS
VDD (0.5 V)
Veffn
0.15 V
Drain-Source Voltage, VDS
Dra
in-S
ou
rce
Cu
rre
nt,
ID
S
Vb VDD (1.2 V)
Linear
RegionSaturation Region
Maximum
Voltage Swing
0.75 V2 X Veffn
0.3 V
Veffp
0.15 V
Drain-Source Voltage, VDS
Voc VDD (1.2 V)
Linear
RegionSaturation Region
Maximum
Voltage Swing
1 VVeffn
0.15 V
Dra
in-S
ou
rce
Cu
rre
nt,
ID
S
0.0 0.2 0.4 0.6 0.8 1.00
1
2
3
4
5
6
Ga
in (
V/V
)
VDD
-Voc
(V)
CL=50 fF
CL=100 fF
CL=150 fF
CL=200 fF
Gain
11
Clipping DD oc
diff
eff
2 V -VG =
V
Gdiff: differential gain
VDD: supply voltage
Voc: common-mode (CM)
output voltage
Veff: effective gate voltage,
which is gate-source
voltage minus
threshold voltage
VDD = 1.2 V
Veff = VDD/2 - Vthn
Signal Swing and Linearity
12
• Wider signal swing, especially in low
voltage operation
fs = 50 MHz
Vic = VDD/2
-1 0 1-6
-4
-2
0
2
4
6
8
10
12
14
16
18
Ga
in (
dB
)
Output voltage (V)
Proposed, 1.2 V
Conv., 1.2 V
Proposed, 0.7 V
Conv., 0.7 V
Proposed, 0.5 V
Conv., 0.5 V
Gain
(d
B)
Output voltage (V)
Speed
• Key applications: Mixed-signal circuits
13
DCM
S
DD oc L P2
If =
V -V C +C
Vic = VDD/2 Vid = 0.1 V
100M 1G 10G7
8
9
10
11
12
13
14151617
Ga
in (
dB
)
Frequency (Hz)
CL = 50 fF (1.2 V)
CL = 100 fF (1.2 V)
CL = 150 fF (1.2 V)
CL = 200 fF (1.2 V)
CL = 100 fF (0.5 V) fS: operating/clock
frequency
IDCM: CM drain current
CL: load capacitance
CP: parasitic
capacitance
Vid: diff.-mode (DM)
input voltage
Vic: CM input voltage
10M 100M 1G
1E-3
0.01
0.1
1
Po
we
r d
iss
ipa
tio
n (
mW
)
Frequency (Hz)
Conv. (1.2 V)
Conv. (0.7 V)
Proposed (1.2 V)
Proposed (0
.5 V)Proposed (0.7 V)
Power Dissipation
• Scalable power dissipation due to
dynamic operation
14
P (f ) =
P (f )+ P (f )
T S
Amp S CMD S
Incomplete amplification
PT: total power
dissipation
PAmp: power dissipation
in amplifier circuit
PCMD: power dissipation
in logic circuit
Power Dissipation, cont’d
15
2P = f C V
P =
ΔVC +C f ΔV V -
CMD S L2 DD
Amp
L P1 S DD 22
Pre-charge
Phase
Amplification
Phase
Time
Vo
lta
ge
Voc
Clock
VDD
CL+CP1
Voc
VDDΦ1 Φ2
CP1: parasitic capacitance
CL2: common-mode detector’s
load capacitance
ΔV: VDD-Voc
• A dynamic amplifier
can save energy
• Delay causes a gain error and a CM
output voltage shiftc
Effects of Delay
16
t
I - IV = V -V
I
+I - I
C
D1 D2OUT DD oc
D1 D2
L
DCM
d
0.0 100.0p 200.0p 300.0p 400.0p-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Vo
lta
ge
(V
)
Time (s)
Clock
VOUT1
VOUT2Δt
t1 t2
Voc shift
• Parasitic capacitance causes a common-
voltage error
Circuit Implementation
17
1 2X
PX
0
PXDD
0 PX
1
21
2
2
V +VV =
C+
C
C + V
C +C
C0: common-mode detector’s
sampling capacitor
CPX: parasitic capacitance at node X
VINP VINN
VOUTPVOUTN
CLK
CLK
VDD
VX V2V1C0 C0
CLCL
M1
M2
M4M3
M5 M7 M6
CPX
• Capacitor mismatch causes a gain error
Sampling Capacitor Mismatch
18
V = V = V = V
Q = C V
1 2 X DD
X PX DD
Pre-charge phase:
Amplification phase:
'Q = Q
C V +C V +V - V -VV =
C +C
V +V CV = + V -
C C +C+
C
ΔC
V -VΔC
C +C
X X
PX DD 0 1 2 1 2
X
0 PX
1 2 PXX DD
PX 0 PX
1 2
0 PX
0
2
2 2
2
1
2 21
2
C0+ΔC/2
CPX
VXV1 V2
C0-ΔC/2
• 5.59 mV (s 1.27 mV (s
Mismatch Calibration
19
DAC
DAC
VINP VINN
VOUTPVOUTN
VC
inv_b
CLK
CLK
inv_b
VDD
VX V2V1C0 C0
CLCL
Co
un
ter
M1
M2
M4M3
M8 M9
M5 M7 M6
0 20 40 60 80-20
-15
-10
-5
0
5
10
15
20
Inp
ut-
refe
rre
d o
ffs
et
vo
lta
ge
(m
V)
Number
Uncalibrated
Calibrated
• 3 dB gain control
Gain Control
20
DAC
DAC
VINP VINN
VOUTPVOUTN
VC
inv_b
CLK
CLK
inv_b
VDD
VX V2V1C0 C0
CLCL
Co
un
ter
M1
M2
M4M3
M8 M9
M5 M7 M6
0.4 0.6 0.8 1.0 1.210
11
12
13
14
15
Ga
in (
dB
)
Bias voltage for gain control, Vc (V)
Conclusion
• A dynamic amplifier realizes
– 0.5 V ultra low voltage operation
– Wider signal swing
– Variable power dissipation for clock scalable
circuits
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0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.30.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Ou
tpu
t v
olt
ag
e s
win
g (
VP
-P)
Supply voltage (V)
Dynamic am
plifier
Conv. am
plifier
0.5 VP-P
Future Work
• Low-voltage ADC using dynamic
amplifiers
• Other RF applications such as
sampling mixers
22
References
[1] International Technology Roadmap for Semiconductors,
“2010 update – RF and analog mixed-signal CMOS
technology requirements,” Dec. 2009.
[2] A. Matsuzawa, “An ultra low power analog and ADC
design,” ISSCC Forum, Feb. 2011.
[3]B. Razavi, “Design of analog CMOS integrated circuits,”
McGraw-Hill, 2001.
[4]B. Razavi, “Principle of data conversion system design,”
IEEE Press, 1994.
[5]H. Fujisawa, T. Takahashi, M. Nakamura, and K. Kajigaya,
“A dual phase-controlled dynamic latched (DDL) amplifier
for high-speed and low-power DRAMs,” Proc. 26th Eur.
Solid-State Circuits Conf., pp. 184-187, Sept. 2000.
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