1.`Motivation for SoC Design _by Raveendra Somana

7/27/2019 1.`Motivation for SoC Design _by Raveendra Somana

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Motivation for soc

The Lives and the Death of Moore’s Law:

In 1965, Gordon Moore, Director of Fairchild Semiconductor’s Research and

Development Laboratories, wrote an article on the future development of semiconductorindustry for the 35th anniversary issue of the Electronics magazine. In the article, Moore

noted that the complexity of minimum cost semiconductor components had doubled per

year since the first prototype microchip was produced in 1959. This exponential increase in

the number of components on a chip became later known as Moore’s Law. In the 1980s,

Moore’s Law started to be described as the doubling of number of transistors on a chip

every 18 months. At the beginning of the 1990s, Moore’s Law became commonly

interpreted as the doubling of microprocessorpower every 18 months. In the 1990s,

Moore’s Law became widely associated with the claim that computing power at fixed cost is

doubling ever y 18 months.

Moore’s Law has mainly been used to highlight the rapid change in information

processing technologies. The growth in chip complexity and fast reduction in manufacturing

costs have meant that technological advances have become important factors in economic,

organizational, and social change. In f act, during the last decades a good first approximation

for long-range planning has often been that information processing capacity is essentially

free and technical possibilities are unlimited.

Regular doubling means exponential growth. Exponential growth, however, also

means that the fundamental physical limits of microelectronics are approaching rapidly.

Several observers have therefore speculated about the possibility of “the end of Moore’s

Law.” Often these speculations have concluded by noting that Moore’s Law will probably bevalid for at least “a few more generations of technology,” or about a decade. An important

example is the International Technology Roadmap for Semiconductors (ITRS), which now ex

tends to 2016. This roadmap is generated by a global group of experts and represents their

consensus. Although it notes that within the next 10-15 years “most of the known

technological capabilities will approach or have reached their limits,” its basic assumption is

that Moore’s Law, although perhaps slowing down, still provides a good basis for predicting

future developments in the semiconductor industry (ITRS, 2001).

Of course, if Moore’s Law is valid, independent of the exact nature of physical limits,

exponential development means that the limits are only a few technological generations

ahead. Order of magnitude errors in our current estimates of the ultimate limits of chip

technology will create at most a few months of error in the time when they become

bottlenecks in chip technology. As a result, it is easy to predict that Moore’s Law will

become invalid soon. Speculations on the extended lifetime of Moore’s Law are therefore

often centered on quantum computing, bio-computing, DNA computers, and other

theoretically possible information processing mechanisms. Such extensions, obviously,

extend beyond semiconductor industry and the domain of Moore’s Law. Indeed, it could be

difficult to define a “component” or a “chip” in those future devices.

Motivation for SoC Design




Future of Moore’s Law:

It is becoming clear that SOC presents major technical, financial, business, and

legalchallenges that are forcing industry and academic researchers to consider other

optionsfor semiconductors and systems. For the first time, industry may not invest in

extendingMoore’s law beyond 2015. This is leading the industry to explore alternative ways

toachieve systems integration wherein semiconductor integration is pursued, not

onlyhorizontally by SOC, but also vertically by SIP via 3D stacking of bare or packaged ICsand

by SOP. More than 50 companies are pursuing SIP.The SIP allows Moore ’s law to continue,

not in two dimensions as in the past, but in three dimensions

In parallel, the computing industry has been following Moore’s Law where the

number of transistors on the IC has continued to double every 18 months for the last 15years.However, the scaling beyond the 90-nm node is causing significant challenges

associated with leakage and latency causing engineers to develop new architectures. With

the trend toward multicore processors and the need for significant memory contentwith

reduced latency in systems, the package is becoming more critical for the functioning of the

system. The package now has to support high-speed I/Os containing serial and parallel links

with speeds in excess of 3 Gbytes per second (Gbytes/s). With the convergence of

computing and communication capabilities, the need for integrating the high-speed

microprocessor, memory, and wireless ICs in a single package, with the antenna and RF

front-end passives integrated in the package, is becoming very critical.

In recent years, the growing fear that Moore ’s law will slow or collapse with theever-

shrinking dimensions and ever-increasing die size, coupled with the unceasingdemand for

low-cost microminiaturized devices, such as the iPhone, have led to theconcept of system-

on-package (SOP), where the system board and IC package becomeone and the same. This

so-called second law of electronics is expected to enable theelectronic devices to achieve

unprecedented functionality and miniaturization atreduced cost.

Benefits of System-on-Chip:

1. Cost:

While it is obvious that a customer cares for lower cost, it is important tonote thatthe cost applies to the bill of materials (BOM) of the entire system, asopposed to the cost of

the SOC chip alone. For example, consider two scenariosfor a system that performs a data-

intensive application such as video and imageprocessing and hence is built with an SOC and

a large amount of off-chipmemory. In one case, the external memory interface of the SOC

needs to operateat 100 MHz, as opposed to 133 MHz in the other case, to be able to

achieve thedesired system throughput. The SOC that operates with a 100-MHz interfacewill

need to employ microarchitectural options such as a wider interface (64 bitversus 32 bit) or

a higher on-chip memory, which can result in a higher SOC cost. However, at a system level,

a 100-MHz interface allows the use of memorieswith a lower speed grade, which are

significantly cheaper than the memoriesrequired to interface with a 133-MHz interface.Thus at a system level, thesolution that uses a marginally expensive SOC can turn out to be




more costefficient. Later in this chapter we will discuss how such system- and

boardlevelconsiderations can be comprehended during the SOC definition phase.

2. Power Dissipation

Power dissipation is increasingly becoming a key concernfor portable devices such as

mobile phones, personal digital assistants (PDAs),digital still cameras, and MP3 playersbecause lower power translates to longerbattery life. As mobile phones move from second

generation (2G) to 2.5G to 3G,the computing requirements are increasing at a rapid

pace,and with that thedynamic and switching power dissipation is also increasing. Battery

technologyis progressing in terms of energy per dollar, energy per weight, energy

pervolume, and so forth, but at a relatively slower pace. This is making low poweran

increasingly important requirement. While deep submicron CMOS technologyenables the

performance and level of integration required for the 3Gapplication, with each new process

technology node, the leakage power isalso increasing significantly. Since this impacts the

standby time, animportant consideration for these mobile applications, SOC designers

needto employ aggressive power management techniques to reduce leakagepower

dissipation.

Power dissipation in the “standby mode” is an important requirement forautomotive

applications as well, where a small component of the system needsto be running

continuously even when the car is switched off.

In case of infrastructure devices such as wireless base stations, DSL centraloffices,

and Cable Modem Termination Systems (CMTS), the system employsarrays of SOCs to be

able to support thousands of communication channels.The power per channel is hence an

important metric for these applications.While performance is the key optimization vector

for these infrastructure devices, the performance needs to be pushed while taking the

power constraintsinto consideration.

3.Programmability and performance headroom In applications where the same devices perform different functions (for example,

multifunction devices that operate as a printer-scanner-copier-fax), programmability

enables the same hardware to be used to efficiently implement these different functions.

Programmability is also required for applications that need to support multiple standards

such as, for example, in the video domain where in addition to MPEG2, MPEG4, H.263,

there are applications that use proprietary standards as well. For applications where the

standards are evolving, programmability isagain very valuable as the standards can be

supported primarilythroughsoftware upgrades. The programmability also allowscustomization, differentiation, and value-added capabilities over the baseline functionality

of thesystem. This customization hence demands the appropriate performanceheadroom to

be able to provide additional capabilities while still meeting theperformance requirements

of the base functionality. While the programmabilityis primarily supported by embedding

programmable processor cores into thesystem, hardware programmability is also feasible

using field programmablegate array (FPGA) technology.

FIVE MAJOR SYSTEM TECHNOLOGIES:

The five major system technologies for electronic digital convergence are1. System-on-board (SOB).Discrete components interconnected on system boards.




2. System-on-chip (SOC). Partial system on a single IC with two or morefunctions.

3. Multichip module (MCM). Package-enabled horizontal or 2D integration of two or more

ICs for high electrical system performance.

4. Stacked ICs and packages (SIP).Package-enabled 3D stacking of two or more thinned ICs

for system miniaturization.

5. System-on-package (SOP).Best IC and system integration for ultra-miniaturization,Multiple to mega functions, ultrahigh performance, low cost, and high

reliability.

Fig. 1: Historical evolution of the five system technologies over the past 50 years.

System-on-board (SOB):

The current approach to manufacturing systems involves fabricating the

componentsseparately and assembling them onto system boards. The strategy to

miniaturize the systems in this traditional approach has beento reduce the size of each

component by reducing the input-output (I/O) pitch, wiring,and insulation dimensions in

each of the layers. But this approach presents majorlimitations to achieving digital

convergence. The IC packaging thatis used to provide I/O connections from the chip to the

rest of the system is typicallybulky and costly, limiting both the performance and the

reliability of the IC it packages.Systems packaging, involving the interconnection of

components on a system-levelboard, is similarly bulky and costly with poor electrical andmechanical performance.




System-on-chip (SOC):

Semiconductors have been the backbone of the IT industry, typically governedbyMoore’s law. Since the invention of the transistor, microelectronics technology

hasimpacted every aspect of human life by electronic products in the automotive,computer,

telecommunication, aerospace, military, and medical industries by ever higherintegration of

transistors, and at an ever-lowercost pertransistor. This integration and cost path has led

the microelectronics industry to believethat thiskind of progress can go on forever, leading

to a “system-on-a-chip” for allapplications to form completeend-product systems.

Multichip module (MCM): The MCM (Shown in below Figure) was invented back in the 1980s at IBM, Fujitsu,

NEC, and Hitachi forthe sole purpose of interconnecting dozens of good bare ICs to produce

a substrate waferthat looked like the original wafer, since larger chips could not be

produced with anyacceptable yields on the original silicon wafer. These original MCMs were

horizontal or twodimensional.They started with so-called hightemperature cofired ceramics

(HTCCs)multilayer ceramics, such as alumina, metallized andinterconnected with dozens of

layersof either cofired molybdenum or tungsten. These then were replaced with higher-

performanceceramic MCMs called low-temperature cofired ceramics (LTCCs)made of lower-

dielectricconstantceramics such as glass-ceramics, metallized with better electrical




conductors such ascopper, gold, or silver-palladium. The third generation of MCMs

improved further withadd-on multilayer organic dielectrics and conductors of much lower

dielectric constant andsputtered or electroplated copper with better electrical conductivity.

Stacked ICs and packages (SIP): Here, SIP is defined as a vertical stacking of similar or dissimilar ICs, in contrast to

thehorizontal nature of SOC, which overcomes some of the above SOC limitations, such as

latency, if the size of the chips andtheir thicknesses used in stacking are small. SIP is

alsodefined often as the entire system-in-a-package. If all the system components (forexample,passive components, interconnections, connectors, and thermal structures such as

heatsinks and thermal interface materials), power sources, and system board are

miniaturizedand integrated into a complete system as SOP, then there is nodifference

between SIP and SOP.

But there is one major issue with this approach. The SIP, defined above as stacking

ofICs, includes only the IC integration and hence addresses only about 10 to 20 percent

ofthe system by extending Moore’s law in the third dimension. If all the ICs in the stack

arelimited to CMOS IC processing, the end-product system is limited by what it can

achieveonly with CMOS processing at or below Nano scale. The above fundamental and

integrationbarriers of SOC, therefore, remain. There are clear major benefits, however, to

SIP: simplerdesign and design verification, a process with minimal mask steps, minimal time-

to market,and minimal Intellectual Property (IP) issues.System-on-package (SOP):

If, in fact, the system components such as batteries, packages, boards, thermal

structures,and interconnections are miniaturized as described above with Nano scale

materials andstructures, this should lead to the second law of electronics. The SOP achieves

true system integration, not justwith the best IC integration as in the past but also with the

best system integration. Assuch, it addresses then the 80 to 90 per cent of the system

problems that had not beenaddressed, as described earlier. In contrast to IC integration by

Moore’s law, measuredin transistors per cubic centimetre, the SOP-based second law

addresses the systemintegration challenges as measured in functions or components per

cubic centimetre.




Comparison of SOB, SOC &SOP Technologies:

The below figure3alists the system drivers as being miniaturization,

electricalperformance, power usage, thermal performance, reliability, development

andmanufacturing cost, time-to-market, and flexibility.

Figure3bcompares each of the above system Technologies against the

sameparameters, showing the strengths and weaknesses of each of the technologies.

The SOC is a clear technology leader in electrical performance and power usage,and

while it is a miniaturization leader at the IC level, it is not a leader at the systemlevel, as can

be seen in below Figure. This is due to the fact that the system technologiessuch as power

supplies and thermal structures are not miniaturized. The highdevelopment cost, longer

time-to-market, and limited flexibility are its major weaknesses.In addition, complete

integration of RF, digital, and optical technologies on a singlechip poses

numerouschallenges. RF circuit performance, for example, is a trade-offbetween the quality

factor (Q) of passive components (inductors and capacitors) andpower.

Low-power circuit implementations for mobile applications require high-Qpassive

components. In standard silicon technologies, the Q factor is limited to about 25due to the

inherent losses of silicon and large area usage beyond traditional digitalCMOS dimensions.

This can be improved by using esoteric technologies such as thickoxides, high-resistivity Si,

SiGe, or gallium arsenide (GA As), which increase the costsubstantially. In addition, these

passive components consume valuable real estate andoccupy more than 50 percent of the

silicon area.




Fig 3a: System Drivers

Fig 3b: System Technologies with respect to System Drivers

The SOB, on the other hand, shows its strengths in those areas where SOC is

weakbut suffers in those areas such as electrical performance and power usage where

SOCshines. The SIP is a good trade-off between these two technologies, and at the

sametime it is at the heart of semiconductor companies and their need to manufactureasmuch silicon as possible to justify their wafer fabrication investments. In addition,the SIP




addresses the wireless cell phone “sweet spot” application. Therefore, it isnot surprising

that almost all major IC companies are manufacturing these modules.The major weakness

of SIP is that it addresses the system drivers at the module levelonly and not at a system

level. The 80 to 90 per cent of the system problems remainsunanswered.

The SOP is an even better and more optimized system solution than SIP, as can

beseen from Figure 3b. It addresses at the IC level without compromise by means ofbothon-chip SOC integration and package-enabled SIP and 3D integration and at the

systemlevel by system miniaturization technologies such as power supplies, thermal

structures,and passive components, as indicated previously in Figures 1.5 and 1.9b for

digital, RF,optical, and sensor components. Unlike SOC, however, no performance

compromiseshave to be made in order to integrate these disparate technologies since each

technologyis separately fabricated either in the IC or the package and subsequently

integrated intothe SOP system package. System design times are expected to be much

shorter in theSOP concept, as it allows for greater flexibility with which to take advantage of

emergingtechnologies.Nevertheless, SOP must successfully overcome a different set of

challenges,namely infrastructure and investment challenges.

Comparison Between SOB, SOC &SOP

System Drivers SOB SOC SOP

Flexibility Highly flexible Very low Moderate

Thermal dissipation More Less Very less

System Reliability Very poor Good Very good

Performance Very low High High

Power consumption More Less Less

Size Big Small Small

Manufacturing cost low More Very low

Time to market Less More Less

Scaling:Process technology is linearly shrinking at approximately 70 per cent per generation.

This enables the implementation of a logic function in half the die area compared to the

previous technology node, hence lowering the cost.

While every advanced process technology node provides the 70 per cent linear

shrink, the bond pad pitch (for wire-bond packaging) and bump pitch (for flip-chip

packaging) have not scaled accordingly. In addition, I/Os and analog components do not

shrink as much as the standard logic. These factors need to be taken into consideration

when assessing the cost benefit of moving to a new technology node. Every new processnode comes with an increased reticle cost and increased fabrication cycle time. The wafer




manufacturing cost depends on several factors such as the cost of capital involved in the

procurement of steppers and scanners and the cost of the process material and fabrication

facilities. Wafer throughput also impacts the manufacturing cost, and this throughput is

directly dependent on the number and size of the “steps” printed on the wafer. Typically, a

130-nm mask set can cost around US$750,000, while the 90-nm mask set costs over 1

million U.S. dollars.As indicated in Figure 4a, technology scaling has resulted in finer geometry sizes,

which in turn has caused an increased resistance in both wires and vias. The number of

metal layers that are supported in current technology nodes has also increased the cross-

coupling capacitance to ground capacitance ratio. Lower device thresholds have caused

lower noise margins.

Fig 4a: Aspect ratio & Pitch

Leakage power continues to dominate newer process nodes such as 90, 65,and45

nm, as shown in Figure 4b. This is primarily due to the source-to-drain leakagecurrent that

increases with a lowering of the threshold voltage (Vt), increasingtemperature, and shorter

transistor channel lengths. Also, with gate oxide thicknessesdecreasing at such newer

process nodes, the voltages across the gate must be reducedto keep the electric fields from

becoming too high for the insulating material. Both alower Vt and gate oxidethicknessexponentially increase the transistor leakage current.

New design techniques have come on the horizon to tackle the leakage power

issue.Several power management techniques are being integrated on the SOC to

handleleakage power. One of the most common approaches to address leakage power is

theuse of multi-Vt libraries that most Application Specific Integrated Circuit (ASIC)

vendorsprovide today at 130 nm and below.

Fig 4b: Power Consumption




The increasing levels of component integration would not have been

possiblewithout technology scaling that has enabled a reduction in transistor size,

allowingmore of them to be integrated into the same area with each passing

technologygeneration. However, these technological advances that have ushered

theindustry into the deep submicron(DSM) era, with the on-going commercializationof the90 and 65 nm processes, have introduced new challenges for on-chip

communicationarchitecture design.

Precise control of the fabrication process in DSM technologies is almost impossible.

Leading to process uncertainties that cause non-uniformity of sheet resistance and

an increase in coupling noise between adjacent wires in buses.

Decreasing wire pitch and increasing aspect ratio with technological advances

further accelerates these issues.

The end result of these factors is that signal propagation delay on wires (i.e.,

interconnect delay) is increasing with each technology generation, which puts a limit on thecommunication performance.

According to the International Technology Roadmap for Semiconductors(ITRS) 2005

predictions (Fig 4c), the gap between interconnection delay andgate delay will increase to

9:1 at the 65 nm technology. This is in sharp contrast tothe 2:1 gap between

interconnection delay and gate delay at the 180 nm technology.

Fig 4c:Relative delay comparison of wires vs. process technology




Design Productivity Gap:Design productivity lags the design complexity improvements made possible by

thetechnological evolution. The Figure belowshows the design productivity gap.

The gate complexity is shown in Logic transistors/chip and the design productivity is

shown in Transistors/staff month.

The increasing complexity of ICs poses challenges to both system design

engineersand verification engineers. This productivity gap cannot be addressed by

simplythrowing more engineers at the problem. For one thing, there are not enough

qualifiedengineers to solve the problem and, even if there were, there are practicallimitationson how large adesign team can grow. As design teams grow, so does thelevel of

coordination required to keep everyone in sync. Instead, new methodologiesthat make the

design process more productive are required.

Solution:

The industry has responded to this challenge by adopting design reuse strategies.By

utilizing pre-existing blocks (also known as intellectual property (IP) blocks orvirtual

components (VC)), the amount of original design work required to realize anew design is

reduced. With platform-based design, design reuse goes beyond reusingindividual blocks. In

platform-based design, a set of core elements that are commonacross a family of productsis identified, integrated, and verified as a singleentity. The actual products are then realized

by adding individual design elementsto this core. The individual elements can be either

additional IP blocks or newlyauthored elements. This concept of design reuse not only

reduces the design effort,but also significantly reduces the verification effort in realizing a

new design.

SOC Intellectual Property (IP):One of the most critical components of SOC design is the integration of

predevelopedpieces of functionality called intellectual property (IP). These IP blocks can

offer a hugedifferentiation to designers building SOC designs for various applications andhelpsreduce development cycle-time significantly. However, while attempting to




integratesuchmultiple IPs, the SOC designer is faced with tremendous challenges

inunderstanding thesepredefined functional IPs as well as coping with the issues thatneed

to be dealt with ingetting these IPs to talk to the rest of their SOC and in verifyingthe whole

systemthereafter. Complicating the problem is the reality that IP developersand SOC

designers aregeographically distributed across the world. This can, veryoften, offset the

advantage ofreducing development cycle-time that the reuse itselfbrings in. Severalinitiatives have beenstarted in the industry today to tackle this majorIP reuse issue. One

such industryconsortium called the Virtual Socket Interface Alliance(VSIA) was founded in

September1996 with an attempt to bring together IP [also calledvirtual components (VC) by

thisconsortium] developers and SOC houses to worktogether to define standards for

designand integration of reusable IP. Several IP-centricbus definitions and interconnect

strategieshave been suggested to make IP reuse asseamless as possible for the SOC

designer. A VCquality checklist was also developedby this consortium to quantify the

“readiness” of thesecomponents for reuse. Thisfocused on qualifying an IP from both a

developer’s perspectiveas well as from anintegrator perspective and incorporating as many

best practices aspossible. Another consortium that was launched at the Design Automation

Conference 2004was theStructure for Packaging, Integrating, and Re-using IP with Tool-

flows (SPIRIT) tocovera Register Transfer Level (RTL) encapsulation for automated IP

integration andinteroperability of IP with multiple toolsets. This included tools for system-

level design,verification, and simulation as well as synthesis.

IP cores or blocks can be integrated in three variants on an SOC:

• Hard.These blocks are physical design completed and optimized at a particularprocess

node. As a result, while these blocks can differentiate in terms of speed,power, and area,

they are the least flexible and portable across technology nodesand SOC designs, given that

their physical attributes such as size and aspectratiocannot change.

• Soft.These blocks are reused as a register transfer –level representation of the IPalong with

the necessary synthesizable constraints and test benches toimplement and verify these

blocks in the SOC context. In contrast to hardblocks, these IP components have the most

flexibility and portability acrossSOC designs and are amenable to in-context physical

optimization for best SOCpower-speed-area parameters.

• Firm.This type of IP reuse combines the best advantages of both the above tworeuse

scenarios where the IP is optimized for power-speed-area cares aboutacross process nodes.

However, given that the physical layout is uncommitted,the IP is configurable to

various“use” scenarios.

References: 1) Rao R. Tummala, MadhavanSwaminathan,“Introduction to System-on-Package (SOP)

Miniaturization of the Entire System” Copyright © 2008 by The McGraw-Hill

Companies.

2) SudeepPasricha and NikilDutt,”On-Chip Communication Architectures: System on Chip

Interconnect”, Morgan Kaufmann Publishers © 2008.

3) PrakashRashinkar, Peter Paterson and Leena Singh “System – on – a - Chip Verification –

Methodology and Techniques”, Kulwer Publishers, 2001.

4) “The Lives and the Death of Moore’s Law” Ilkkatuomi.

1.`Motivation for SoC Design _by Raveendra Somana

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