14th International Conference

MIXED DESIGN

MIXDES 2007Ciechocinek, POLAND21 23 June 2007

TRADEOFFS AND OPTIMIZATION IN ANALOG CMOS DESIGN

D. M. BINKLEYTHE UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE, USA

KEYWORDS: Analog CMOS, MOS design, Tradeoffs, Optimization, Weak, moderate, strong inversion, Inversion coefficient, Channel length, Sizing, Transconductance efficiency,Early voltage, Gain, Bandwidth, Distortion, Thermal noise, Flicker noise, Mismatch, Operational transconductance amplifier, EKV MOS model

ABSTRACT: The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numericalmeasure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimumdesign. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization ofperformance are illustrated by the design of three, 0.18-m CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, outputresistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.

INTRODUCTION

Analog CMOS design is complicated by three degrees of design freedom present for every MOS device operating in the usual saturation region. Traditionally, these degrees of design freedom have been drain current, channel width, and channel length. However, selecting drain current, inversion coefficient [1], and channel length provides better design insight leading towards optimized design, where channel width is easily calculated for layout. This is because the inversion coefficient provides a numerical representation of the region and level of MOS inversion, permitting design freely in weak, moderate, and strong inversion. Design in moderate inversion is increasingly important for modern, low-voltage processes because of high transconductance efficiency, moderate intrinsic bandwidth, low drain-source saturation voltage, and good immunity to velocity saturation effects. This paper begins by illustrating some of the many tradeoffs in MOS device performance. This is done using simple hand expressions motivated by the EKV MOS model [2 4], and measured data in weak, moderate, and strong inversion over a wide range of channel length. Tradeoffs in performance are then illustrated by the design of three, cascoded operational transconductance amplifiers (OTAs) optimized for DC, balanced, and AC performance. The optimization of these OTAs is facilitated by a spreadsheet design tool where MOS device performance is explored over drain current, inversion coefficient, and channel length choices and mapped into complete circuit performance. The OTAs are fabricated in 0.18-mCMOS technology and experimentally evaluated. Although the tradeoff and optimization methods described do not offer the accuracy of computer

simulations using production MOS models, predicted circuit performance, including flicker noise and input-referred offset voltage, is in sufficient agreement with measurements to provide useful design guidance. The intention of the methods and spreadsheet design tool is to provide design intuition that rapidly guides the designer towards optimum tradeoffs in gain, bandwidth, distortion, thermal noise, flicker noise, DC voltage and current mismatch, and other measures of analog performance.

EXAMPLE CMOS PROCESS

Tradeoffs in MOS device performance and the optimization of OTAs are illustrated here for a typical, 0.18-m, bulk CMOS process. Table 1 defines and lists nominal process parameters for this process at room temperature (T = 300 K). Although this is used as an example process, the technology normalization inherent in the MOS inversion coefficient readily enables design optimization in smaller-geometry processes.

MOS DRAIN CURRENT, SUBSTRATE FACTOR, AND INVERSION COEFFICIENT

Table 2 gives an expression for MOS drain current, ID,from weak through strong inversion [2 - 4, p. 45]. W is the effective channel width, L is the effective channel length, VGS is the gate-source voltage, VT is the threshold voltage, and UT is the thermal voltage. The drain current converges to the exponential-law value of ID = 2nCOXUT2(W/L)exp[(VGS-VT)/(nUT)] in weak inversion and converges to the square-law value of ID = (1/2)(COX/n)(W/L)(VGS-VT)2 in strong inversion. Velocity saturation and vertical field mobility reduction (VFMR) decreases in mobility and drain current can be

Copyright 2007 by Department of Microelectronics & Computer Science, Technical University of Lodz 47

approximated through the expression modification described in the table [10]. This modification considers the decrease in drain current at high inversion (high VGS-VT) due primarily to velocity saturation for short-channel devices and VFMR for long-channel devices. The substrate factor, n, listed in Table 2 reduces the drain current and, correspondingly, transconductance in weak, moderate, and strong inversion because of the substrate, body, or back-gate effect [2 4, pp. 21-22, 9, 10]. In weak inversion, n is recognized as the weak-inversion slope factor. In strong inversion, n is related to the reduction of the channel pinch-off voltage and drain current due to body-effect along the MOS channel. n has a weak-inversion value of approximately 1.4 for typical bulk CMOS processes. It decreases slightly with increasing MOS inversion (increasing VGS-VT) and also decreases slightly with increasing source-body voltage, VSB.Table 2 also gives an expression for the fixed-normalized, inversion coefficient, referred to here as IC.This has a slightly different definition compared to the traditional inversion coefficient [1], which is equal to the normalized forward drain current in the EKV MOS model [2 4, pp. 40-44] and is related to the normalized forward drain current in a similar MOS model [5]. In the fixed-normalized inversion coefficient, unlike the traditional inversion coefficient [1], n is held fixed at is average moderate inversion value of n0 and is held fixed at its low-field value of 0 [6 - 10].

The fixed-normalized inversion coefficient permits a simple drain current normalization using a fixed technology current, I0, resulting in linear relationships between the drain current and MOS sizing [6 - 10]. The fixed-normalized and original inversion coefficients are nearly equal in weak and moderate inversion, but deviate in strong inversion due primarily to the decrease in . The effects of mobility reduction due to velocity saturation and VFMR are considered separately and outside the fixed-normalized inversion coefficient definition [10]. Although the fixed normalized inversion coefficient uses a fixed normalization current (I0), this must be corrected for temperature through the values of 0 and UT [8 - 10].

TRADEOFFS IN MOS PERFORMANCE VERSUS DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL LENGTH

Design using the inversion coefficient enables a conscious choice of the region and level of MOS inversion and facilitates optimum analog design. Weak inversion corresponds to IC < 0.1, moderate inversion corresponds to 0.1 < IC < 10, and strong inversion corresponds to IC > 10. Design expressions developed in terms of the inversion coefficient enable design and design optimization freely in all regions of inversion, including moderate inversion. As anticipated 25 years ago [11], moderate inversion is important for modern, low-voltage design because of high transconductance efficiency and low drain-source saturation voltage. Every MOS device operating in saturation (VDS > VDSAT)in an analog circuit operates at a selected drain current, inversion coefficient, and channel length. For a given drain current, the selected inversion coefficient and channel length corresponds to a point on the MOSFETOperating Plane shown in Fig. 1 [6-10]. This illustrates the significant tradeoffs in analog performance available to the designer. Some MOS performance tradeoffs are described below.

TABLE 1. Process parameters at room temperature for the example, 0.18-m CMOS process.

Process parameter nMOS pMOS Units Electrical gate-oxide

thickness, tox4.1 4.1 nm

Low-field mobility, 0 422 89.2 cm2/VsGate-oxide capacitance, COX 8.41 8.41 fF/m2Low-field transconductance

factor, k0 = 0COX355 75 A/V2

Body-effect factor, 0.56 0.61 V1/2Twice the Fermi potential,

PHI = 2F0.85 0.85 V

Average value of substrate factor, n0

1.35 1.35

Technology current, I0 0.64 0.135 AEarly voltage factor, VAL

(see Fig. 5) 3 - 34 3 - 34 V/m

Critical, velocity saturation electric field, ECRIT

5.6 14 V/m

Vertical field mobility reduction factor,

0.28 0.35 V-1

Low inversion, flicker noise factor, KF0

(6,700)2 (5,800)2 (nV)2m2

Voltage describing increase in flicker noise with VEFF, VKF

1 0.25 V

Threshold voltage mismatch factor, AVTO

5 5 mVm

Transconductance factor, mismatch factor, AKP

2 2 %m

Large geometry threshold voltage, VTO

+0.42 -0.42 V

Threshold voltage change with VDS (min. L)

-8 +10 mV/V

Lateral diffusion, DL(DW = 0 m)

0.028 0.051 m

TABLE 2. Expressions for MOS drain current, substrate factor, fixed-normalized inversion coefficient, and

technology current.

Expression

Drain current: )e1(ln2 222' TTGS

nUVV

TOXD LWUCnI

+

=

may be replaced by 0 divided by ( )

+CRIT

TGS

LE

VV1

to approximate velocity saturation and VFMR effects where (LECRIT) = LECRIT||(1/).

Substrate factor: ( ) SBTGS VnVVn +++= /21 0 ,

where 0 2F + 4UT 0.85 V + 0.1 V = 0.95 V.Inversion coefficient (fixed normalized):

=

LWI

IIC D

0

Technology current: 2'000 2 TOX UCnI =

48

Sizing

Table 3 gives expressions for the MOS shape factor, S = W/L, channel width, W, and gate area, WL, as a function of the drain current, inversion coefficient, and channel length [6-10]. Each of these sizing measures is inversely proportional to the selected inversion coefficient and is directly proportional to the selected drain current. Additionally, the channel width is proportional to the selected channel length, while the gate area is proportional to the square of the selected channel length. Gate area is proportional to the square of channel length because an increase in channel length requires an equal increase in channel width to maintain the selected drain current and inversion coefficient. This is significant because capacitances, flicker noise, and local-area mismatch depend on the gate area.

Effective Gate-Source Voltage and Drain-Source Saturation Voltage

Table 4 gives an expression for the effective gate-source voltage, VEFF = VGS-VT, which approaches VEFF = nUTln(IC) in weak inversion and VEFF = 2nUTIC in strong inversion [9, 10]. The table also gives the drain-source saturation voltage, VDSAT,which approaches VDSAT = 4UT in weak inversion and VDSAT = 2UTIC = VEFF/n in strong inversion [9, 10]. Both VEFF and VDSAT increase as the square-root of ICin strong inversion, complicating low-voltage design.

When velocity saturation is significant for short-channel devices operating in strong inversion at high IC, VEFF increases directly with IC as predicted by the modification described in the table [10]. When evaluated in terms of IC, VDSAT becomes a smaller fraction of the increasing VEFF and is thus relatively insensitive to velocity saturation effects [10].

Transconductance Efficiency

Table 4 gives expressions for the transconductance efficiency, gm/ID, where transconductance is found by gm = (gm/ID)ID. The first expression involving a single square-root term [3] predicts gm/ID with an accuracy of 4% from weak through strong inversion, while the second expression involving a double square-root term [2] predicts gm/ID with an accuracy of 2.5% [10]. Both expressions predict gm/ID = 1/(nUT) in weak inversion and gm/ID = 1/(nUTIC) in strong inversion. Fig. 2 shows measured and predicted gm/ID for nMOS devices in the 0.18-m CMOS described in Table 1.

TABLE 4. Expressions for MOS effective gate-source voltage, drain-source saturation voltage, transconductance

efficiency, and Early voltage.

ExpressionEffective gate-source voltage1:

== 1ln2 ICTTGSEFF enUVVV

Drain-source saturation voltage:

TTDSAT UICUV 325.02 ++=Transconductance efficiency2:

( )5.025.0115.0

11

++

++

==

ICnU

ICICnUVIg

T

TgmD

m

Early voltage: LVLICVV DSALA = ),,( , where gds = ID/VA and rds = VA/ID.

1Velocity saturation and VFMR effects can be approximated by replacing IC with IC = IC(1+IC/(4ICCRIT)).

2Velocity saturation and VFMR effects can be approximated by replacing IC with IC = IC(1+IC/ICCRIT). ICCRIT = [(LECRIT)/(4nUT)]2.

1

10

100

0.01 0.1 1 10 100Inversion Coefficient, IC

Tran

sco

ndu

cta

nc

e Ef

ficie

nc

y,

g m/ I D

( S

/ A)

W.I.1/[nU T ] S.I., no vel. sat. and VFMR,1/[nU T Sqrt(IC )]

W.I.

Measured

PredictedL (m)

0.180.280.48

14

nMOS 0.18 m processn = 1.33 (held fixed)E CRIT = 5.6 V/m = 0.28 V-1

S.I.M.I.

g m = (g m /I D )I D

Fig. 2. Predicted and measured transconductance efficiency for nMOS devices in a 0.18-m CMOS process. Copyright John

Wiley and Sons Limited. Reproduced with permission from [10].

Inversion Coefficient, IC

Best VA, rdsBest VA, rdsC

hann

el L

engt

h (L

)

Weak Moderate Strong (possible vel. sat. for short L)

Best VGS-VT (min.) VDSAT (min.) gm/ID, gm Thermal SVG (min.)

Best VGS-VT (min.) VDSAT (min.) gm/ID, gm Thermal SVG (min.)

0.1 1.0 10 100 1,000

Best Bandwidth, fTi C (min.) Layout area (min.)

Best DC gain, AVi DC mismatch (min.) Flicker SVG (min.) Flicker SID (min.)

Best DC gain, AVi DC mismatch (min.) Flicker SVG (min.) Flicker SID (min.)

Forf

ixed

IC,

W

L ,W

L

L2

For fixed L, W 1/IC

Best gm distortion (min.) Thermal SID (min.)

Best gm distortion (min.) Thermal SID (min.)

Fig. 1. The MOSFET operating plane illustrating tradeoffs in performance for the selected inversion coefficient and channel length. Copyright John Wiley and Sons Limited. Reproduced

with permission from [10].

TABLE 3. Expressions for MOS shape factor, channel width, and gate area.

Expression

Shape factor:

=

0

1II

ICLW D

Channel width:

=

0II

ICLW D

Gate area:

=

0

2

II

ICLWL D

49

Predicted gm/ID is found from the double square-root expression in Table 4 using the modification listed for velocity saturation and VFMR effects [10]. In this modification, ICCRIT corresponds to a critical value of the inversion coefficient where gm/ID transitions from strong inversion, square-law operation to velocity-saturated, linear-law operation. gm/ID is constant and maximum in weak inversion, decreases modestly in moderate inversion, and decreases as the inverse square-root of IC in strong inversion. When velocity saturation is significant for short-channel devices operating in strong inversion at high IC, gm/IDdecreases inversely with IC.gm/ID predicted in Fig. 2 by the simple hand prediction of Table 4 is within 5% of measured values, except at very high levels of inversion where IC > 65 [10]. As observed, gm/ID remains high in moderate inversion and is essentially unaffected by velocity saturation effects.

Normalized Drain-Source Conductance

Although a simple hand prediction of gm/ID from weak through strong inversion is available as verified in Fig. 2, no simple prediction of drain-source conductance, gds,or drain-source resistance, rds = 1/gds, is available. Table 4 shows the prediction of gds = ID/VA and rds = VA/IDfound in normalized form from the Early voltage, VA. As shown, VA can be found by VA = VAL (IC, L, VDS)L,where VAL = VA/L is an Early voltage factor or the Early voltage normalized to the channel length. It is important to note that VA and VAL are not fixed values for the process, but are complex functions of the inversion coefficient, and, especially, the channel length and drain-source voltage, VDS.Fig. 3 shows measured VA = (gds/ID)-1 for nMOS devices in the 0.18-m CMOS process operating at VDS = 0.5 V. Except for operation at short channel lengths and operation at high IC for all channel lengths, VA is nearly

independent of the inversion coefficient. Instead, VAincreases nearly directly with L.As seen in Fig. 3, VA for short-channel devices decreases in weak inversion because of drain-induced barrier lowering (DIBL). Here, the threshold voltage decrease with increasing VDS (listed in Table 1) results in significantly increased drain current and gds,corresponding to decreased VA. The DIBL effect is worse in weak inversion because the high gm/ID present maximizes the conversion of threshold voltage decrease with increasing VDS into increased drain current and gds.As observed, increasing the channel length only modestly from the process minimum significantly reduces the DIBL increase in gds and the corresponding decrease in VA. The DIBL effect decreases as approximately the inverse cube of increasing channel length [10]. The measured data of Fig. 3 shows that gds increases and, correspondingly, VA decreases at high levels of inversion where VDSAT begins to approach VDS = 0.5 V used in the measurements. This emphasizes the importance of VDS, where VDS must be well above VDSATto prevent a significant increase in gds or reduction in rdsthat can significantly decrease small-signal resistance levels and related signal gains in analog circuits [10]. Fig. 4 shows measured VA = (gds/ID)-1, this time versus the channel length for nMOS and pMOS devices in the 0.18-m CMOS process operating in saturation at VDS = 0.25, 0.5, and 1 V. Here, the nearly constant values of VA over the wide range of inversion coefficients seen in Fig. 3 and in additional measurements are averaged. Fig. 4 shows that VA increases rapidly as channel length increases from the process minimum. This is a result of the rapid decrease of DIBL effects with increasing channel length. For channel lengths modestly above the process minimum, VA increases sub-linearly with L for VDS = 0.25 V and increases nearly linearly with L at the higher VDS = 1 V. For a given channel length modestly above the process

1

10

100

0.01 0.1 1 10 100Inversion Coefficient, IC

Early

Vol

tage

, VA

(V

)

W.I.

Drops due to DIBL

L (m)

0.18

0.28

0.481

4

nMOS, 0.18 m processV DS = 0.5 V, V SB = 0 V

S.I.M.I.

0.38

2

V A = (g ds /I D )-1; g ds = I D /V ADecreases as V DSAT

approaches V DS

Fig. 3. Measured Early voltage, VA = (gds/ID)-1, for nMOS devices in a 0.18-m CMOS process operating at VDS = 0.5 V.

Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

1

10

100

0.1 1 10Channel Length, L (m)

Early

Vol

tage

, VA

(V

)

Decreases due to DIBL

0.18 m processV SB = 0 VV A is averaged as

described in text. 0.5 V

0.25 V

V DS =1 V

nMOS, diamondspMOS, triangles

V A = (g ds /I D )-1; g ds = I D /V A

L 0.73

L 0.79

L 0.39

L 0.43

L 1.1

L 1

Fig. 4. Measured Early voltage, VA = (gds/ID)-1, versus the channel length for nMOS and pMOS devices in a 0.18-m

CMOS process operating in saturation at VDS = 0.25, 0.5, and 1 V. Copyright John Wiley and Sons Limited. Reproduced

with permission from [10].

50

minimum, VA nearly doubles as VDS increases from 0.25 V to 0.5 V and nearly doubles again as VDSincreases from 0.5 V to 1 V. This corresponds to an approximate doubling and quadrupling of rds as VDSincreases from 0.25 V to 0.5 V and from 0.25 V to 1 V. This, again, emphasizes the importance of VDS.Unfortunately, low values of VDS required in low-voltage design result in significantly reduced VA and rds, corresponding to reduced small-signal resistance levels and related signal gains [10]. Fig. 5 shows the extracted Early voltage factor, VAL = VA/L, versus the channel length for nMOS and pMOS devices in the 0.18-m CMOS process operating in saturation at VDS = 0.25, 0.5, and 1 V. VAL is found from the measured VA data of Fig. 4. VAL peaks rapidly as channel length increases modestly from the process minimum because of the rapid decrease of DIBL effects. VAL then decreases with increasing channel length. Like VA shown in Fig. 4, VAL increases significantly with increasing values of VDS.Fig. 5 shows that the assumption of a fixed value of VAL for a CMOS process, for example at VAL = 10 V/m, results in significant errors in the prediction of VA and, correspondingly, gds and rds. VALvaries from approximately 3 40 V/m as channel length varies from 0.18 to 4 m and VDS varies from 0.25 to 1 V. The measurements shown in Figs. 3 5 illustrate the complex behavior of VA and, correspondingly, gds and rdsas a function of the inversion level and, especially, the channel length and drain-source voltage. The prediction of MOS gds and rds has a long history of significant modeling errors. Fortunately, the use of negative feedback in analog circuits helps mitigate errors in small-signal resistance levels and open-loop circuit gains resulting from errors in MOS gds and rds.Small-signal resistance levels and resulting open-loop gains are effectively squared in cascode circuits and cubed in regulated cascode circuits from device values of rds [10]. Thus for cascode circuits, open-loop gain is

increasingly sensitive to modelling errors in gds and rdsand to the effect of VDS as this decreases closer to VDSATin low-voltage design [10]. The measurement methodology shown in Figs. 3 5 provides an extensive evaluation of process gds and rdsfor analog design and provides a rigorous benchmark for evaluating MOS models.

Intrinsic Voltage Gain and Bandwidth

The intrinsic voltage gain, AVi, is the gate-to-drain voltage gain of a single MOS device having a grounded source and drain connected to a current-source load. AVi is the maximum voltage gain available for a single device and provides useful trend information for circuit gains. Table 5 gives an expression for AVi, which is independent of the drain current when expressed in terms of the inversion coefficient [9, 10]. The intrinsic bandwidth, fTi, is the unity-gain frequency for the gate-to-drain current gain of a single MOS device having a grounded source and drain. fTi is also related to the -3-dB frequency at the MOS source and at the drain of a diode-connected device. Table 5 gives an expression for fTi, which, like AVi, is independent of the drain current when expressed in terms of the inversion coefficient [9, 10]. Operating circuit bandwidths are lower than fTi,especially for short-channel devices that have small gate area and small intrinsic capacitances [10]. This is because fTi excludes the capacitive loading of extrinsic gate overlap capacitances and the drain-body and source-body junction capacitances. Although operating circuit bandwidths are lower, fTi provides useful trend information.

0

10

20

30

40

0.1 1 10Channel Length, L (m)

Early

Vol

tage

Fa

cto

r,

V AL

(V

/ m)

0.18 m processV SB = 0 VV AL is averaged per text.

V AL = V A /L

V DS = 1 V

0.5 V

0.25 V

nMOS, diamondspMOS, triangles

V A = (g ds /I D )-1; g ds = I D /V A

Fig. 5. Extracted Early voltage factor, VAL = VA/L, versus the channel length for nMOS and pMOS devices in a 0.18-m

CMOS process operating in saturation at VDS = 0.25, 0.5, and 1 V. Copyright John Wiley and Sons Limited. Reproduced

with permission from [10].

TABLE 5. Expressions for MOS intrinsic voltage gain, intrinsic bandwidth, and intrinsic gate capacitances.

ExpressionIntrinsic voltage gain1:

( )( )5.025.0,, ++ == ICnU LVLICVggA T DSALdsmViIntrinsic bandwidth1:

( )

( )

+

++

=

+=

20

5.025.0

2

LCCU

ICIC

CCgf

gbigsi

T

gbigsi

mTi

Instrinsic gate-source and gate-body capacitances:

'

0

2'

OXD

gsiOXgsigsi CII

ICLCWLCCC

==

'

0

2'

OXD

gbiOXgbigbi CII

ICLCWLCCC

==

where 32

31

30 ,, =gsiC and ( ) nngbiC 1313233 ,, = in W.I., M.I.,

and S.I. with continuous expressions given in [9,10]. 1Velocity saturation and VFMR effects can be approximated by

replacing IC with IC = IC(1+IC/ICCRIT) in the 25.0+ICterms related to gm/ID and gm.

51

Fig. 6 shows the tradeoffs between measured AVi at VDS = 1 V and predicted fTi for nMOS devices in the 0.18-m CMOS process. This illustrates the well-known gain and bandwidth tradeoffs for analog CMOS circuits. As IC increases in weak inversion, AVi remains nearly constant due to constant gm/ID, while fTi increases nearly directly with IC, due to the reduction of gate area and intrinsic gate capacitances. In strong inversion, AVidecreases as the inverse square-root of IC due to the decrease in gm/ID, while fTi increases as the square-root of IC because the decrease of gate area and intrinsic gate capacitances exceeds the decrease in gm/ID. Thus, in strong inversion, the product of AVi and fTi is nearly constant. However, velocity saturation effects present for short-channel devices at high IC cause AVi to decrease inversely with IC, due to the decrease in gm/ID,while fTi levels off. Although AVi and fTi are strong functions of IC, they are even stronger functions of L. When velocity saturation is negligible, AVi increases nearly directly with L, while fTi decreases as the inverse square of L. When velocity saturation is significant, AVi increases more rapidly with L, while fTi decreases as the inverse of L.

Intrinsic Gate Capacitances and Gate-Referred, Thermal Noise Voltage

Table 5 gives expressions for the intrinsic gate-source, Cgsi, and gate-body, Cgbi, capacitances. These track the total gate-oxide capacitance, CGOX = WLCOX, which tracks the gate area. The intrinsic gate-drain capacitance, Cgdi, is zero in saturation and is not included. Cgsi and Cgbi are required for the prediction of fTi described above and will be compared to the gate-referred, thermal-noise voltage density. Table 6 gives an expression for the gate-referred, thermal-noise voltage power spectral density (PSD), where is

the thermal noise factor, relating thermal noise to the operating transconductance in saturation [10]. Fig. 7 shows the tradeoffs between predicted intrinsic gate capacitances, Cgsi and Cgbi, and gate-referred, thermal-noise voltage density for nMOS devices in the 0.18-m CMOS process. Unlike gm/ID, VA, VAL, AVi, and fTi described above, the intrinsic gate capacitances and thermal noise depend on the drain current and are evaluated at ID = 100 A. As IC increases beyond weak inversion, the thermal-noise voltage density increases modestly because of the decrease of gm/ID and gm. The intrinsic gate capacitance, however, decreases significantly due primarily to the decrease in gate area.

0.01

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10 100

Inversion Coefficient, IC

Intr

insi

c B

andw

idth

, fTi

(M

Hz)

10

100

1000

10000

100000

1000000

10000000

100000000

Intr

ins

ic V

olta

ge G

ain,

AVi

(V

/V)

W. I. M. I. S. I.

0.18

0.48

L (m)

4

0.18

f Ti , solid

A Vi , dashed

nMOS, 0.18-m processL = 0.18, 0.28, 0.38, 0.48, 1, 2, 4 m

4

L (m)

Drops dueto DIBL

Levels offdue tovel. sat.

V DS = 1 V

Drops due to vel. sat.

Fig. 6. Tradeoffs between measured intrinsic voltage gain and predicted intrinsic bandwidth for nMOS devices in a 0.18-m

CMOS process. Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

TABLE 6. Expressions for MOS gate-referred, thermal noise, flicker noise, and voltage mismatch.

ExpressionGate-referred, thermal-noise voltage PSD1:

( ) ( )D

T

mVG I

ICUnkTg

nkTS 5.025.04)(42 ++

=

=

where = in W.I. and in S.I., excluding possible small-geometry increases, with full expression given in [10].

Gate-referred, flicker-noise voltage PSD: ( )

AFKFEFFF

DVG f

VVKII

LICfS

200

2/1)( +

=

Threshold voltage mismatch variance1:

( )

( )( )

+++

=

+=

2202

2122

5.025.0ICnUAAII

LIC

Ig

KKVV

TKPVTOD

D

m

P

PTOGS

1Velocity saturation and VFMR effects can be approximated by replacing IC with IC = IC(1+IC/ICCRIT) in the 25.0+ICterms related to gm/ID and gm.

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

100000

1000000

0.01 0.1 1 10 100

Inversion Coefficient, IC

Intr

insi

c G

ate

Capa

cita

nce,

C in

(fF

)

1

10

100

1000

Gat

e Th

erm

al-N

oise

Vo

ltage

Den

sity

, S V

G1/

2 (n

V/Hz

1/2 )

W. I. M. I. S.I.

0.18

4

C in = C gsi + C gbi , solid

nMOS, 0.18-m processL = 0.18, 0.28, 0.38, 0.48, 1, 2, 4 m

L (m)

0.48

S VG 1/2, dashed

I D = 100 A

0.18

4

Increases due tovel. sat. drop of g m

Fig. 7. Tradeoffs between predicted intrinsic gate capacitance and gate-referred, thermal-noise voltage density for nMOS devices in a 0.18-m CMOS process operating at a drain

current of 100 A. Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

52

The thermal noise is independent of the channel length, except for short-channel devices operating at high IC where the noise increases because of velocity saturation reductions of gm/ID and gm. Additionally, as noted in Table 6, the thermal noise may increase for short-channel devices due to a complex combination of small-geometry, channel-length modulation, VFMR, velocity saturation, and carrier heating effects with some compensation occurring among the effects [4, pp. 198-212]. The intrinsic gate capacitances, however, always depend strong on L, increasing as the square of L because of the significant increase in gate area.The intrinsic gate capacitances increase with the drain current, due to the increase in channel width and gate area. The gate-referred, thermal-noise voltage decreases as the inverse square-root of drain current, due to the increase in gm.

Gate-Referred, Flicker Noise Voltage and Gate-Source Mismatch Voltage

Table 6 gives an expression for the gate-referred, flicker-noise voltage PSD, where the increase associated with increasing inversion or VEFF = VGS-VT is modelled by a voltage, VKF [10]. As listed in Table 1, VKF is low for pMOS devices, modelling considerably more flicker noise increase with inversion compared to nMOS devices in the 0.18-m CMOS process [10]. Table 6 also gives the gate-source voltage mismatch variance associated with local-area mismatch. This mismatch increases some for non-zero VSB through increased threshold voltage mismatch, but this increase is small when VSB is limited to low values in low-voltage

designs [10]. Both the gate-referred, flicker-noise voltage PSD and threshold voltage mismatch variance are inversely proportional to the gate area, which is given by the prefix terms in the expressions. Fig. 8 shows the tradeoffs between predicted gate-referred, flicker-noise voltage density and gate-source mismatch voltage for nMOS devices in the 0.18-mCMOS process operating at ID = 100 A. The flicker-noise voltage density and mismatch voltage increase together as the square-root of IC, because gate area decreases inversely with IC. At high levels of IC, the flicker-noise voltage density increases further, especially for pMOS devices, because of the increase in flicker noise with inversion level [10]. At high levels of IC, the mismatch voltage increases further when transconductance factor mismatch dominates over threshold voltage mismatch [10]. The flicker-noise voltage density and gate-source mismatch voltage are strong functions of L, decreasing inversely with L because gate area increases as the square of L. These both decrease inversely with the square-root of drain current because the gate area increases directly with the drain current.

Drain-Referred, Flicker Noise Current and Drain Mismatch Current

Fig. 9 shows tradeoffs between predicted drain-referred, flicker-noise current density and drain mismatch current for nMOS devices in the 0.18-m CMOS process operating at ID = 100 A. The drain-referred values shown are found from the gate-referred values shown in Fig. 8 multiplied by the device transconductance given in Table 4.

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10 100

Inversion Coefficient, IC

Gat

e Fl

icke

r-N

oise

Vo

ltage

D

ensi

ty,

S VG

1/2 (n

V/Hz

1/2 )

0.1

1

10

100

1000

10000

100000

Gat

e-So

urce

Vo

ltage

Mis

mat

ch (1

),

VG

S (m

V)

W. I. M. I. S.I.

0.18

4

nMOS, 0.18-m processL = 0.18, 0.28, 0.38, 0.48, 1, 2, 4 m

L (m)

0.48

V GS , dashed

I D = 100 A

0.18

4

0.48

S VG 1/2, solid

L (m)

Fig. 8. Tradeoffs between predicted gate-referred, flicker-noise voltage density and gate-source mismatch voltage for nMOS devices in a 0.18-m CMOS process operating at a drain current of 100 A. Copyright John Wiley and Sons

Limited. Reproduced with permission from [10].

1

10

100

1000

10000

100000

0.01 0.1 1 10 100

Inversion Coefficient, IC

Dra

in F

licke

r-N

oise

Cu

rren

t Den

sity

,

S ID

1/2

(pA/

Hz1/

2 )

0.1

1

10

100

1000

10000D

rain

Cu

rre

nt M

ism

atc

h (1

), I D

/ I D (%

)

W. I. M. I. S.I.

0.18

0.48

L (m)

4 I D /I D , dashed

nMOS, 0.18-m processL = 0.18, 0.28, 0.38, 0.48, 1, 2, 4 m

0.18

4

I D = 100 A

0.48

S ID 1/2, solid

Drops dueto vel. sat.drop of g m

Fig. 9. Tradeoffs between predicted drain-referred, flicker-noise current density and drain mismatch current for nMOS

devices in a 0.18-m CMOS process operating at a drain current of 100 A. Copyright John Wiley and Sons Limited.

Reproduced with permission from [10].

53

In weak inversion where gm/ID and gm are constant at their maximum values, the flicker-noise current density and mismatch current increase together as the square-root of IC because the gate area decreases inversely with IC. Interestingly, in strong inversion, both the flicker-noise current density and mismatch current level off because the decrease in gm/ID and gm with increasing ICis countered by the increase in gate-referred, flicker-noise voltage and threshold voltage mismatch associated with decreasing gate area [9, 10]. However, at high levels of IC, the flicker-noise current density can decrease if velocity saturation reduces gm/ID and gm, or it can increase if inversion-level increases in the gate-referred, flicker noise voltage are significant as common for pMOS devices [10]. Finally, at high levels of IC, the mismatch current increases when transconductance factor mismatch dominates over threshold voltage mismatch [10]. The flicker-noise current density and drain mismatch current are strong functions of L, generally decreasing inversely with L because, again, gate area increases as the square of L. This behavior, however, is altered if velocity saturation effects or inversion level increases in the gate-referred, flicker noise voltage are present. The flicker-noise current density increases as the square-root of drain current because the increase in transconductance exceeds the decrease in gate-referred, flicker noise voltage due to increased gate area. The drain mismatch current, which is given as a relative mismatch current, decreases as the inverse square-root of drain current because the gate area increases directly with the drain current.

Additional Aspects of Analog Performance

All aspects of MOS device performance can be predicted and experimentally evaluated across the design choices of drain current, inversion coefficient, and channel length. Additional aspects of performance include the transconductance distortion, which is inversely proportional to gm/ID [10]. Additional aspects for performance are described in detail in [10].

Summary of Performance Tradeoffs

Qualitative performance tradeoffs associated with the selected inversion coefficient and channel length were shown in the MOSFET Operating Plane of Fig. 1. Here, operation at low inversion coefficients and long channel lengths in the upper, left portion of the plane results in a DC optimization giving maximum gm/ID, gm, AVi, and rds,combined with minimum flicker noise and local-area DC mismatch. Conversely, operation at high inversion coefficients and short channel lengths in the lower, right portion of the plane results in an AC optimization giving maximum fTi, combined with minimum W, WL,capacitances, and transconductance distortion. Fig. 10 illustrates numerical tradeoffs in performance versus the selected inversion coefficient. W, WL, gm/ID,gm, and AVi decrease as IC increases, while VDSAT, VEFF,and fTi increase. The figure shows that there is little or no advantage of operation in weak inversion where there is little increase in gm/ID, gm, and AVi, but a significant increase in W and WL, and a significant decrease in fTi.The figure also shows that fTi is maximum in strong inversion, but this comes at the expense of low gm/ID, gm,

Fig. 10. The MOS inversion coefficient presented as a number line showing tradeoffs in analog performance. When velocity saturation effects are significant for short-channel devices operating at high inversion, gm/ID, AVi, and fTi are reduced from the

relative values shown while VEFF is increased. Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

Inversion Coefficient

-163 mV -72 mV 40 mV 225 mV 724 mVVEFF

104 mV 108 mV 135 mV 243 mV 595 mVVDSAT

0.03x 0.23x 1x 3.4x 10.9xRel. fTi

97% 89% 63% 28% 9.7%Rel. gm/ID, AVi

Moderate inversionWeak inversion Strong inversion

0.01 0.1 1 10 100

High

Si

deW

eak

Inve

rsio

nSi

de

Stro

ngIn

vers

ion

Side

Cen

ter

Ons

et,

Low

Si

de

Heavy orDeepDeep

y Large device sizey Low bandwidthy No improvement in gm/ID, VDSATy High leakage current

y Moderate device sizey Moderate bandwidthy gm/ID moderately highy VEFF, VDSAT moderately lowy Little velocity saturationy Important for power-

efficient, low-voltagedesigns

y Small device sizey High bandwidthy gm/ID lowy VEFF, VDSAT highy Velocity saturation at short Ly Difficult for power-efficient, low-

voltage designs

Rel. W, WL100x 10x 1x 0.1x 0.01x

54

and AVi, combined with high VDSAT and VEFF that do not support low-voltage design. Finally, the figure shows that moderate inversion provides a compromise of moderate W, WL, gm/ID, gm, AVi, and fTi, combined with moderate values of VDSAT and VEFF that support low-voltage design. Inversion-coefficient based design that permits design freely in moderate inversion is important for modern, low-voltage design. Although bandwidth is reduced in moderate inversion compared to operation in strong inversion, velocity saturation effects are greatly reduced in moderate inversion and bandwidth is adequate for many applications. Additionally, VDSAT and VEFF are low as required for low-voltage design.

OPTIMIZING ANALOG DESIGN THROUGH THE SELECTION OF DRAIN CURRENT, INVERSION COEFFICIENT, AND CHANNEL LENGTH

Design Methodologies and EDA Tools

The preceding discussion of MOS performance tradeoffs over the design choices of drain current, inversion coefficient, and channel length provides insight that leads towards the optimum sizing of devices in analog circuits. The design methodologies discussed here have been previously reported [6 - 10] along with other methodologies [12 15]. Additionally, university electronic design automation (EDA) tools have been reported to aid the designer in the optimum selection of drain current, inversion coefficient, and channel length [8, 16]. Finally, commercial sizing EDA tools are available [17], including a tool that considers device mismatch [18]. These design methodologies and EDA

tools illustrate the importance and complexity of sizing MOS devices for optimum analog circuit performance. The graphical design tool reported earlier by the author and colleagues [8] shows performance tradeoffs, including device noise and mismatch, through vertical bar-graph displays. Additionally, this tool shows process variations and permits the assignment of performance goals where green, yellow, and red bar-graph displays correspond to goals met, marginally met, or not met. Although useful as an educational tool, this graphical design tool does not permit easy extension to user-defined circuits. The spreadsheet design tool illustrated here and described further in [10] does permit easy extension to user-defined circuits. This tool contains a MOSFETssheet giving MOS device geometry and performance for the selected drain current, inversion coefficient, and channel length. A Circuit Analysis sheet then contains user-defined circuit analysis equations, permitting easy extension to user-defined circuits.

Design of Three Cascoded OTAs Optimized for DC, Balanced, and AC Performance

The spreadsheet design tool will be used to illustrate the design of three cascoded operational transconductance amplifiers (OTAs) optimized for DC, balanced, and AC performance [10]. Fig. 11 shows a schematic diagram of the OTAs, with drain current, inversion coefficient, channel width, and channel length given for devices in the three versions. Drain currents are held constant to permit optimization at constant power consumption. The OTAs were fabricated in the 0.18-m CMOS process described in Table 1.

50 A 50 A

150 A150 A50 A

50 A50 A200 A

100 A100 A

50 A50 A

M15

VDD = +0.9 V

VIN+

VIN-

IBIAS

VBIAS1

VBIAS2VINCM

VOUT

M11 = (1/3)M3

M12 = M7

IC = 9W/L = 68.8/2

M3 = M4

M7 = M8

M9 = M10

M5 = M6

M1 = M2

M16 = M17 = (1/2)M1

M13 = M14 = (1/4)M15

MOSFET W/L in m/m given for DC, balanced, and AC optimized OTA

VSS = -0.9 V

M3 - M4, IC = ~16W/L = 122.4/2, 30/0.48, 11.4/0.18

M7 - M8, IC = ~2.5W/L = 168/1.4, 60/0.48, 22/0.18

M1 - M2, IC = ~0.8W/L = 352/2, 84.8/0.48, 32/0.18

M9 - M10, IC = ~2.5W/L = 36.8/1.4, 12.8/0.48, 4.8/0.18

M5 - M6, IC = ~16W/L = 8.8/2, 2.2/0.48, 0.8/0.18

Fig. 11. Schematic diagram of three cascoded OTAs optimized for DC, balanced, and AC performance.Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

55

Selection and Performance of MOS Devices. Fig. 12 shows an excerpt of the MOSFETs sheet from the spreadsheet design tool listing devices used in the OTAs [10]. This sheet shows drain current, inversion coefficient, and channel length selections and resulting MOS geometry and performance for the M1 and M2differential pair devices and the M3 and M4 current source devices. The sheet additionally includes columns not shown for the M5 and M6 current mirror devices and the M7 - M10 cascode devices, all of which govern the performance of the OTAs. The M1 and M2 input devices are operated at IC 0.8 near the center of moderate inversion for high gm/ID and gm. This minimizes their gate-referred thermal noise voltage as seen in Fig. 7 and helps ensure they dominate the overall OTA thermal noise. The M3 and M4 current

source devices and the M5 and M6 current mirror devices are operated at IC 16 well into strong inversion for low gm/ID and gm. This minimizes their drain-referred thermal noise current (having PSD of SID = 4kT(n)gm)such that the M1 and M2 input devices dominate the overall OTA thermal noise. The thermal noise current of the M3 M6 non-input devices is referred to an OTA input noise voltage by division by the input-pair transconductance, which is equal to gm of the M1 and M2input devices. The M7 - M10 cascode devices are operated at IC 2.5 in moderate inversion for low values of VDSAT, which maximizes the OTA output voltage swing. These devices influence the OTA output resistance, voltage gain, and transconductance bandwidth, but contribute negligible input-referred thermal noise, flicker noise,

Analog CMOS Design, Tradeoffs and Optimization Spreadsheet -- MOSFETs SheetFor design guidance only as results are approximate and not for any particular CMOS process. 2000 - 2007, David M. Binkley. See Disclaimer, Notes Sheet. ---------- Optional User Design Information ----------Description ------------ Input pair ------------ --- pMOS current source ---Device reference M1, M2 M1, M2 M1, M2 M3, M4 M3, M4 M3, M4Device notes DC BAL AC DC BAL AC ---------- Required User Design Inputs ----------Device model nMIL2 nMIL05 nMIL02 pSIL2 pSIL05 pSIL02I D A (+) 100 100 100 150 150 150IC (fixed normalized) 0.866 0.832 0.742 17.461 15.843 12.537L DRAWN m 1.98 0.48 0.18 1.98 0.48 0.18

---------- Calculated Results ---------- OK OK OK OK OK OK Effective Width, Length, Gate AreaW m 352.00 84.80 32.00 122.40 30.00 11.40L m 1.952 0.452 0.152 1.929 0.429 0.129WL m2 687.10 38.33 4.86 236.11 12.87 1.47 DC Bias VoltagesV EFF = V GS -V T V 0.032 0.030 0.024 0.298 0.285 0.258V T (adjusted for V SB ) V 0.420 0.420 0.420 0.420 0.420 0.420V GS = V T +V EFF V 0.452 0.450 0.444 0.718 0.705 0.678V DSAT V 0.133 0.132 0.130 0.301 0.290 0.267 Small Signal Parametersg m /I D S/A 19.50 19.66 20.08 6.37 6.57 6.97g m S 1949.59 1965.63 2008.14 955.51 985.33 1045.98V A V 17.93 8.13 2.27 7.91 3.20 1.50g ds S 5.5758 12.3038 44.0606 18.9688 46.8880 99.9052A Vi = g m /g ds V/V 349.7 159.8 45.6 50.4 21.0 10.5 Transcond. Distortion (Diff. Pair)V INDIF,1dB (input 1-dB comp.) V 0.072 0.071 0.071 0.271 0.261 0.244 Capacitances and BandwidthsC GS = C gsi +C GSO fF 2188.1 181.7 42.4 1236.3 81.8 14.3C GB = C gbi +C GBO fF 865.3 48.7 6.3 181.1 10.0 1.2C GD = C GDO (in saturation) fF 330.9 79.7 30.1 78.3 19.2 7.3C DB (at V DB = V DS +V SB ) fF 175.1 42.8 16.3 63.0 15.8 6.5f Ti = g m /[2(C gsi +C gbi )] MHz 114.0 2077.1 17139.3 113.6 2158.4 20299.9f T = g m /[2(C GS +C GB )] MHz 101.6 1358.2 6559.0 107.3 1707.2 10742.5f DIODE = g m /[2(C GS +C GB +C DB )], MHz 96.1 1145.4 4915.0 102.7 1456.3 7577.9 Thermal and Flicker NoiseS VG 1/2 thermal nV/Hz1/2 2.51 2.50 2.46 3.82 3.76 3.65S VG 1/2 flicker at f FLICKER nV/Hz1/2 37.24 157.39 439.44 73.77 308.42 865.93S ID 1/2 thermal pA/Hz1/2 4.90 4.91 4.95 3.65 3.71 3.82S ID 1/2 flicker at f FLICKER pA/Hz1/2 72.61 309.38 882.45 70.49 303.89 905.75f FLICKER , freq. for flicker noise Hz 100 100 100 100 100 100f c , flicker noise corner MHz 0.0569 1.7102 19.8233 0.0281 0.4415 3.3442 DC Mismatch for Device PairV GS (1) mV 0.19 0.82 2.31 0.38 1.63 4.75I D /I D (1) % 0.38 1.62 4.64 0.24 1.07 3.31

Fig. 12. Excerpt of the MOSFETs sheet in the spreadsheet design tool for the three OTAs showing drain current, inversion coefficient, and channel length selections and the resulting geometry and performance for the M1 and M2 input pair,

and M3 and M4 current source devices.

56

and offset voltage because they have significant resistive source degeneration. This significantly lowers the effective transconductance of these devices. For the DC, balanced, and AC optimized OTAs, only the channel lengths are changed. Long channel lengths of 2 m, moderate channel lengths of 0.48 m, and short channel lengths at the process minimum of 0.18 m are used for the DC, balanced, and AC optimized OTAs, respectively. Channel lengths for the M7 M10 cascode devices are decreased from 2 to 1.4 m for the DC optimized OTA to improve the transconductance bandwidth. The decrease of channel lengths across the DC, balanced, and AC optimized OTAs corresponds to a trajectory from the top to the bottom of the MOSFETOperating Plane shown in Fig. 1. Circuit Analysis and Performance. Fig. 13 shows an excerpt of the Circuit Analysis sheet from the spreadsheet design tool for the OTAs [10]. This sheet contains user-defined, circuit analysis equations that use

MOS device performance from the MOSFETs sheet shown in Fig. 12. As a result, circuit performance is immediately observed as the designer explores the selection of MOS device drain current, inversion coefficient, and channel length in the MOSFETs sheet. The Circuit Analysis sheet of Fig. 13 shows predicted OTA transconductance, GM, output resistance, ROUT,voltage gain, AV, transconductance bandwidth, f-3dB, and input-referred, thermal-noise voltage density, SVIN1/2(thermal). The input-referred, flicker-noise voltage density, SVIN1/2 (flicker), input-referred, offset voltage, VINOFFSET, input and output capacitances, input and output voltage ranges, and input, 1-dB compression point are also included in the Circuit Analysis sheet but not shown in the excerpt of Fig. 13 [10]. The Circuit Analysis sheet also includes measured and simulated performance to permit comparison with the predicted performance. Circuit performance for the OTAs is not derived here, but is listed in the Circuit Analysis sheet.

Summary of Predicted, Simulated, and Measured Performance for Three, 0.18-m OTA's

Transconductance, G MG M = g m 1[g ms 7/(g ms 7+g ds 1+g ds 3)]

DC Balanced ACPredicted 1,931 1,921 1,904 SSimulated 1,964 1,935 1,833 SMeasured 1,918 1,937 1,800 S

Output Resistance, R OUTR OUT = r outD 8 || r outD 10

DC Balanced ACPredicted 9.0 1.93 0.35 MSimulated 11.0 2.70 0.36 MMeasured 10.0 2.27 0.27 M

r outD 8 = r ds 8[1+g ms 8/(g ds 2+g ds 4)] 10.5 2.25 0.42 Mr outD 10 = r ds 10(1+g ms 10/g ds 6) 62.7 13.49 2.06 M

Voltage Gain, A VA V = G M R OUT = g m 1[g ms 7/(g ms 7+g ds 1+g ds 3)](r outD 8||r outD 10)

DC Balanced ACPredicted 17,353 3,702 661 V/VSimulated 21,600 5,230 662 V/VMeasured 19,100 4,400 490 V/V

Bandwidth, f-3dB

f-3dB f p 7 g m 7/[2(C GS 7+C SB 7+C DB 1+CGD 1+C DB 3+C GD 3)]

Pole at source of pMOS cascode devices, M 7 and M 8 DC Balanced ACPredicted 61 320 1075 MHzSimulated 76 286 860 MHz

Input-Referred Thermal Noise Voltage, S VIN 1/2 (thermal)S VIN 1/2 = Sqrt [{24kT (n )1/g m 1}(1+RNP 3+RNP 5)]

DC Balanced ACPredicted 4.7 4.7 4.6 nV/Hz1/2

Simulated nV/Hz1/2

Measured 5 5 nV/Hz1/2

Relative Noise Power (RNP ) -- relative to M 1, M 2DC Balanced AC

M 1, M 2 1 1 1 1M 3, M 4 RNP 3 = [(n )3/(n )1][g m 3/g m 1] 0.56 0.57 0.60M 5, M 6 RNP 5 = [(n )5/(n )1][g m 5/g m 1] 0.18 0.18 0.16Total: 1.74 1.75 1.76

Fig. 13. Excerpt of the Circuit Analysis sheet in the spreadsheet design tool for the three OTAs showing predicted performancefound from the MOSFETs sheet of Fig. 12. The Circuit Analysis sheet also includes simulated and measured performance.

Copyright John Wiley and Sons Limited. Reproduced with permission from [10].

57

The prediction of thermal noise includes the relative noise powers of non-input devices relative to the M1 and M2 input devices. These relative noise power contributions are denoted as RNP3 for M3 and M4, and RNP5 for M5 and M6 [10]. As listed in Fig. 13, the total relative noise power contribution is 1.75, indicating the OTA input-referred, thermal-noise voltage PSD is 175%, or the thermal-noise voltage density is 132% that of the M1 and M2 input devices. This analysis methodology allows the designer to quickly ensure that input devices dominate the thermal noise for low noise applications. A similar methodology is used for the analysis of input-referred, flicker noise voltage and offset voltage due to local-area mismatch but is not shown in the Fig. 13 excerpt [10]. Table 7 shows a summary of performance for the DC, balanced, and AC optimized OTAs [10]. All performance is measured except for the transconductance bandwidth that is simulated. Transconductance and input-referred, thermal noise voltage are nearly unchanged because MOS device drain currents and inversion coefficients are unchanged across the OTAs. The output resistance and voltage gain, however, are much higher for the DC optimized OTA because of long channel lengths and the squaring effect in the output resistance as a result of the cascoded output stage [10]. The transconductance bandwidth is higher for the AC optimized OTA because of short channel lengths. The expected tradeoffs between gain and bandwidth, shown for single MOS devices in Fig. 6, are clearly seen between the DC and AC optimized OTAs. These tradeoffs, however, are exaggerated by the squaring or cubing effect of output resistance and resulting gain present for cascode or regulated cascode circuits. The input-referred, flicker noise voltage and offset voltage due to local-area mismatch shown in Table 7 are lower for the DC optimized OTA because of its long channel lengths and resulting large gate areas. Fig. 14

shows measured and predicted input-referred noise voltage for the OTAs, where the noise is well predicted except for the under prediction of flicker noise for the AC optimized OTA [10]. Increased flicker noise for this OTA may be caused by increased damage at the silicon, silicon-dioxide interface in minimum channel length devices due to the fabrication of the nearby source and drains. This noise increase can be considered by increasing the flicker noise factor, KF0, for minimum channel length devices. As mentioned, predicted flicker noise is included in the Circuit Analysis sheet of the spreadsheet design tool but is not included in the excerpt of Fig. 13. Fig. 15 shows a histogram of measured input-referred offset voltage for the DC optimized OTA. The 1-offset of 0.24 mV corresponds to a 3- offset of 0.72 mV, which is unusually low for analog CMOS circuits. Measured 1- values of 0.24, 1.1, and 3.2 mV are conservatively below predicted values of 0.36, 1.5, and 4.2 mV for the DC, balanced, AC optimized OTAs [10]. As mentioned, predicted offset is included in the Circuit Analysis sheet of the spreadsheet design tool but is not included in the excerpt of Fig. 13.

TABLE 7. Summary of performance for the DC, balanced, and AC optimized OTAs. All performance is measured except for transconductance bandwidth that is simulated.

Performance DC BAL AC Units Transconductance,

GM1918 1937 1800 S

Ouput resistance, ROUT

10.0 2.3 0.27 M

Voltage gain, AV 19,100 4,400 490 V/V Transconductance

bandwidth, f-3dB76 286 890 MHz

Input-ref. thermal noise, SVG1/2

5 5 nV/Hz1/2

Input-ref. flicker noise, SVG1/2

96 420 1700 nV/Hz1/2(100 Hz)

Input-ref. offset voltage, VINOFFSET

0.24 1.1 3.2 mV (1 )

Layout area 20,800 2,800 1,900 m2Supply voltages,

VDD, VSS+0.9, -0.9 V

Power dissipation, PDISS

540 W

1

10

100

1000

10000

1 10 100 1000 10000 100000 1E+06 1E+07

Frequency (Hz)

Inpu

t-Refe

rred

Noise

Volta

ge (n

V/Hz

1/2 )

Balanced OTA

AC OTA

DC OTA

Triangles: Predicted Values

S/N 2T = 300 K

Fig. 14. Measured and predicted input-referred noise voltage for the three OTAs. Copyright John Wiley and Sons Limited.

Reproduced with permission from [10].

0

1

2

3

4

5

6

7

8

9

-

0.8-

0.7-

0.6-

0.5-

0.4-

0.3-

0.2-

0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

V INOFFSET (mV)

Nu

mbe

r of o

ccu

rren

ces

DC OTAMean: 0.05 mVStandard deviation: 0.24 mVT = 300 K

Fig. 15. Measured input-referred offset voltage for the DC optimized OTA. Copyright John Wiley and Sons Limited.

Reproduced with permission from [10].

58

Fig. 16 shows a photomicrograph of the OTAs with layout dimensions. The high output resistance and voltage gain, combined with low input-referred flicker noise voltage and offset voltage of the DC optimized OTA comes at the penalty of larger layout area. The layout area of the DC optimized OTA can be reduced some as observed by open area in the layout, but will still be well above that of the balanced and AC optimized OTAs.

EXTENSION OF METHODS TO SMALLER-GEOMETRY PROCESSES

Although tradeoffs and optimization of MOS device performance and OTA circuit performance were illustrated for a typical, 0.18-m, bulk CMOS process, the technology normalization inherent in the inversion coefficient readily permits extension of the design methods to smaller-geometry processes. The trends of MOS device performance generally remain unchanged, including the fundamental shape of the gm/ID curve shown in Fig. 2 [10]. Additionally, the simple hand predictions of MOS device performance included important small-geometry effects like the reduction of gm/ID due to velocity saturation and increases in the gate-referred, flicker noise with increasing inversion. Finally, the MOS device measurement methods allow the evaluation of all effects, including DIBL effects on gds shown in Figs. 3 5. Gate leakage current and the resulting gate-source conductance, gate mismatch current, and gate shot and flicker noise current can affect performance trends for gate-oxide thicknesses below approximately 2 nm [10]. When these effects are significant, DC performance is no longer optimized using arbitrarily long channel lengths and large gate areas. However, gate leakage effects, like all aspects of MOS performance, can be evaluated in terms of the selected drain current, inversion coefficient, and channel length [10]. This, again, enables the development of design expressions that guide the designer towards optimum design.

APPLICATION OF THE METHODS AND POTENTIAL FUTURE WORK

The hand predictions of MOS device performance and resulting circuit performance described here are often within measured values by 10%. This accuracy is typically obtained for operation from weak through strong inversion, inclusive of small geometry effects like velocity saturation reductions of gm/ID and inversion-level increases in flicker noise. Although the prediction accuracy is often encouraging, the hand predictions described here and included in the spreadsheet tool are intended only for initial design guidance. Such design guidance can provide design intuition, minimize trial-and-error simulations, reduce design time, and enhance the enjoyment of design. Extensive simulations using production MOS models are still required to evaluate a candidate design over process variations, temperature, and layout parasitics. Such MOS models, including process variations, could ultimately be mapped into the spreadsheet tool to improve the accuracy of predicted performance. Additionally, gate leakage effects could be included as well.

THE AUTHOR

Dr. David M. Binkley is with the Department of Electrical and Computer Engineering at the University of North Carolina at Charlotte, 9201 University City Boulevard, Charlotte, North Carolina, United States. e-mail: dmbinkle@uncc.edu.

ACKNOWLEDGEMENTS

The author thanks Helmut Graeb and Mariusz Orlikowski for their assistance with this paper and thanks Yannis Tsividis and Christian Enz for their interest in this work and encouragement. The author also thanks John Wiley and Sons Limited for permission to reproduce figures from [10].

REFERENCES

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[2] C. Enz, F. Krummenacher, and E. A. Vittoz, An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications, Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83-114, July 1995.

[3] M. Bucher, C. Lallement, C. Enz, F. Thodoloz, and F. Krummenacher, The EPFL-EKV MOSFET model equations for simulation, version 2.6, Technical Report, EPFL, July 1998, Revision II, on-line at http://legwww.epfl.ch/ekv/.

Fig. 16. Photomicrograph of the three OTAs. The layout area of the OTAs, especially the DC optimized OTA, could be reduced from the areas shown. Copyright John Wiley and

Sons Limited. Reproduced with permission from [10].

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[4] C. C. Enz and E. A. Vittoz, Charge-based MOS transistor modeling: The EKV model for low-power and RF IC design, John Wiley and Sons, 2006.

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[15] K. Antreich, J. Eckmller, H. Graeb, M. Pronath, F. Schenkel, R. Schwencker, and S. Zizala, WiCkeD: analog circuit synthesis incorporating mismatch, Proc. of the IEEE 2000 Custom Integrated Circuits Conference, pp. 511 514, May 2000.

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