© 2010 Altera Corporation—Public Quickly Master SDC (Synopsis Design Constraint) Timing Analysis...

© 2010 Altera Corporation—Public

Quickly Master SDC (Synopsis Design Constraint) Timing Analysis

2010 Technology Roadshow


ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Agenda

TimeQuest timing analyzer overview TimeQuest basic steps Using TimeQuest in the Quartus II design flow Summary

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TimeQuest Timing Analyzer Overview The TimeQuest analyzer

is the timing engine in the Quartus II software

Provides a timing analysis solution for all levels of user experience

Features Synopsys Design

Constraints (SDC) support Standardized constraint

methodology Easy-to-use interface

Constraint entry Standard reporting

Scripting emphasis Presentation focuses

on using GUI

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TimeQuest Analyzer GUI

Report Pane

Tasks Pane

Console Pane

View Pane

Menu Access to All TimeQuest Analyzer Features

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Basic Steps for Using the TimeQuest Analyzer

1. Generate a timing netlist

2. Enter SDC constraintsa. Create new, or input an existing SDC file

(recommended method)

orb. Constrain your design directly in the console

3. Update timing netlist

4. Generate timing reports

5. Save timing constraints (optional)

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1) Generate a Timing Netlist Create a timing netlist (database) based on compilation results

Post-synthesis (mapping) or post-fit (if design is already fully compiled) Timing models: worst-case (slow—highest operating temperature),

best-case (fast—lowest operating temperature) Set custom operating conditions (65 nm technology devices, military,

industrial, and so on.) To execute:

Netlist Menu Tasks Pane

Tcl Equivalent of Command

Tcl: create_timing_netlist

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2a) Create and Input Constraints Create SDC file using file editor

Do not enter constraints using Constraints menu

Input constraints and exceptions from existing SDC file Skip if no SDC file

Execution Read SDC File (Tasks pane or

Constraints menu)

File precedence (if no filename is specified) Files specifically added to Quartus® II

project <current_revision>.sdc

(if it exists in project directory)

Tcl: read_sdc [<filename>]

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2b) Constrain Directly in the Console

Apply new constraints directly to the netlist with console SDC commands or from the Constraints menu Not automatically added to the SDC file Not needed if all constraints are in the SDC file

Note: It is better to use an SDC file (step 2a) instead, to ease management and storage of constraints

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Using GUI to Enter Constraints Directly Most common constraints

can be accessed from the Constraints menu

Same as “Edit menu Insert Constraints” in SDC file editor

Use if unfamiliar with SDC syntax

Constraints Menu

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Constraining User must enter constraints for all paths, to fully

analyze design Timing analyzer only performs slack analysis on constrained

design paths Constraints guide the fitter to place and route the design to meet

timing requirements Recommendation: Constrain all paths (at least clocks and I/O)

Not as difficult a task as it may sound Wildcards help Single, generalized, constraints cover many paths, even all paths

in an entire clock domain

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3) Update Timing Netlist Apply SDC constraints/exceptions to current

timing netlist Generates warnings

Undefined clocks Partially defined I/O delays Combinatorial loops

Update timing netlist after adding any new constraint

Execution Update Timing Netlist (Tasks pane or Netlist menu)

Tcl: update_timing_netlist

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4) Generate Timing Reports Verify timing requirements

and locate violations Check for fully constrained

design or ignored timing constraints

Two methods Tasks pane

Shortcut: Automatically creates/updates netlist and reads default SDC file if needed

Reports menu Must have valid netlist to access

Double-Click on Individual Report

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“Out of Date” Reports Adding new constraints interactively in the

console causes current reports to be “out of date” Update timing netlist and regenerate reports

(Report pane, right-click menu) No such warning when using SDC file

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Reset Design Command

Tasks pane or Constraints menu Removes all timing constraints from current

timing netlist Functional Tcl equivalent: delete_timing_netlist

command followed by create_timing_netlist

Uses Re-starting timing analysis on same timing netlist, applying

different constraints or SDC file Re-starting analysis if previous results are questionable

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5) Save Timing Constraints (Optional) write_sdc command

Saves all constraints and exceptions applied to current netlist into SDC file

Use if constraints added during TimeQuest analyzer session using console instead of SDC file

Notes SDC files are generated by

TimeQuest analyzer only if requested Use -expand option (not in GUI) to

convert Altera-specific SDC commands (discussed later) into standard SDC

Run report_sdc command (console Tasks pane, or Report menu) to see what is written to the SDC file

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Basic Steps for Using TimeQuest Analyzer (Review)

1. Generate timing netlist

2. Enter SDC constraintsa. Create a new, or input an existing SDC file

(recommended method)

orb. Constrain design directly in console

3. Update timing netlist

4. Generate timing reports

5. Save timing constraints (optional)

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Agenda

TimeQuest overview TimeQuest basic steps Using TimeQuest in the Quartus II design flow Summary

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Using the TimeQuest Analyzer in the Quartus II Flow

Enable TimeQuest Analyzer in a Quartus II Project

Synthesize Quartus II Project

Use TimeQuest Analyzer to Specify Timing Requirements

Verify Timing inTimeQuest Analyzer

Perform Full Compilation(Run Fitter)

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Timing Requirements: Create Post-Map Netlist Follow the TimeQuest analyzer flow Use -post_map argument for synthesis-only

(mapping) netlist If design is already fully compiled,

choose -post_fit (default)

Tasks list command defaults to post-fit, so you must use Netlist menu in GUI

Zero IC delays auto-enabled with Post-map Quickly determines if it will be possible to meet best-case timing

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Timing Requirements: Enter Constraints

Three ways to enter constraints, in two locations SDC File Editor: Edit Insert Constraints submenu

(preferred method) Main TimeQuest analyzer window: Enter commands directly into

the console Main TimeQuest analyzer window: Enter commands directly into

the console using GUI dialog boxes in Constraints menu

Choose your method carefully!

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Using the TimeQuest Analyzer in the Quartus II Flow

Enable TimeQuest Analyzer in Quartus II Project

SynthesizeQuartus II Project




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Enable TimeQuest in Quartus II Software

Causes the Quartus II software to use SDC constraints during fitting

File order precedence1. Any SDC files manually added to Quartus II project (in order)

2. <current_revision>. SDC located in project directory

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Enabling the TimeQuest Analyzer in the Quartus II Software

Notes:•Arria GX and newer devices only support TimeQuest analyzer.

•TimeQuest analyzer is enabled by default for new Stratix III and Cyclone III designs.

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Quartus II TimeQuest Settings

Analyze and Fit for All Corners at the Same Time(Default “On” for Recent

Cyclone and Stratix Devices)

Select and Add SDC Files to List

(Evaluated in Order)

Assignments Settings

Report Worst-Case Paths in Quartus II

Compilation Report or Customize Reporting

with Script Advanced I/O Timing and Common Clock Path Pessimism (CCPP) removal discussed later

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Using TimeQuest TA in Quartus II Flow

Enable TimeQuest Analyzer in Quartus II Project

Synthesize Quartus II Project




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Verifying Timing Requirements View TimeQuest analyzer summary information directly, in

the Quartus II compilation report Open TimeQuest analyzer for a thorough analysis

Follow TimeQuest analyzer flow, selecting Post-fit netlistOptional: Enable Zero IC Delays to see if there is any chance of

meeting timing without having to enable optimization options Run TimeQuest easy-to-use reporting capabilities (Tasks pane) Many different reporting options available Place Tcl reporting commands into script file

Easy repetition

Verify whether the fitter was able to meet all timing requirements

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TimeQuest Analyzer Summary Reports in Compilation Report

• SDC Files Used During Fitting• Clocks Generated• Timing Violations• Unconstrained Paths

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Instructor-Led Training

With Altera's instructor-led training courses, you can:•Listen to a lecture from an Altera technical training engineer (instructor) •Complete hands-on exercises with guidance from an Altera instructor •Ask questions, and receive real-time answers, from an Altera instructor •Each instructor-led class is one or two days in length (eight working hours per day).

Online Training

With Altera's online training courses, you can:

• Take a course at any time that is convenient for you• Take a course from the comfort of your home or office (no need to travel as with instructor-led courses)

Each online course will take approximately one to three hours to complete.

http://www.altera.com/trainingView training class schedule and register for a class

Learn More Through Technical Training

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Summary (1/2)Timing analysis

2nd generation, easy-to-use timing analyzer

Complete GUI environment and scripting support for creating timing constraints and reports

Support for Synopsis Design Constraints (SDC)

Altera is the Only FPGA Vendor with Comprehensive SDC Support

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Summary (2/2): Top Five Reasons to Use the TimeQuest Timing Analyzer

Easier to use, and interactive: The TimeQuest analyzer provides an easier-to-use GUI, and interactive reporting for timing analysis

Industry standard: SDC format is an established industry standard Simpler and more concise timing format

More powerful: SDC allows for faster, easier, description and analysis of advanced design constructs

DDR (other source sync.), complex clocks

Designs run faster: TimeQuest precisely analyzes timing behavior; gain 3%-5% performance at 65 nm

Interoperability: Allows for easy migration of SDC constraints for ASIC and HardCopy ASIC designs

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Thank You!

For more information visit: www.altera.com

© 2010 Altera Corporation—Public Quickly Master SDC (Synopsis Design Constraint) Timing Analysis...

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